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| To all our customers Regarding the change of names mentioned in the document, such as Hitachi Electric and Hitachi XX, to Renesas Technology Corp. The semiconductor operations of Mitsubishi Electric and Hitachi were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.) Accordingly, although Hitachi, Hitachi, Ltd., Hitachi Semiconductors, and other Hitachi brand names are mentioned in the document, these names have in fact all been changed to Renesas Technology Corp. Thank you for your understanding. Except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. Renesas Technology Home Page: http://www.renesas.com Renesas Technology Corp. Customer Support Dept. April 1, 2003 Cautions Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corporation product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corporation or a third party. 2. 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H8S/2350 Series H8S/2351, HD6432351, H8S/2350, HD6412350 Hardware Manual ADE-602-111A Rev. 2.0 3/10/03 Hitachi, Ltd. MC-Setsu Notice When using this document, keep the following in mind: 1. This document may, wholly or partially, be subject to change without notice. 2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without Hitachi's permission. 3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other reasons during operation of the user's unit according to this document. 4. Circuitry and other examples described herein are meant merely to indicate the characteristics and performance of Hitachi's semiconductor products. Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein. 5. No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi, Ltd. 6. MEDICAL APPLICATIONS: Hitachi's products are not authorized for use in MEDICAL APPLICATIONS without the written consent of the appropriate officer of Hitachi's sales company. Such use includes, but is not limited to, use in life support systems. Buyers of Hitachi's products are requested to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL APPLICATIONS. Preface The H8S/2350 Series is a series of high-performance microcontrollers with a 32-bit H8S/2000 CPU core, and a set of on-chip supporting functions required for system configuration. The H8S/2000 CPU can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. The CPU can handle a 16 Mbyte linear address space (architecturally 4 Gbytes). Programs based on the high-level language C can also be run efficiently. The address space is divided into eight areas. The data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. On-chip memory consists of large-capacity ROM (H8S/2351 only) and RAM. On-chip supporting functions include a 16-bit timer pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. In addition, an on-chip DMA controller (DMAC) and data transfer controller (DTC) are provided, enabling high-speed data transfer without CPU intervention. Use of the H8S/2350 Series enables easy implementation of compact, high-performance systems capable of processing large volumes of data. This manual describes the hardware of the H8S/2350 Series. Refer to the H8S/2600 Series and H8S/2000 Series Programming Manual for a detailed description of the instruction set. Contents Section 1 1.1 1.2 1.3 Overview............................................................................................................ 1 Overview............................................................................................................................ 1 Block Diagram ................................................................................................................... 5 Pin Description................................................................................................................... 6 1.3.1 Pin Arrangement ................................................................................................... 6 1.3.2 Pin Functions in Each Operating Mode................................................................ 8 1.3.3 Pin Functions ........................................................................................................ 13 21 21 21 22 23 23 24 29 30 30 31 32 34 35 35 37 38 38 39 41 51 52 52 55 59 59 60 61 64 64 64 i Section 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 CPU ..................................................................................................................... Overview............................................................................................................................ 2.1.1 Features ................................................................................................................. 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU .................................. 2.1.3 Differences from H8/300 CPU ............................................................................. 2.1.4 Differences from H8/300H CPU .......................................................................... CPU Operating Modes ....................................................................................................... Address Space.................................................................................................................... Register Configuration ....................................................................................................... 2.4.1 Overview............................................................................................................... 2.4.2 General Registers.................................................................................................. 2.4.3 Control Registers .................................................................................................. 2.4.4 Initial Register Values .......................................................................................... Data Formats...................................................................................................................... 2.5.1 General Register Data Formats............................................................................. 2.5.2 Memory Data Formats.......................................................................................... Instruction Set .................................................................................................................... 2.6.1 Overview............................................................................................................... 2.6.2 Instructions and Addressing Modes...................................................................... 2.6.3 Table of Instructions Classified by Function........................................................ 2.6.4 Basic Instruction Formats ..................................................................................... Addressing Modes and Effective Address Calculation...................................................... 2.7.1 Addressing Mode.................................................................................................. 2.7.2 Effective Address Calculation .............................................................................. Processing States................................................................................................................ 2.8.1 Overview............................................................................................................... 2.8.2 Reset State ............................................................................................................ 2.8.3 Exception-Handling State ..................................................................................... 2.8.4 Program Execution State ...................................................................................... 2.8.5 Bus-Released State................................................................................................ 2.8.6 Power-Down State ................................................................................................ 2.9 Basic Timing...................................................................................................................... 2.9.1 Overview............................................................................................................... 2.9.2 On-Chip Memory (ROM, RAM).......................................................................... 2.9.3 On-Chip Supporting Module Access Timing ....................................................... 2.9.4 External Address Space Access Timing ............................................................... 65 65 65 67 68 Section 3 3.1 MCU Operating Modes................................................................................. 69 69 69 70 71 71 71 72 73 73 73 73 73 74 74 74 75 75 3.2 3.3 3.4 3.5 Overview............................................................................................................................ 3.1.1 H8S/2350 Operating Mode Selection ................................................................... 3.1.2 H8S/2351 Operating Mode Selection ................................................................... 3.1.3 Register Configuration.......................................................................................... Register Descriptions ......................................................................................................... 3.2.1 Mode Control Register (MDCR) .......................................................................... 3.2.2 System Control Register (SYSCR)....................................................................... Operating Mode Descriptions ............................................................................................ 3.3.1 Mode 1 .................................................................................................................. 3.3.2 Mode 2 (H8S/2351 Only) ..................................................................................... 3.3.3 Mode 3 (H8S/2351 Only) ..................................................................................... 3.3.4 Mode 4 .................................................................................................................. 3.3.5 Mode 5 .................................................................................................................. 3.3.6 Mode 6 (H8S/2351 Only) ..................................................................................... 3.3.7 Mode 7 (H8S/2351 Only) ..................................................................................... Pin Functions in Each Operating Mode ............................................................................. Memory Map in Each Operating Mode ............................................................................. Section 4 4.1 Exception Handling........................................................................................ 79 79 79 80 80 82 82 82 83 84 84 85 86 87 88 89 4.2 4.3 4.4 4.5 4.6 4.7 Overview............................................................................................................................ 4.1.1 Exception Handling Types and Priority................................................................ 4.1.2 Exception Handling Operation ............................................................................. 4.1.3 Exception Vector Table ........................................................................................ Reset................................................................................................................................... 4.2.1 Overview............................................................................................................... 4.2.2 Reset Types........................................................................................................... 4.2.3 Reset Sequence ..................................................................................................... 4.2.4 Interrupts after Reset............................................................................................. 4.2.5 State of On-Chip Supporting Modules after Reset Release.................................. Traces ................................................................................................................................. Interrupts ............................................................................................................................ Trap Instruction.................................................................................................................. Stack Status after Exception Handling .............................................................................. Notes on Use of the Stack.................................................................................................. ii Section 5 5.1 Interrupt Controller......................................................................................... 91 91 91 92 93 93 94 94 95 96 97 98 99 99 100 100 104 104 107 109 111 113 114 114 115 115 115 116 116 116 117 5.2 5.3 5.4 5.5 5.6 Overview............................................................................................................................ 5.1.1 Features ................................................................................................................. 5.1.2 Block Diagram...................................................................................................... 5.1.3 Pin Configuration.................................................................................................. 5.1.4 Register Configuration.......................................................................................... Register Descriptions ......................................................................................................... 5.2.1 System Control Register (SYSCR)....................................................................... 5.2.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................ 5.2.3 IRQ Enable Register (IER) ................................................................................... 5.2.4 IRQ Sense Control Registers H and L (ISCRH, ISCRL) ..................................... 5.2.5 IRQ Status Register (ISR) .................................................................................... Interrupt Sources................................................................................................................ 5.3.1 External Interrupts ................................................................................................ 5.3.2 Internal Interrupts.................................................................................................. 5.3.3 Interrupt Exception Handling Vector Table ......................................................... Interrupt Operation............................................................................................................. 5.4.1 Interrupt Control Modes and Interrupt Operation ................................................ 5.4.2 Interrupt Control Mode 0...................................................................................... 5.4.3 Interrupt Control Mode 2...................................................................................... 5.4.4 Interrupt Exception Handling Sequence ............................................................... 5.4.5 Interrupt Response Times ..................................................................................... Usage Notes ....................................................................................................................... 5.5.1 Contention between Interrupt Generation and Disabling ..................................... 5.5.2 Instructions that Disable Interrupts....................................................................... 5.5.3 Times when Interrupts are Disabled ..................................................................... 5.5.4 Interrupts during Execution of EEPMOV Instruction .......................................... DTC and DMAC Activation by Interrupt.......................................................................... 5.6.1 Overview............................................................................................................... 5.6.2 Block Diagram...................................................................................................... 5.6.3 Operation .............................................................................................................. Section 6 6.1 Bus Controller.................................................................................................. 119 119 119 121 122 123 124 124 125 126 130 iii 6.2 Overview............................................................................................................................ 6.1.1 Features ................................................................................................................. 6.1.2 Block Diagram...................................................................................................... 6.1.3 Pin Configuration.................................................................................................. 6.1.4 Register Configuration.......................................................................................... Register Descriptions ......................................................................................................... 6.2.1 Bus Width Control Register (ABWCR) ............................................................... 6.2.2 Access State Control Register (ASTCR).............................................................. 6.2.3 Wait Control Registers H and L (WCRH, WCRL) .............................................. 6.2.4 Bus Control Register H (BCRH) .......................................................................... 6.2.5 Bus Control Register L (BCRL) ........................................................................... 6.2.6 Memory Control Register (MCR) ........................................................................ 6.2.7 DRAM Control Register (DRAMCR).................................................................. 6.2.8 Refresh Timer/Counter (RTCNT) ........................................................................ 6.2.9 Refresh Time Constant Register (RTCOR).......................................................... 6.3 Overview of Bus Control ................................................................................................... 6.3.1 Area Partitioning................................................................................................... 6.3.2 Bus Specifications ................................................................................................ 6.3.3 Memory Interfaces................................................................................................ 6.3.4 Advanced Mode.................................................................................................... 6.3.5 Areas in Normal Mode.......................................................................................... 6.3.6 Chip Select Signals ............................................................................................... 6.4 Basic Bus Interface ............................................................................................................ 6.4.1 Overview............................................................................................................... 6.4.2 Data Size and Data Alignment.............................................................................. 6.4.3 Valid Strobes........................................................................................................ 6.4.4 Basic Timing......................................................................................................... 6.4.5 Wait Control.......................................................................................................... 6.5 DRAM Interface ................................................................................................................ 6.5.1 Overview............................................................................................................... 6.5.2 Setting DRAM Space............................................................................................ 6.5.3 Address Multiplexing............................................................................................ 6.5.4 Data Bus................................................................................................................ 6.5.5 Pins Used for DRAM Interface ............................................................................ 6.5.6 Basic Timing......................................................................................................... 6.5.7 Precharge State Control ........................................................................................ 6.5.8 Wait Control ......................................................................................................... 6.5.9 Byte Access Control ............................................................................................. 6.5.10 Burst Operation..................................................................................................... 6.5.11 Refresh Control..................................................................................................... 6.6 DMAC Single Address Mode and DRAM Interface ......................................................... 6.6.1 When DDS = 1...................................................................................................... 6.6.2 When DDS = 0...................................................................................................... 6.7 Burst ROM Interface.......................................................................................................... 6.7.1 Overview............................................................................................................... 6.7.2 Basic Timing......................................................................................................... 6.7.3 Wait Control.......................................................................................................... 6.8 Idle Cycle ........................................................................................................................... 6.8.1 Operation .............................................................................................................. 6.8.2 Pin States in Idle Cycle ......................................................................................... 6.9 Write Data Buffer Function ............................................................................................... 6.10 Bus Release........................................................................................................................ 6.10.1 Overview............................................................................................................... iv 132 134 137 140 140 141 141 142 143 144 145 146 147 147 147 149 150 158 160 160 160 160 161 161 162 163 164 166 168 171 174 174 175 176 176 176 178 179 179 183 184 185 185 6.10.2 Operation .............................................................................................................. 6.10.3 Pin States in External Bus Released State ............................................................ 6.10.4 Transition Timing ................................................................................................. 6.10.5 Usage Note............................................................................................................ 6.11 Bus Arbitration................................................................................................................... 6.11.1 Overview............................................................................................................... 6.11.2 Operation .............................................................................................................. 6.11.3 Bus Transfer Timing ............................................................................................. 6.11.4 External Bus Release Usage Note ........................................................................ 6.12 Resets and the Bus Controller............................................................................................ 185 186 187 188 188 188 188 189 189 190 191 191 191 192 193 195 196 197 198 199 199 200 205 211 211 211 212 213 217 222 222 225 226 227 227 230 233 236 240 243 246 252 v Section 7 7.1 7.2 7.3 7.4 7.5 DMA Controller .............................................................................................. Overview............................................................................................................................ 7.1.1 Features ................................................................................................................. 7.1.2 Block Diagram...................................................................................................... 7.1.3 Overview of Functions.......................................................................................... 7.1.4 Pin Configuration.................................................................................................. 7.1.5 Register Configuration.......................................................................................... Register Descriptions (1) (Short Address Mode) .............................................................. 7.2.1 Memory Address Registers (MAR)...................................................................... 7.2.2 I/O Address Register (IOAR) ............................................................................... 7.2.3 Execute Transfer Count Register (ETCR)............................................................ 7.2.4 DMA Control Register (DMACR) ....................................................................... 7.2.5 DMA Band Control Register (DMABCR) ........................................................... Register Descriptions (2) (Full Address Mode) ................................................................. 7.3.1 Memory Address Register (MAR)........................................................................ 7.3.2 I/O Address Register (IOAR) ............................................................................... 7.3.3 Execute Transfer Count Register (ETCR)............................................................ 7.3.4 DMA Control Register (DMACR) ....................................................................... 7.3.5 DMA Band Control Register (DMABCR) ........................................................... Register Descriptions (3) ................................................................................................... 7.4.1 DMA Write Enable Register (DMAWER)........................................................... 7.4.2 DMA Terminal Control Register (DMATCR) ..................................................... 7.4.3 Module Stop Control Register (MSTPCR)........................................................... Operation............................................................................................................................ 7.5.1 Transfer Modes ..................................................................................................... 7.5.2 Sequential Mode ................................................................................................... 7.5.3 Idle Mode.............................................................................................................. 7.5.4 Repeat Mode ......................................................................................................... 7.5.5 Single Address Mode............................................................................................ 7.5.6 Normal Mode........................................................................................................ 7.5.7 Block Transfer Mode............................................................................................ 7.5.8 DMAC Activation Sources ................................................................................... 7.6 7.7 Basic DMAC Bus Cycles...................................................................................... DMAC Bus Cycles (Dual Address Mode) ........................................................... DMAC Bus Cycles (Single Address Mode) ......................................................... Write Data Buffer Function .................................................................................. DMAC Multi-Channel Operation ......................................................................... Relation Between External Bus Requests, Refresh Cycles, the DTC, and the DMAC...................................................................................................... 7.5.15 NMI Interrupts and DMAC .................................................................................. 7.5.16 Forced Termination of DMAC Operation ............................................................ 7.5.17 Clearing Full Address Mode................................................................................. Interrupts ............................................................................................................................ Usage Notes ....................................................................................................................... 7.5.9 7.5.10 7.5.11 7.5.12 7.5.13 7.5.14 255 256 264 270 271 273 274 275 276 277 278 Section 8 8.1 Data Transfer Controller ............................................................................... 283 283 283 284 285 286 286 288 289 289 289 290 290 291 292 293 293 295 296 299 300 301 302 304 305 306 308 309 311 312 8.2 8.3 8.4 8.5 vi Overview............................................................................................................................ 8.1.1 Features ................................................................................................................. 8.1.2 Block Diagram...................................................................................................... 8.1.3 Register Configuration.......................................................................................... Register Descriptions ......................................................................................................... 8.2.1 DTC Mode Register A (MRA) ............................................................................. 8.2.2 DTC Mode Register B (MRB).............................................................................. 8.2.3 DTC Source Address Register (SAR) .................................................................. 8.2.4 DTC Destination Address Register (DAR) .......................................................... 8.2.5 DTC Transfer Count Register A (CRA) ............................................................... 8.2.6 DTC Transfer Count Register B (CRB)................................................................ 8.2.7 DTC Enable Registers (DTCER).......................................................................... 8.2.8 DTC Vector Register (DTVECR) ........................................................................ 8.2.9 Module Stop Control Register (MSTPCR)........................................................... Operation............................................................................................................................ 8.3.1 Overview............................................................................................................... 8.3.2 Activation Sources................................................................................................ 8.3.3 DTC Vector Table ................................................................................................ 8.3.4 Location of Register Information in Address Space............................................. 8.3.5 Normal Mode........................................................................................................ 8.3.6 Repeat Mode ......................................................................................................... 8.3.7 Block Transfer Mode............................................................................................ 8.3.8 Chain Transfer ...................................................................................................... 8.3.9 Operation Timing.................................................................................................. 8.3.10 Number of DTC Execution States ........................................................................ 8.3.11 Procedures for Using DTC.................................................................................... 8.3.12 Examples of Use of the DTC................................................................................ Interrupts ............................................................................................................................ Usage Notes ....................................................................................................................... Section 9 9.1 9.2 I/O Ports ............................................................................................................. Overview............................................................................................................................ Port 1.................................................................................................................................. 9.2.1 Overview............................................................................................................... 9.2.2 Register Configuration.......................................................................................... 9.2.3 Pin Functions ........................................................................................................ 9.3 Port 2.................................................................................................................................. 9.3.1 Overview............................................................................................................... 9.3.2 Register Configuration.......................................................................................... 9.3.3 Pin Functions ........................................................................................................ 9.4 Port 3.................................................................................................................................. 9.4.1 Overview............................................................................................................... 9.4.2 Register Configuration.......................................................................................... 9.4.3 Pin Functions ........................................................................................................ 9.5 Port 4.................................................................................................................................. 9.5.1 Overview............................................................................................................... 9.5.2 Register Configuration.......................................................................................... 9.5.3 Pin Functions ........................................................................................................ 9.6 Port 5.................................................................................................................................. 9.6.1 Overview............................................................................................................... 9.6.2 Register Configuration.......................................................................................... 9.6.3 Pin Functions ........................................................................................................ 9.7 Port 6.................................................................................................................................. 9.7.1 Overview............................................................................................................... 9.7.2 Register Configuration.......................................................................................... 9.7.3 Pin Functions ........................................................................................................ 9.8 Port A ................................................................................................................................. 9.8.1 Overview............................................................................................................... 9.8.2 Register Configuration.......................................................................................... 9.8.3 Pin Functions ........................................................................................................ 9.8.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 9.9 Port B ................................................................................................................................. 9.9.1 Overview............................................................................................................... 9.9.2 Register Configuration [H8S/2351 Only]............................................................. 9.9.3 Pin Functions ........................................................................................................ 9.9.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 9.10 Port C ................................................................................................................................. 9.10.1 Overview............................................................................................................... 9.10.2 Register Configuration [H8S/2351 Only]............................................................. 9.10.3 Pin Functions ........................................................................................................ 9.10.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 9.11 Port D ................................................................................................................................. 9.11.1 Overview............................................................................................................... 313 313 319 319 320 322 330 330 331 333 341 341 341 344 346 346 347 347 348 348 348 350 351 351 352 354 356 356 357 360 362 363 363 364 366 368 369 369 370 372 374 375 375 vii 9.11.2 Register Configuration [H8S/2351 Only]............................................................. 9.11.3 Pin Functions ........................................................................................................ 9.11.4 MOS Input Pull-Up Function [H8S/2351]............................................................ 9.12 Port E.................................................................................................................................. 9.12.1 Overview............................................................................................................... 9.12.2 Register Configuration.......................................................................................... 9.12.3 Pin Functions ........................................................................................................ 9.12.4 MOS Input Pull-Up Function [H8S/2351 Only] .................................................. 9.13 Port F.................................................................................................................................. 9.13.1 Overview............................................................................................................... 9.13.2 Register Configuration.......................................................................................... 9.13.3 Pin Functions ........................................................................................................ 9.14 Port G ................................................................................................................................. 9.14.1 Overview............................................................................................................... 9.14.2 Register Configuration.......................................................................................... 9.14.3 Pin Functions ........................................................................................................ 376 378 379 380 380 381 383 384 385 385 386 388 391 391 392 394 Section 10 16-Bit Timer Pulse Unit (TPU) .................................................................. 397 10.1 Overview............................................................................................................................ 10.1.1 Features ................................................................................................................. 10.1.2 Block Diagram...................................................................................................... 10.1.3 Pin Configuration.................................................................................................. 10.1.4 Register Configuration.......................................................................................... 10.2 Register Descriptions ......................................................................................................... 10.2.1 Timer Control Register (TCR).............................................................................. 10.2.2 Timer Mode Register (TMDR)............................................................................. 10.2.3 Timer I/O Control Register (TIOR)...................................................................... 10.2.4 Timer Interrupt Enable Register (TIER)............................................................... 10.2.5 Timer Status Register (TSR) ................................................................................ 10.2.6 Timer Counter (TCNT)......................................................................................... 10.2.7 Timer General Register (TGR) ............................................................................. 10.2.8 Timer Start Register (TSTR) ................................................................................ 10.2.9 Timer Synchro Register (TSYR) .......................................................................... 10.2.10 Module Stop Control Register (MSTPCR)........................................................... 10.3 Interface to Bus Master...................................................................................................... 10.3.1 16-Bit Registers .................................................................................................... 10.3.2 8-Bit Registers ...................................................................................................... 10.4 Operation............................................................................................................................ 10.4.1 Overview............................................................................................................... 10.4.2 Basic Functions..................................................................................................... 10.4.3 Synchronous Operation ........................................................................................ 10.4.4 Buffer Operation ................................................................................................... 10.4.5 Cascaded Operation .............................................................................................. viii 397 397 401 402 404 406 406 411 413 426 429 433 434 435 436 437 438 438 438 440 440 441 447 449 453 10.4.6 PWM Modes ......................................................................................................... 10.4.7 Phase Counting Mode ........................................................................................... 10.5 Interrupts ............................................................................................................................ 10.5.1 Interrupt Sources and Priorities ............................................................................ 10.5.2 DTC/DMAC Activation........................................................................................ 10.5.3 A/D Converter Activation..................................................................................... 10.6 Operation Timing ............................................................................................................... 10.6.1 Input/Output Timing ............................................................................................. 10.6.2 Interrupt Signal Timing ........................................................................................ 10.7 Usage Notes ....................................................................................................................... 455 460 467 467 469 469 470 470 474 478 Section 11 Programmable Pulse Generator (PPG) ..................................................... 489 11.1 Overview............................................................................................................................ 11.1.1 Features ................................................................................................................. 11.1.2 Block Diagram...................................................................................................... 11.1.3 Pin Configuration.................................................................................................. 11.1.4 Registers................................................................................................................ 11.2 Register Descriptions ......................................................................................................... 11.2.1 Next Data Enable Registers H and L (NDERH, NDERL) ................................... 11.2.2 Output Data Registers H and L (PODRH, PODRL) ............................................ 11.2.3 Next Data Registers H and L (NDRH, NDRL) .................................................... 11.2.4 Notes on NDR Access .......................................................................................... 11.2.5 PPG Output Control Register (PCR) .................................................................... 11.2.6 PPG Output Mode Register (PMR) ...................................................................... 11.2.7 Port 1 Data Direction Register (P1DDR).............................................................. 11.2.8 Port 2 Data Direction Register (P2DDR).............................................................. 11.2.9 Module Stop Control Register (MSTPCR)........................................................... 11.3 Operation............................................................................................................................ 11.3.1 Overview............................................................................................................... 11.3.2 Output Timing ...................................................................................................... 11.3.3 Normal Pulse Output ............................................................................................ 11.3.4 Non-Overlapping Pulse Output ............................................................................ 11.3.5 Inverted Pulse Output ........................................................................................... 11.3.6 Pulse Output Triggered by Input Capture............................................................. 11.4 Usage Notes ....................................................................................................................... 489 489 490 491 492 493 493 494 495 495 497 499 502 502 503 504 504 505 506 508 511 512 513 Section 12 Watchdog Timer.............................................................................................. 515 12.1 Overview............................................................................................................................ 12.1.1 Features ................................................................................................................. 12.1.2 Block Diagram...................................................................................................... 12.1.3 Pin Configuration.................................................................................................. 12.1.4 Register Configuration.......................................................................................... 12.2 Register Descriptions ......................................................................................................... 515 515 516 517 517 518 ix 12.2.1 Timer Counter (TCNT)......................................................................................... 12.2.2 Timer Control/Status Register (TCSR) ................................................................ 12.2.3 Reset Control/Status Register (RSTCSR) ............................................................ 12.2.4 Notes on Register Access...................................................................................... 12.3 Operation............................................................................................................................ 12.3.1 Watchdog Timer Operation .................................................................................. 12.3.2 Interval Timer Operation ...................................................................................... 12.3.3 Timing of Setting Overflow Flag (OVF).............................................................. 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF).......................... 12.4 Interrupts ............................................................................................................................ 12.5 Usage Notes ....................................................................................................................... 12.5.1 Contention between Timer Counter (TCNT) Write and Increment...................... 12.5.2 Changing Value of CKS2 to CKS0 ...................................................................... 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 12.5.4 System Reset by WDTOVF Signal ...................................................................... 12.5.5 Internal Reset in Watchdog Timer Mode ............................................................. 518 518 520 522 524 524 525 525 526 527 527 527 527 528 528 528 Section 13 Serial Communication Interface (SCI) ..................................................... 529 13.1 Overview............................................................................................................................ 13.1.1 Features ................................................................................................................. 13.1.2 Block Diagram...................................................................................................... 13.1.3 Pin Configuration.................................................................................................. 13.1.4 Register Configuration.......................................................................................... 13.2 Register Descriptions ......................................................................................................... 13.2.1 Receive Shift Register (RSR) ............................................................................... 13.2.2 Receive Data Register (RDR)............................................................................... 13.2.3 Transmit Shift Register (TSR).............................................................................. 13.2.4 Transmit Data Register (TDR).............................................................................. 13.2.5 Serial Mode Register (SMR) ................................................................................ 13.2.6 Serial Control Register (SCR) .............................................................................. 13.2.7 Serial Status Register (SSR) ................................................................................. 13.2.8 Bit Rate Register (BRR) ....................................................................................... 13.2.9 Smart Card Mode Register (SCMR)..................................................................... 13.2.10 Module Stop Control Register (MSTPCR)........................................................... 13.3 Operation............................................................................................................................ 13.3.1 Overview............................................................................................................... 13.3.2 Operation in Asynchronous Mode........................................................................ 13.3.3 Multiprocessor Communication Function ............................................................ 13.3.4 Operation in Clocked Synchronous Mode............................................................ 13.4 SCI Interrupts ..................................................................................................................... 13.5 Usage Notes ....................................................................................................................... 529 529 531 532 533 534 534 534 535 535 536 539 543 546 555 556 557 557 559 570 578 586 588 x Section 14 Smart Card Interface ...................................................................................... 593 14.1 Overview............................................................................................................................ 14.1.1 Features ................................................................................................................. 14.1.2 Block Diagram...................................................................................................... 14.1.3 Pin Configuration.................................................................................................. 14.1.4 Register Configuration.......................................................................................... 14.2 Register Descriptions ......................................................................................................... 14.2.1 Smart Card Mode Register (SCMR)..................................................................... 14.2.2 Serial Status Register (SSR) ................................................................................. 14.2.3 Serial Mode Register (SMR) ................................................................................ 14.2.4 Serial Control Register (SCR) .............................................................................. 14.3 Operation............................................................................................................................ 14.3.1 Overview............................................................................................................... 14.3.2 Pin Connections .................................................................................................... 14.3.3 Data Format .......................................................................................................... 14.3.4 Register Settings ................................................................................................... 14.3.5 Clock ..................................................................................................................... 14.3.6 Data Transfer Operations...................................................................................... 14.3.7 Operation in GSM Mode ...................................................................................... 14.4 Usage Notes ....................................................................................................................... 593 593 594 595 596 597 597 598 599 600 601 601 602 603 605 607 609 616 617 Section 15 A/D Converter.................................................................................................. 621 15.1 Overview............................................................................................................................ 15.1.1 Features ................................................................................................................. 15.1.2 Block Diagram...................................................................................................... 15.1.3 Pin Configuration.................................................................................................. 15.1.4 Register Configuration.......................................................................................... 15.2 Register Descriptions ......................................................................................................... 15.2.1 A/D Data Registers A to D (ADDRA to ADDRD).............................................. 15.2.2 A/D Control/Status Register (ADCSR) ................................................................ 15.2.3 A/D Control Register (ADCR) ............................................................................. 15.2.4 Module Stop Control Register (MSTPCR)........................................................... 15.3 Interface to Bus Master...................................................................................................... 15.4 Operation............................................................................................................................ 15.4.1 Single Mode (SCAN = 0) ..................................................................................... 15.4.2 Scan Mode (SCAN = 1)........................................................................................ 15.4.3 Input Sampling and A/D Conversion Time .......................................................... 15.4.4 External Trigger Input Timing.............................................................................. 15.5 Interrupts ............................................................................................................................ 15.6 Usage Notes ....................................................................................................................... 621 621 622 623 624 625 625 626 628 629 630 631 631 633 635 636 637 637 Section 16 D/A Converter.................................................................................................. 643 16.1 Overview............................................................................................................................ 643 xi 16.1.1 Features ................................................................................................................. 16.1.2 Block Diagram...................................................................................................... 16.1.3 Pin Configuration.................................................................................................. 16.1.4 Register Configuration.......................................................................................... 16.2 Register Descriptions ......................................................................................................... 16.2.1 D/A Data Registers 0 and 1 (DADR0, DADR1).................................................. 16.2.2 D/A Control Register (DACR) ............................................................................. 16.2.3 Module Stop Control Register (MSTPCR)........................................................... 16.3 Operation............................................................................................................................ 643 644 645 645 646 646 646 648 649 Section 17 RAM.................................................................................................................... 651 17.1 Overview............................................................................................................................ 17.1.1 Block Diagram...................................................................................................... 17.1.2 Register Configuration.......................................................................................... 17.2 Register Descriptions ......................................................................................................... 17.2.1 System Control Register (SYSCR)....................................................................... 17.3 Operation............................................................................................................................ 17.4 Usage Note ......................................................................................................................... 651 651 652 652 652 653 653 Section 18 ROM (H8S/2351 Only)................................................................................. 655 18.1 Overview............................................................................................................................ 655 18.1.1 Block Diagram...................................................................................................... 655 18.2 Operation............................................................................................................................ 656 Section 19 Clock Pulse Generator ................................................................................... 657 19.1 Overview............................................................................................................................ 19.1.1 Block Diagram...................................................................................................... 19.1.2 Register Configuration.......................................................................................... 19.2 Register Descriptions ......................................................................................................... 19.2.1 System Clock Control Register (SCKCR)............................................................ 19.3 Oscillator............................................................................................................................ 19.3.1 Connecting a Crystal Resonator............................................................................ 19.3.2 External Clock Input ............................................................................................. 19.4 Duty Adjustment Circuit.................................................................................................... 19.5 Medium-Speed Clock Divider ........................................................................................... 19.6 Bus Master Clock Selection Circuit................................................................................... 657 657 658 659 659 660 660 662 664 664 664 Section 20 Power-Down Modes ...................................................................................... 665 20.1 Overview............................................................................................................................ 20.1.1 Register Configuration.......................................................................................... 20.2 Register Descriptions ......................................................................................................... 20.2.1 Standby Control Register (SBYCR) ..................................................................... 20.2.2 System Clock Control Register (SCKCR)............................................................ xii 665 666 667 667 668 20.2.3 Module Stop Control Register (MSTPCR)........................................................... 20.3 Medium-Speed Mode......................................................................................................... 20.4 Sleep Mode ........................................................................................................................ 20.5 Module Stop Mode ............................................................................................................ 20.5.1 Module Stop Mode ............................................................................................... 20.5.2 Usage Notes .......................................................................................................... 20.6 Software Standby Mode..................................................................................................... 20.6.1 Software Standby Mode........................................................................................ 20.6.2 Clearing Software Standby Mode......................................................................... 20.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode ... 20.6.4 Software Standby Mode Application Example .................................................... 20.6.5 Usage Notes .......................................................................................................... 20.7 Hardware Standby Mode ................................................................................................... 20.7.1 Hardware Standby Mode ...................................................................................... 20.7.2 Hardware Standby Mode Timing ......................................................................... 20.8 o Clock Output Disabling Function ................................................................................... 669 670 671 671 671 672 673 673 673 674 674 675 676 676 676 677 Section 21 Electrical Characteristics .............................................................................. 679 21.1 Absolute Maximum Ratings .............................................................................................. 21.2 DC Characteristics ............................................................................................................. 21.3 AC Characteristics ............................................................................................................. 21.3.1 Clock Timing ........................................................................................................ 21.3.2 Control Signal Timing .......................................................................................... 21.3.3 Bus Timing ........................................................................................................... 21.3.4 DMAC Timing...................................................................................................... 21.3.5 Timing of On-Chip Supporting Modules.............................................................. 21.4 A/D Conversion Characteristics ........................................................................................ 21.5 D/A Convervion Characteristics ........................................................................................ 21.6 Usage Note ......................................................................................................................... 679 680 685 686 688 690 700 704 709 710 710 Appendix A Instruction Set............................................................................................... 711 A.1 A.2 A.3 A.4 A.5 A.6 Instruction List ................................................................................................................... Instruction Codes ............................................................................................................... Operation Code Map.......................................................................................................... Number of States Required for Instruction Execution....................................................... Bus States During Instruction Execution ........................................................................... Condition Code Modification ............................................................................................ 711 735 750 754 765 779 Appendix B Internal I/O Register ................................................................................... 785 B.1 B.2 Addresses ........................................................................................................................... 785 Functions............................................................................................................................ 794 xiii Appendix C I/O Port Block Diagrams........................................................................... 913 C.1 C.2 C.3 C.4 C.5 C.6 C.7 C.8 C.9 C.10 C.11 C.12 C.13 Port 1 Block Diagram ........................................................................................................ Port 2 Block Diagram ........................................................................................................ Port 3 Block Diagram ........................................................................................................ Port 4 Block Diagram ........................................................................................................ Port 5 Block Diagram ........................................................................................................ Port 6 Block Diagram ........................................................................................................ Port A Block Diagram........................................................................................................ Port B Block Diagram........................................................................................................ Port C Block Diagram........................................................................................................ Port D Block Diagram........................................................................................................ Port E Block Diagram........................................................................................................ Port F Block Diagram ........................................................................................................ Port G Block Diagram........................................................................................................ 913 916 917 920 921 923 929 935 937 939 941 943 951 Appendix D Pin States........................................................................................................ 955 D.1 D.2 Port States in Each Mode [H8S/2351] ............................................................................... 955 Port States in Each Mode [H8S/2350] ............................................................................... 959 Appendix E Pin States at Power-On .............................................................................. 962 E.1 E.2 When Pins Settle from an Indeterminate State at Power-On ............................................. 962 When Pins Settle from the High-Impedance State at Power-On ....................................... 963 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode............................................................................................... 964 Appendix G Product Code Lineup.................................................................................. 965 Appendix H Package Dimensions................................................................................... 966 xiv Section 1 Overview 1.1 Overview The H8S/2350 Series is a series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Hitachi's proprietary architecture, and equipped with peripheral functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space. The instruction set is upward-compatible with H8/300 and H8/300H CPU instructions at the object-code level, facilitating migration from the H8/300, H8/300L, or H8/300H Series. On-chip peripheral functions required for system configuration include DMA controller (DMAC) and data transfer controller (DTC) bus masters, ROM (H8S/2351 only) and RAM memory, a16-bit timer-pulse unit (TPU), programmable pulse generator (PPG), watchdog timer (WDT), serial communication interface (SCI), A/D converter, D/A converter, and I/O ports. The H8S/2351 has on-chip mask ROM. The H8S/2351 supports seven operating modes (modes 1 to 7), while the H8S/2350 supports three operating modes (modes 1, 4, and 5). There is a choice of address space and single-chip mode or expansion mode. The features of the H8S/2350 Series are shown in Table 1-1. 1 Table 1-1 Item CPU Overview Specification * General-register machine Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * High-speed operation suitable for realtime control Maximum clock rate: 20 MHz High-speed arithmetic operations 8/16/32-bit register-register add/subtract : 50 ns 16 x 16-bit register-register multiply 32 / 16-bit register-register divide * Sixty-five basic instructions 8/16/32-bit move/arithmetic and logic instructions Unsigned/signed multiply and divide instructions Powerful bit-manipulation instructions * Two CPU operating modes Normal mode Advanced mode : 64-kbyte address space : 16-Mbyte address space : 1000 ns : 1000 ns Instruction set suitable for high-speed operation Bus controller * * * * * * * * Address space divided into 8 areas, with bus specifications settable independently for each area Chip select output possible for each area Choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area Number of program wait states can be set for each area Burst ROM directly connectable Maximum 8-Mbyte DRAM directly connectable (or use of interval timer possible) External bus release function Choice of short address mode or full address mode 4 channels in short address mode 2 channels in full address mode Transfer possible in repeat mode, block transfer mode, etc. Single address mode transfer possible Can be activated by internal interrupt DMA controller (DMAC) * * * * * * 2 Table 1-1 Item Overview (cont) Specification * * * * Can be activated by internal interrupt or software Multiple transfers or multiple types of transfer possible for one activation source Transfer possible in repeat mode, block transfer mode, etc. Request can be sent to CPU for interrupt that activated DTC 6-channel 16-bit timer on-chip Pulse I/O processing capability for up to 16 pins' Automatic 2-phase encoder count capability Maximum 16-bit pulse output possible with TPU as time base Output trigger selectable in 4-bit groups Non-overlap margin can be set Direct output or inverse output setting possible Watchdog timer or interval timer selectable Asynchronous mode or synchronous mode selectable Multiprocessor communication function Smart card interface function Resolution: 10 bits Input: 8 channels High-speed conversion : 6.7 s minimum conversion time (at 20 MHz operation) Single or scan mode selectable Sample and hold circuit A/D conversion can be activated by external trigger or timer trigger Resolution: 8 bits Output: 2 channels 87 I/O pins, 8 input-only pins Mask ROM High-speed static RAM ROM -- 64 kbytes RAM 2 kbytes 2 kbytes Data transfer controller (DTC) 16-bit timer-pulse unit (TPU) * * * * * * * * * * * * * * * * * Programmable pulse generator (PPG) Watchdog timer Serial communication interface (SCI) 2 channels A/D converter D/A converter I/O ports Memory * * * * * Product Name H8S/2350 H8S/2351 Interrupt controller * * * Nine external interrupt pins (NMI, IRQ0 to IRQ7) 42 internal interrupt sources Eight priority levels settable 3 Table 1-1 Item Overview (cont) Specification * * * * * Medium-speed mode Sleep mode Module stop mode Software standby mode Hardware standby mode Power-down state Operating modes Seven MCU operating modes CPU Operating Mode Mode Description 1 2* 3* 4 5 6* 7* * * * Normal On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode Advanced On-chip ROM disabled expansion mode On-chip ROM disabled expansion mode On-chip ROM enabled expansion mode Single-chip mode External Data Bus On-Chip Initial ROM Value Disabled 8 bits Enabled 8 bits Enabled -- Disabled 16 bits Disabled 8 bits Enabled 8 bits Enabled -- 16 bits 16 bits 16 bits Maximum Value 16 bits 16 bits Note: * Only applies to the H8S/2351. Clock pulse generator Packages Built-in duty correction circuit 120-pin plastic TQFP (TFP-120) 128-pin plastic QFP (FP-128) Model Name ROMless Version -- HD6412350 Mask ROM Version HD6432351 -- ROM/RAM (Bytes) 64 k/2 k --/2 k Packages TFP-120 FP-128 TFP-120 FP-128 Product lineup 4 1.2 Block Diagram Figure 1-1 shows an internal block diagram of the H8S/2350 Series. PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 Port E VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS VSS Port D Internal data bus H8S/2000 CPU Internal address bus Bus controller MD2 MD1 MD0 EXTAL XTAL STBY RES WDTOVF NMI Port A Clock pulse generator PA7 /A23 / IRQ7 PA6 /A22 / IRQ6 PA5 /A21 / IRQ5 PA4 /A20 / IRQ4 PA3 /A19 PA2 /A18 PA1 /A17 PA0 /A16 PB7 /A15 PB6 /A14 PB5 /A13 PB4 /A12 PB3 / A11 PB2 /A10 PB1 /A9 PB0 /A8 PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 P50 P51 P52 P53 /ADTRG Interrupt controller PF7 / o PF6 / AS PF5 / RD PF4 / HWR PF3 / LWR PF2 / WAIT /LCAS/ BREQO PF1 / BACK PF0 / BREQ PG4 / CS0 PG3 / CS1 PG2 / CS2 PG1 / CS3 PG0 / CAS P67 / CS7/ IRQ3 P66 / CS6/ IRQ2 P65 / IRQ1 P64 / IRQ0 P63 / TEND1 P62 / DREQ1 P61 / TEND0/ CS5 P60 / DREQ0/ CS4 DTC Port B Peripheral address bus Peripheral data bus ROM* Port F DMAC Port C RAM Port G WDT SCI Port 3 TPU D/A converter Port 6 PPG A/D converter Port 5 Port 1 Port 2 Port 4 P10 /PO8/TIOCA0/ DACK0 P11 /PO9/TIOCB0/ DACK1 P12 / PO10/TIOCC0/TCLKA P13 / PO11/TIOCD0/TCLKB P14 /PO12/TIOCA1 P15 / PO13/TIOCB1/TCLKC P16 /PO14/TIOCA2 P17 / PO15/TIOCB2/TCLKD P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3 P23 /PO3/TIOCD3 P24 /PO4/TIOCA4 P25 /PO5/TIOCB4 P26 /PO6/TIOCA5 P27 /PO7/TIOCB5 Note: * Only applies to the H8S/2351. Figure 1-1 Block Diagram 5 P47 /AN7/DA1 P46 /AN6/DA0 P45 /AN5 P44 /AN4 P43 /AN3 P42 /AN2 P41 /AN1 P40 /AN0 Vref AVCC AVSS 1.3 1.3.1 Pin Description Pin Arrangement Figures 1-2 and 1-3 show the pin arrangement of the H8S/2350 Series. P51 P50 PF0 /BREQ PF1 /BACK PF2 /LCAS/WAIT /BREQO PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 /o VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3 P23 /PO3/TIOCD3 P24 /PO4/TIOCA4 P25 /PO5/TIOCB4 P26 /PO6/TIOCA5 P27 /PO7/TIOCB5 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 Figure 1-2 Pin Arrangement (TFP-120: Top View) 6 VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 /IRQ4 PA5 /A21 /IRQ5 PA6 /A22 /IRQ6 PA7 /A23 /IRQ7 P67 /CS7/IRQ3 P66 /CS6/IRQ2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P52 P53 / ADTRG AVCC Vref P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6/ DA0 P47 / AN7/ DA1 AVSS VSS P17 / PO15/ TIOCB2 / TCLKD P16 / PO14/ TIOCA2 P15 / PO13/ TIOCB1 / TCLKC P14 / PO12/ TIOCA1 P13 / PO11/ TIOCD0 / TCLKB P12 / PO10/ TIOCC0 / TCLKA P11 / PO9/ TIOCB0 /DACK1 P10 / PO8/ TIOCA0 /DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 PG3 / CS1 PG4 / CS0 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 P60 / DREQ0/ CS4 VSS P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC P64 / IRQ0 P65 / IRQ1 AVCC Vref P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6/ DA0 P47 / AN7/ DA1 AVSS VSS P17 / PO15/ TIOCB2 / TCLKD P16 / PO14/ TIOCA2 P15 / PO13/ TIOCB1 / TCLKC P14 / PO12/ TIOCA1 P13 / PO11/ TIOCD0 / TCLKB P12 / PO10/ TIOCC0 / TCLKA P11 / PO9/ TIOCB0 / DACK1 P10 / PO8/ TIOCA0 / DACK0 MD0 MD1 MD2 PG0 / CAS PG1 / CS3 PG2 / CS2 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Figure 1-3 Pin Arrangement (FP-128: Top View) PG3 /CS1 PG4 /CS0 VSS NC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 /IRQ4 PA5 /A21 /IRQ5 PA6 /A22 /IRQ6 PA7 /A23 /IRQ7 P67 /CS7/IRQ3 P66 /CS6/IRQ2 VSS VSS P65 /IRQ1 P64 /IRQ0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 P35 / SCK1 P34 / SCK0 P33 / RxD1 P32 / RxD0 P31 / TxD1 P30 / TxD0 VCC PD7 / D15 PD6 / D14 PD5 / D13 PD4 / D12 VSS PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 PE7 / D7 PE6 / D6 PE5 / D5 PE4 / D4 VSS PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 VCC 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 P53 /ADTRG P52 VSS VSS P51 P50 PF0 /BREQ PF1 /BACK PF2 /LCAS/WAIT/BREQO PF3 /LWR PF4 /HWR PF5 /RD PF6 /AS VCC PF7 /o VSS EXTAL XTAL VCC STBY NMI RES WDTOVF P20 /PO0/TIOCA3 P21 /PO1/TIOCB3 P22 /PO2/TIOCC3 P23 /PO3/TIOCD3 P24 /PO4/TIOCA4 P25 /PO5/TIOCB4 P26 /PO6/TIOCA5 P27 /PO7/TIOCB5 P63 /TEND1 P62 /DREQ1 P61 /TEND0/CS5 VSS VSS P60 /DREQ0/CS4 VSS 7 1.3.2 Pin Functions in Each Operating Mode Table 1-2 shows the pin functions of the H8S/2350 Series in each of the operating modes. Table 1-2 Pin No. TFP-120 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 FP-128 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Mode 1 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 PA 0 PA 1 PA 2 PA 3 VSS PA 4/IRQ4 PA 5/IRQ5 PA 6/IRQ6 Mode 2* VCC PC0/A 0 PC1/A 1 PC2/A 2 PC3/A 3 VSS PC4/A 4 PC5/A 5 PC6/A 6 PC7/A 7 PB 0/A 8 PB 1/A 9 PB 2/A 10 PB 3/A 11 VSS PB 4/A 12 PB 5/A 13 PB 6/A 14 PB 7/A 15 PA 0 PA 1 PA 2 PA 3 VSS PA 4/IRQ4 PA 5/IRQ5 PA 6/IRQ6 Mode 3* VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB 0 PB 1 PB 2 PB 3 VSS PB 4 PB 5 PB 6 PB 7 PA 0 PA 1 PA 2 PA 3 VSS PA 4/IRQ4 PA 5/IRQ5 PA 6/IRQ6 Pin Functions in Each Operating Mode Pin Name Mode 4 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA 5/A 21 / IRQ5 PA 6/A 22 / IRQ6 Mode 5 VCC A0 A1 A2 A3 VSS A4 A5 A6 A7 A8 A9 A10 A11 VSS A12 A13 A14 A15 A16 A17 A18 A19 VSS A20 PA 5/A 21 / IRQ5 PA 6/A 22 / IRQ6 Mode 6* VCC PC0/A 0 PC1/A 1 PC2/A 2 PC3/A 3 VSS PC4/A 4 PC5/A 5 PC6/A 6 PC7/A 7 PB 0/A 8 PB 1/A 9 PB 2/A 10 PB 3/A 11 VSS PB 4/A 12 PB 5/A 13 PB 6/A 14 PB 7/A 15 PA 0/A 16 PA 1/A 17 PA 2/A 18 PA 3/A 19 VSS PA 4/A 20 / IRQ4 PA 5/A 21 / IRQ5 PA 6/A 22 / IRQ6 Mode 7* VCC PC0 PC1 PC2 PC3 VSS PC4 PC5 PC6 PC7 PB 0 PB 1 PB 2 PB 3 VSS PB 4 PB 5 PB 6 PB 7 PA 0 PA 1 PA 2 PA 3 VSS PA 4/IRQ4 PA 5/IRQ5 PA 6/IRQ6 8 Table 1-2 Pin No. TFP-120 28 29 30 -- -- 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Pin Functions in Each Operating Mode (cont) Pin Name Mode 1 PA 7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 2* PA 7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 3* PA 7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0 PE 1 PE 2 PE 3 VSS PE 4 PE 5 PE 6 PE 7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 4 PA 7/A 23 / IRQ7 P67/IRQ3/ CS7 P66/IRQ2/ CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 5 PA 7/A 23 / IRQ7 P67/IRQ3/ CS7 P66/IRQ2/ CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 6* PA 7/A 23 / IRQ7 P67/IRQ3/ CS7 P66/IRQ2/ CS6 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0/D0 PE 1/D1 PE 2/D2 PE 3/D3 VSS PE 4/D4 PE 5/D5 PE 6/D6 PE 7/D7 D8 D9 D10 D11 VSS D12 D13 D14 D15 VCC P30/TxD0 P31/TxD1 P32/RxD0 Mode 7* PA 7/IRQ7 P67/IRQ3 P66/IRQ2 VSS VSS P65/IRQ1 P64/IRQ0 VCC PE 0 PE 1 PE 2 PE 3 VSS PE 4 PE 5 PE 6 PE 7 PD0 PD1 PD2 PD3 VSS PD4 PD5 PD6 PD7 VCC P30/TxD0 P31/TxD1 P32/RxD0 FP-128 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 9 Table 1-2 Pin No. TFP-120 56 57 58 59 60 Pin Functions in Each Operating Mode (cont) Pin Name Mode 1 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI Mode 2* P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI Mode 3* P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI Mode 4 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ CS4 VSS VSS P61/ TEND0/ CS5 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI Mode 5 P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ CS4 VSS VSS P61/ TEND0/ CS5 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI Mode 6* P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0/ CS4 VSS VSS P61/ TEND0/ CS5 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI Mode 7* P33/RxD1 P34/SCK0 P35/SCK1 VSS P60/ DREQ0 VSS VSS P61/ TEND0 P62/ DREQ1 P63/ TEND1 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 WDTOVF RES NMI FP-128 62 63 64 65 66 -- -- 61 67 68 69 62 63 64 65 66 67 68 69 70 71 72 73 74 70 71 72 73 74 75 76 77 78 79 80 81 82 10 Table 1-2 Pin No. TFP-120 75 76 77 78 79 80 81 82 83 84 85 86 Pin Functions in Each Operating Mode (cont) Pin Name Mode 1 STBY VCC XTAL EXTAL VSS PF7/o VCC AS RD HWR LWR Mode 2* STBY VCC XTAL EXTAL VSS PF7/o VCC AS RD HWR LWR Mode 3* STBY VCC XTAL EXTAL VSS PF7/o VCC PF6 PF5 PF4 PF3 Mode 4 STBY VCC XTAL EXTAL VSS PF7/o VCC AS RD HWR LWR Mode 5 STBY VCC XTAL EXTAL VSS PF7/o VCC AS RD HWR LWR Mode 6* STBY VCC XTAL EXTAL VSS PF7/o VCC AS RD HWR LWR Mode 7* STBY VCC XTAL EXTAL VSS PF7/o VCC PF6 PF5 PF4 PF3 FP-128 83 84 85 86 87 88 89 90 91 92 93 94 PF2/WAIT/ PF2/WAIT/ PF2 BREQO BREQO PF1/BACK PF1/BACK PF1 PF2/LCAS/ PF2/LCAS/ PF2/LCAS/ PF2 WAIT/ WAIT/ WAIT/ BREQO BREQO BREQO PF1/BACK PF1/BACK PF1/BACK PF1 87 88 89 90 -- -- 91 92 93 94 95 96 97 98 99 100 101 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 PF0/BREQ PF0/BREQ PF0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 PF0/BREQ PF0/BREQ PF0/BREQ PF0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 P50 P51 VSS VSS P52 P53/ ADTRG AV CC Vref P40/AN0 P41/AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6/ DA0 11 Table 1-2 Pin No. TFP-120 102 103 104 105 Pin Functions in Each Operating Mode (cont) Pin Name Mode 1 P47/AN7/ DA1 AV SS VSS Mode 2* P47/AN7/ DA1 AV SS VSS Mode 3* P47/AN7/ DA1 AV SS VSS Mode 4 P47/AN7/ DA1 AV SS VSS Mode 5 P47/AN7/ DA1 AV SS VSS Mode 6* P47/AN7/ DA1 AV SS VSS Mode 7* P47/AN7/ DA1 AV SS VSS FP-128 112 113 114 115 P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ P17/PO15/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TIOCB2/ TCLKD TCLKD TCLKD TCLKD TCLKD TCLKD TCLKD P16/PO14/ P16/PO14/ P16/PO14/ P16/PO14/ P16/PO14/ P16/PO14/ P16/PO14/ TIOCA2 TIOCA2 TIOCA2 TIOCA2 TIOCA2 TIOCA2 TIOCA2 P15/PO13/ P15/PO13/ P15/PO13/ P15/PO13/ P15/PO13/ P15/PO13/ P15/PO13/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TIOCB1/ TCLKC TCLKC TCLKC TCLKC TCLKC TCLKC TCLKC P14/PO12/ P14/PO12/ P14/PO12/ P14/PO12/ P14/PO12/ P14/PO12/ P14/PO12/ TIOCA1 TIOCA1 TIOCA1 TIOCA1 TIOCA1 TIOCA1 TIOCA1 P13/PO11/ P13/PO11/ P13/PO11/ P13/PO11/ P13/PO11/ P13/PO11/ P13/PO11/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TIOCD0/ TCLKB TCLKB TCLKB TCLKB TCLKB TCLKB TCLKB P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ P12/PO10/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TIOCC0/ TCLKA TCLKA TCLKA TCLKA TCLKA TCLKA TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0 PG 1 PG 2 PG 3 PG 4/CS0 VSS NC P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0 PG 1 PG 2 PG 3 PG 4/CS0 VSS NC P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0 PG 1 PG 2 PG 3 PG 4 VSS NC P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0/CAS PG 1/CS3 PG 2/CS2 PG 3/CS1 PG 4/CS0 VSS NC P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0/CAS PG 1/CS3 PG 2/CS2 PG 3/CS1 PG 4/CS0 VSS NC P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0/CAS PG 1/CS3 PG 2/CS2 PG 3/CS1 PG 4/CS0 VSS NC P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 MD0 MD1 MD2 PG 0 PG 1 PG 2 PG 3 PG 4 VSS NC 106 107 116 117 108 109 118 119 110 120 111 121 112 122 113 114 115 116 117 118 119 120 -- -- 123 124 125 126 127 128 1 2 3 4 Note: NC pins should be connected to VSS or left open. * Only applies to the H8S/2351. 12 1.3.3 Pin Functions Table 1-3 outlines the pin functions of the H8S/2350 Series. Table 1-3 Pin Functions Pin No. Type Power Symbol VCC TFP-120 1, 33, 52, 76, 81 6, 15, 24, 38, 47, 59, 79, 104 FP-128 5, 39, 58, 84, 89 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 85 I/O Input Name and Function Power supply: For connection to the power supply. All V CC pins should be connected to the system power supply. Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V). VSS Input Clock XTAL 77 Input Connects to a crystal oscillator. See section 19, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. Connects to a crystal oscillator. The EXTAL pin can also input an external clock. See section 19, Clock Pulse Generator, for typical connection diagrams for a crystal oscillator and external clock input. EXTAL 78 86 Input o 80 88 Output System clock: Supplies the system clock to an external device. 13 Table 1-3 Pin Functions (cont) Pin No. Type Symbol TFP-120 115 to 113 FP-128 125 to 123 I/O Input Name and Function Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the H8S/2350 Series is operating. MD2 0 MD1 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 Operating Mode -- Mode 1 Mode 2* Mode 3* Mode 4 Mode 5 Mode 6* Mode 7* Operating mode MD2 to control MD0 Note: * Only applies to the H8S/2351. System control RES 73 81 Input Reset input: When this pin is driven low, the chip is reset. The type of reset can be selected according to the NMI input level. At power-on, the NMI pin input level should be set high. Standby: When this pin is driven low, a transition is made to hardware standby mode. Bus request: Used by an external bus master to issue a bus request to the H8S/2350 Series. STBY 75 83 Input BREQ 88 96 Input BREQO 86 94 Output Bus request output: The external bus request signal used when an internal bus master accesses external space in the external bus-released state. Output Bus request acknowledge: Indicates that the bus has been released to an external bus master. BACK 87 95 14 Table 1-3 Pin Functions (cont) Pin No. Type Interrupts Symbol NMI TFP-120 74 FP-128 82 I/O Input Name and Function Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high. Interrupt request 7 to 0: These pins request a maskable interrupt. IRQ7 to IRQ0 Address bus A23 to A0 28 to 25, 29 to 32 28 to 25, 23 to 16, 14 to 7, 5 to 2 51 to 48, 46 to 39, 37 to 34 32 to 29, 33, 34, 37, 38 32 to 29, 27 to 20, 18 to 11, 9 to 6 57 to 54, 52 to 45, 43 to 40 Input Output Address bus: These pins output an address. Data bus D15 to D0 CS7 to CS0 I/O Data bus: These pins constitute a bidirectional data bus. Bus control Output Chip select: Signals for selecting 29, 30, 33, 34, areas 7 to 0. 61, 60, 69, 66, 117 to 120 127, 128, 1, 2 82 90 Output Address strobe: When this pin is low, it indicates that address output on the address bus is enabled. Output Read: When this pin is low, it indicates that the external address space can be read. Output High write/write enable: A strobe signal that writes to external space and indicates that the upper half (D15 to D8) of the data bus is enabled. The 2CAS type DRAM write enable signal. Output Low write: A strobe signal that writes to external space and indicates that the lower half (D7 to D0) of the data bus is enabled. Output Upper column address strobe/column address strobe: The 2CAS type DRAM upper column address strobe signal. AS RD 83 91 HWR 84 92 LWR 85 93 CAS 116 126 15 Table 1-3 Pin Functions (cont) Pin No. Type Bus control Symbol WAIT TFP-120 86 FP-128 94 I/O Input Name and Function Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state address space. LCAS 86 94 Output Lower column address strobe: The 2CAS type DRAM lower column address strobe signal Input DMA request 1 and 0: These pins request DMAC activation. DMA controller (DMAC) DREQ1, DREQ0 TEND1, TEND0 DACK1, DACK0 62, 60 63, 61 70, 66 71, 69 Output DMA transfer end 1 and 0: These pins indicate the end of DMAC data transfer. Output DMA transfer acknowledge 1 and 0: These are the DMAC single address transfer acknowledge pins. Clock input D to A: These pins input an external clock. Input capture/ output compare match A0 to D0: The TGR0A to TGR0D input capture input or output compare output, or PWM output pins. Input capture/ output compare match A1 and B1: The TGR1A and TGR1B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A2 and B2: The TGR2A and TGR2B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A3 to D3: The TGR3A to TGR3D input capture input or output compare output, or PWM output pins. 111, 112 121, 122 16-bit timerpulse unit (TPU) TCLKD to TCLKA TIOCA0, TIOCB0, TIOCC0, TIOCD0 TIOCA1, TIOCB1 105, 107, 115, 117, Input 109, 110 119, 120 112 to 109 122 to 119 I/O 108, 107 118, 117 I/O TIOCA2, TIOCB2 106, 105 116, 115 I/O TIOCA3, TIOCB3, TIOCC3, TIOCD3 71 to 68 79 to 76 I/O 16 Table 1-3 Pin Functions (cont) Pin No. Type 16-bit timerpulse unit (TPU) Symbol TIOCA4, TIOCB4 TFP-120 67, 66 FP-128 75, 74 I/O I/O Name and Function Input capture/ output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. Input capture/ output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins. TIOCA5, TIOCB5 65, 64 73, 72 I/O Programmable PO15 to pulse generator PO0 (PPG) Watchdog timer (WDT) Serial communication interface (SCI) Smart Card interface WDTOVF 105 to 112, 64 to 71 72 115 to 122, 72 to 79 80 Output Pulse output 15 to 0: Pulse output pins. Output Watchdog timer overflows: The counter overflows signal output pin in watchdog timer mode. Output Transmit data (channel 0, 1): Data output pins. Input I/O Input Input Receive data (channel 0, 1): Data input pins. Serial clock (channel 0, 1): Clock I/O pins. Analog 7 to 0: Analog input pins. A/D conversion external trigger input: Pin for input of an external trigger to start A/D conversion. TxD1, TxD0 RxD1, RxD0 SCK1, SCK0 AN7 to AN0 ADTRG 54, 53 56, 55 58, 57 102 to 95 92 60, 59 62, 61 64, 63 112 to 105 102 A/D converter D/A converter DA1, DA0 102, 101 112, 111 Output Analog output: D/A converter analog output pins. 17 Table 1-3 Pin Functions (cont) Pin No. Type A/D converter and D/A converter Symbol AVCC TFP-120 93 FP-128 103 I/O Input Name and Function This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V). This is the reference voltage input pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+5 V). Port 1: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 1 data direction register (P1DDR). Port 2: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 2 data direction register (P2DDR). Port 3: A 6-bit I/O port. Input or output can be designated for each bit by means of the port 3 data direction register (P3DDR). Port 4: An 8-bit input port. Port 5: A 4-bit I/O port. Input or output can be designated for each bit by means of the port 5 data direction register (P5DDR). AVSS 103 113 Input Vref 94 104 Input I/O ports P17 to P10 105 to 112 115 to 122 I/O P27 to P20 64 to 71 72 to 79 I/O P35 to P30 58 to 53 64 to 59 I/O P47 to P40 P53 to P50 102 to 95 92 to 89 112 to 105 Input 102, 101, I/O 98, 97 18 Table 1-3 Pin Functions (cont) Pin No. Type I/O ports Symbol P67 to P60 TFP-120 29 to 32, 63 to 60 FP-128 33, 34, 37, 38, 71 to 69, 66 32 to 29, 27 to 24 I/O I/O Name and Function Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR). Port A: An 8-bit I/O port. Input or output can be designated for each bit by means of the port A data direction register (PADDR). Port B*: An 8-bit I/O port. Input or output can be designated for each bit by means of the port B data direction register (PBDDR). Port C*: An 8-bit I/O port. Input or output can be designated for each bit by means of the port C data direction register (PCDDR). Port D*: An 8-bit I/O port. Input or output can be designated for each bit by means of the port D data direction register (PDDDR). Port E: An 8-bit I/O port. Input or output can be designated for each bit by means of the port E data direction register (PEDDR). Port F: An 8-bit I/O port. Input or output can be designated for each bit by means of the port F data direction register (PFDDR). Port G: A 5-bit I/O port. Input or output can be designated for each bit by means of the port G data direction register (PGDDR). PA7 to PA0 28 to 25, 23 to 20 I/O PB7 to PB0 19 to 16, 14 to 11 23 to 20, 18 to 15 I/O PC 7 to PC 0 10 to 7, 5 to 2 14 to 11, 9 to 6 I/O PD 7 to PD 0 51 to 48, 46 to 43 57 to 54, 52 to 49 I/O PE7 to PE0 42 to 39, 37 to 34 48 to 45, 43 to 40 I/O PF 7 to PF 0 80, 82 to 88 88, 90 to 96 I/O PG4 to PG0 120 to 116 2, 1, 128 to 126 I/O Note: * Only applies to the H8S/2351. 19 20 Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features. * Upward-compatible with H8/300 and H8/300H CPUs Can execute H8/300 and H8/300H object programs * General-register architecture Sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) * Sixty-five basic instructions 8/16/32-bit arithmetic and logic instructions Multiply and divide instructions Powerful bit-manipulation instructions * Eight addressing modes Register direct [Rn] Register indirect [@ERn] Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)] Register indirect with post-increment or pre-decrement [@ERn+ or @-ERn] Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] Immediate [#xx:8, #xx:16, or #xx:32] Program-counter relative [@(d:8,PC) or @(d:16,PC)] Memory indirect [@@aa:8] * 16-Mbyte address space Program: 16 Mbytes Data: 16 Mbytes (4 Gbytes architecturally) 21 * High-speed operation All frequently-used instructions execute in one or two states Maximum clock rate : 20 MHz 8/16/32-bit register-register add/subtract : 50 ns 8 x 8-bit register-register multiply : 600 ns 16 / 8-bit register-register divide : 600 ns 16 x 16-bit register-register multiply : 1000 ns 32 / 16-bit register-register divide : 1000 ns * Two CPU operating modes Normal mode Advanced mode * Power-down state Transition to power-down state by SLEEP instruction CPU clock speed selection 2.1.2 Differences between H8S/2600 CPU and H8S/2000 CPU The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below. * Register configuration The MAC register is supported only by the H8S/2600 CPU. * Basic instructions The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the H8S/2600 CPU. * Number of execution states The number of exection states of the MULXU and MULXS instructions. Internal Operation Instruction MULXU Mnemonic MULXU.B Rs, Rd MULXU.W Rs, ERd MULXS MULXS.B Rs, Rd MULXS.W Rs, ERd H8S/2600 3 4 4 5 H8S/2000 12 20 13 21 There are also differences in the address space, CCR and EXR functions, power-down state, etc., depending on the product. 22 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. * More general registers and control registers Eight 16-bit expanded registers, and one 8-bit control register, have been added. * Expanded address space Normal mode supports the same 64-kbyte address space as the H8/300 CPU. Advanced mode supports a maximum 16-Mbyte address space. * Enhanced addressing The addressing modes have been enhanced to make effective use of the 16-Mbyte address space. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Signed multiply and divide instructions have been added. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 2.1.4 Differences from H8/300H CPU In comparison to the H8/300H CPU, the H8S/2000 CPU has the following enhancements. * Additional control register One 8-bit control register has been added. * Enhanced instructions Addressing modes of bit-manipulation instructions have been enhanced. Two-bit shift instructions have been added. Instructions for saving and restoring multiple registers have been added. A test and set instruction has been added. * Higher speed Basic instructions execute twice as fast. 23 2.2 CPU Operating Modes The H8S/2000 CPU has two operating modes: normal and advanced. Normal mode supports a maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller. Maximum 64 kbytes, program and data areas combined Normal mode CPU operating modes Advanced mode Maximum 16-Mbytes for program and data areas combined Figure 2-1 CPU Operating Modes (1) Normal Mode The exception vector table and stack have the same structure as in the H8/300 CPU. Address Space: A maximum address space of 64 kbytes can be accessed. Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. When En is used as a 16-bit register it can contain any value, even when the corresponding general register (Rn) is used as an address register. If the general register is referenced in the register indirect addressing mode with pre-decrement (@-Rn) or post-increment (@Rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (En) will be affected. Instruction Set: All instructions and addressing modes can be used. Only the lower 16 bits of effective addresses (EA) are valid. 24 Exception Vector Table and Memory Indirect Branch Addresses: In normal mode the top area starting at H'0000 is allocated to the exception vector table. One branch address is stored per 16 bits. The configuration of the exception vector table in normal mode is shown in figure 2-2. For details of the exception vector table, see section 4, Exception Handling. H'0000 H'0001 H'0002 H'0003 H'0004 H'0005 H'0006 H'0007 H'0008 H'0009 H'000A H'000B Power-on reset exception vector Manual reset exception vector (Reserved for system use) Exception vector table Exception vector 1 Exception vector 2 Figure 2-2 Exception Vector Table (Normal Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In normal mode the operand is a 16-bit word operand, providing a 16bit branch address. Branch addresses can be stored in the top area from H'0000 to H'00FF. Note that this area is also used for the exception vector table. 25 Stack Structure: When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP PC (16 bits) SP *2 (SP ) EXR*1 Reserved*1,*3 CCR CCR*3 PC (16 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2-3 Stack Structure in Normal Mode (2) Advanced Mode Address Space: Linear access is provided to a 16-Mbyte maximum address space (architecturally a maximum 16-Mbyte program area and a maximum 4-Gbyte data area, with a maximum of 4 Gbytes for program and data areas combined). Extended Registers (En): The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. Instruction Set: All instructions and addressing modes can be used. 26 Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). For details of the exception vector table, see section 4, Exception Handling. H'00000000 Reserved Power-on reset exception vector H'00000003 H'00000004 Reserved Manual reset exception vector H'00000007 H'00000008 Exception vector table H'0000000B H'0000000C (Reserved for system use) H'00000010 Reserved Exception vector 1 Figure 2-4 Exception Vector Table (Advanced Mode) The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of this range is also the exception vector table. 27 Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling. SP SP Reserved PC (24 bits) *2 (SP ) EXR*1 Reserved*1,*3 CCR PC (24 bits) (a) Subroutine Branch (b) Exception Handling Notes: 1. When EXR is not used it is not stored on the stack. 2. SP when EXR is not used. 3. Ignored when returning. Figure 2-5 Stack Structure in Advanced Mode 28 2.3 Address Space Figure 2-6 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'0000 H'00000000 H'FFFF Program area H'00FFFFFF Data area Cannot be used by the H8S/2350 Series H'FFFFFFFF (a) Normal Mode (b) Advanced Mode Figure 2-6 Memory Map 29 2.4 2.4.1 Register Configuration Overview The CPU has the internal registers shown in figure 2-7. There are two types of registers: general registers and control registers. General Registers (Rn) and Extended Registers (En) 15 ER0 ER1 ER2 ER3 ER4 ER5 ER6 ER7 (SP) Control Registers (CR) 23 PC 76543210 EXR T -- -- -- -- I2 I1 I0 76543210 CCR I UI H U N Z V C Legend SP: PC: EXR: T: I2 to I0: CCR: I: UI: 0 E0 E1 E2 E3 E4 E5 E6 E7 07 R0H R1H R2H R3H R4H R5H R6H R7H 07 R0L R1L R2L R3L R4L R5L R6L R7L 0 Stack pointer Program counter Extended control register Trace bit Interrupt mask bits Condition-code register Interrupt mask bit User bit or interrupt mask bit* H: U: N: Z: V: C: Half-carry flag User bit Negative flag Zero flag Overflow flag Carry flag Note: * In the H8S/2350 Series, this bit cannot be used as an interrupt mask. Figure 2-7 CPU Registers 30 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7). The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R (R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit registers. The E registers (E0 to E7) are also referred to as extended registers. The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit registers. Figure 2-8 illustrates the usage of the general registers. The usage of each register can be selected independently. * Address registers * 32-bit registers * 16-bit registers E registers (extended registers) (E0 to E7) * 8-bit registers ER registers (ER0 to ER7) R registers (R0 to R7) RH registers (R0H to R7H) RL registers (R0L to R7L) Figure 2-8 Usage of General Registers 31 General register ER7 has the function of stack pointer (SP) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. Figure 2-9 shows the stack. Free area SP (ER7) Stack area Figure 2-9 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC): This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an instruction is fetched, the least significant PC bit is regarded as 0.) (2) Extended Control Register (EXR): This 8-bit register contains the trace bit (T) and three interrupt mask bits (I2 to I0). Bit 7--Trace Bit (T): Selects trace mode. When this bit is cleared to 0, instructions are executed in sequence. When this bit is set to 1, a trace exception is generated each time an instruction is executed. Bits 6 to 3--Reserved: These bits are reserved. They are always read as 1. 32 Bits 2 to 0--Interrupt Mask Bits (I2 to I0): These bits designate the interrupt mask level (0 to 7). For details, refer to section 5, Interrupt Controller. Operations can be performed on the EXR bits by the LDC, STC, ANDC, ORC, and XORC instructions. All interrupts, including NMI, are disabled for three states after one of these instructions is executed, except for STC. (3) Condition-Code Register (CCR): This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7--Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller. Bit 6--User Bit or Interrupt Mask Bit (UI): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. With the H8S/2350 Series, this bit cannot be used as an interrupt mask bit. Bit 5--Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. When the ADD.W, SUB.W, CMP.W, or NEG.W instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. When the ADD.L, SUB.L, CMP.L, or NEG.L instruction is executed, the H flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. Bit 4--User Bit (U): Can be written and read by software using the LDC, STC, ANDC, ORC, and XORC instructions. Bit 3--Negative Flag (N): Stores the value of the most significant bit (sign bit) of data. Bit 2--Zero Flag (Z): Set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. Bit 1--Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. Bit 0--Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by: * Add instructions, to indicate a carry * Subtract instructions, to indicate a borrow * Shift and rotate instructions, to store the value shifted out of the end bit The carry flag is also used as a bit accumulator by bit manipulation instructions. 33 Some instructions leave some or all of the flag bits unchanged. For the action of each instruction on the flag bits, refer to Appendix A.1, List of Instructions. Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized. The stack pointer should therefore be initialized by an MOV.L instruction executed immediately after a reset. 34 2.5 Data Formats The CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ..., 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two digits of 4-bit BCD data. 2.5.1 General Register Data Formats Figure 2-10 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 76543210 Don't care 1-bit data RnL Don't care 7 0 76543210 4-bit BCD data RnH 7 Upper 43 Lower 0 Don't care 4-bit BCD data RnL Don't care 7 Upper 43 Lower 0 Byte data RnH 7 MSB 0 Don't care LSB 7 Don't care MSB LSB 0 Byte data RnL Figure 2-10 General Register Data Formats 35 Data Type Register Number Data Format Word data Rn 15 MSB 0 LSB Word data 15 MSB Longword data 31 MSB En 0 LSB ERn 16 15 En Rn 0 LSB Legend ERn: General register ER En: General register E Rn: General register R RnH: General register RH RnL: General register RL MSB: Most significant bit LSB: Least significant bit Figure 2-10 General Register Data Formats (cont) 36 2.5.2 Memory Data Formats Figure 2-11 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches. Data Type Address 7 1-bit data Address L 7 6 5 4 3 2 1 0 0 Data Format Byte data Address L MSB LSB Word data Address 2M MSB Address 2M + 1 LSB Longword data Address 2N MSB Address 2N + 1 Address 2N + 2 Address 2N + 3 LSB Figure 2-11 Memory Data Formats When ER7 is used as an address register to access the stack, the operand size should be word size or longword size. 37 2.6 2.6.1 Instruction Set Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2-1. Table 2-1 Function Data transfer Instruction Classification Instructions MOV POP* , PUSH* LDM, STM MOVFPE, MOVTPE* 3 1 1 Size BWL WL L B BWL B BWL L BW WL B BWL Types 5 Arithmetic operations ADD, SUB, CMP, NEG ADDX, SUBX, DAA, DAS INC, DEC ADDS, SUBS MULXU, DIVXU, MULXS, DIVXS EXTU, EXTS TAS 19 Logic operations Shift Bit manipulation Branch System control Block data transfer AND, OR, XOR, NOT 4 8 14 5 9 1 SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR BWL BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND, BIAND, BOR, BIOR, BXOR, BIXOR Bcc* 2, JMP, BSR, JSR, RTS B -- TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP -- EEPMOV -- Notes: B-byte size; W-word size; L-longword size. 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn, @SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and MOV.L ERn, @-SP. 2. Bcc is the general name for conditional branch instructions. 3. Cannot be used in the H8S/2350 Series. 38 2.6.2 Table 2-2 Combinations of Instructions and Addressing Modes Addressing Modes Function #xx Instruction Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Data transfer -- -- -- BWL WL B -- -- -- -- -- -- -- -- -- B -- -- -- WL -- -- -- -- BWL -- -- -- -- -- -- -- BW -- -- -- -- -- -- -- -- -- BW -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- L -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOV BWL BWL BWL BWL BWL BWL B BWL -- BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- WL L -- -- -- -- -- -- -- -- -- -- -- -- POP, PUSH LDM, STM MOVFPE, MOVTPE* Arithmetic operations ADD, CMP SUB ADDX, SUBX ADDS, SUBS Instructions and Addressing Modes INC, DEC DAA, DAS MULXU, DIVXU MULXS, DIVXS NEG EXTU, EXTS TAS Table 2-2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. -- Note: * Cannot be used in the H8S/2350 Series. 39 #xx Rn @ERn @(d:16,ERn) @(d:32,ERn) @-ERn/@ERn+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,PC) @(d:16,PC) @@aa:8 Logic operations AND, OR, XOR NOT -- -- -- -- -- -- -- -- B -- B -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B W W W W B W W W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- W W -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- B B -- -- -- B B -- BWL -- -- -- -- -- -- -- -- B -- -- -- -- -- -- W W -- -- -- -- BWL -- -- -- -- -- -- -- -- BWL BWL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Shift Bcc, BSR JMP, JSR RTS TRAPA RTE SLEEP LDC STC ANDC, ORC, XORC NOP Bit manipulation Branch System control -- -- -- Block data transfer BW Legend B: Byte W: Word L: Longword -- 40 Addressing Modes Instruction Table 2-2 Combinations of Instructions and Addressing Modes (Cont) Function 2.6.3 Table of Instructions Classified by Function Table 2-3 summarizes the instructions in each functional category. The notation used in table 2-3 is defined below. Operation Notation Rd Rs Rn ERn (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / :8/:16/:24/:32 General register (destination)* General register (source)* General register* General register (32-bit register) Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Addition Subtraction Multiplication Division Logical AND Logical OR Logical exclusive OR Move NOT (logical complement) 8-, 16-, 24-, or 32-bit length Note: * General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 41 Table 2-3 Type Data transfer Instructions Classified by Function Instruction MOV Size* B/W/L Function (EAs) Rd, Rs (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. Cannot be used in the H8S/2350 Series. Cannot be used in the H8S/2350 Series. @SP+ Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn. Rn @-SP Pushes a register onto the stack. PUSH.W Rn is identical to MOV.W Rn, @-SP. PUSH.L ERn is identical to MOV.L ERn, @-SP. @SP+ Rn (register list) Pops two or more general registers from the stack. Rn (register list) @-SP Pushes two or more general registers onto the stack. MOVFPE MOVTPE POP B B W/L PUSH W/L LDM STM L L Note: * Size refers to the operand size. B: Byte W: Word L: Longword 42 Table 2-3 Type Arithmetic operations Instructions Classified by Function (cont) Instruction ADD SUB Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.) Rd Rs C Rd, Rd #IMM C Rd Performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. Rd 1 Rd, Rd 2 Rd Increments or decrements a general register by 1 or 2. (Byte operands can be incremented or decremented by 1 only.) Rd 1 Rd, Rd 2 Rd, Rd 4 Rd Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. Rd decimal adjust Rd Decimal-adjusts an addition or subtraction result in a general register by referring to the CCR to produce 4-bit BCD data. Rd x Rs Rd Performs unsigned multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd x Rs Rd Performs signed multiplication on data in two general registers: either 8 bits x 8 bits 16 bits or 16 bits x 16 bits 32 bits. Rd / Rs Rd Performs unsigned division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. ADDX SUBX B INC DEC B/W/L ADDS SUBS DAA DAS L B MULXU B/W MULXS B/W DIVXU B/W Note: * Size refers to the operand size. B: Byte W: Word L: Longword 43 Table 2-3 Type Arithmetic operations Instructions Classified by Function (cont) Instruction DIVXS Size* B/W Function Rd / Rs Rd Performs signed division on data in two general registers: either 16 bits / 8 bits 8-bit quotient and 8-bit remainder or 32 bits / 16 bits 16-bit quotient and 16bit remainder. Rd - Rs, Rd - #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result. 0 - Rd Rd Takes the two's complement (arithmetic complement) of data in a general register. Rd (zero extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. Rd (sign extension) Rd Extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. @ERd - 0, 1 ( CMP B/W/L NEG B/W/L EXTU W/L EXTS W/L TAS B Note: * Size refers to the operand size. B: Byte W: Word L: Longword 44 Table 2-3 Type Logic operations Instructions Classified by Function (cont) Instruction AND Size* B/W/L Function Rd Rs Rd, Rd #IMM Rd Performs a logical AND operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical OR operation on a general register and another general register or immediate data. Rd Rs Rd, Rd #IMM Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data. (Rd) (Rd) Takes the one's complement of general register contents. Rd (shift) Rd Performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. Rd (shift) Rd Performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. Rd (rotate) Rd Rotates general register contents. 1-bit or 2-bit rotation is possible. Rd (rotate) Rd Rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. OR B/W/L XOR B/W/L NOT B/W/L Shift operations SHAL SHAR SHLL SHLR ROTL ROTR ROTXL ROTXR B/W/L B/W/L B/W/L B/W/L Note: * Size refers to the operand size. B: Byte W: Word L: Longword 45 Table 2-3 Type Bitmanipulation instructions Instructions Classified by Function (cont) Instruction BSET Size* B Function 1 ( BCLR B BNOT B BTST B BAND B BIAND B BOR B BIOR B Note: * Size refers to the operand size. B: Byte 46 Table 2-3 Type Bitmanipulation instructions Instructions Classified by Function (cont) Instruction BXOR Size* B Function C ( BIXOR B BLD B BILD B BST B BIST B Note: * Size refers to the operand size. B: Byte 47 Table 2-3 Type Branch instructions Instructions Classified by Function (cont) Instruction Bcc Size* -- Function Branches to a specified address if a specified condition is true. The branching conditions are listed below. Mnemonic BRA(BT) BRN(BF) BHI BLS BCC(BHS) BCS(BLO) BNE BEQ BVC BVS BPL BMI BGE BLT BGT BLE JMP BSR JSR RTS -- -- -- -- Description Always (true) Never (false) High Low or same Carry clear (high or same) Carry set (low) Not equal Equal Overflow clear Overflow set Plus Minus Greater or equal Less than Greater than Less or equal Condition Always Never CZ=0 CZ=1 C=0 C=1 Z=0 Z=1 V=0 V=1 N=0 N=1 NV=0 NV=1 Z(N V) = 0 Z(N V) = 1 Branches unconditionally to a specified address. Branches to a subroutine at a specified address. Branches to a subroutine at a specified address. Returns from a subroutine 48 Table 2-3 Type Instructions Classified by Function (cont) Instruction Size* -- -- -- B/W Function Starts trap-instruction exception handling. Returns from an exception-handling routine. Causes a transition to a power-down state. (EAs) CCR, (EAs) EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR (EAd), EXR (EAd) Transfers CCR or EXR contents to a general register or memory. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid. CCR #IMM CCR, EXR #IMM EXR Logically ANDs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically ORs the CCR or EXR contents with immediate data. CCR #IMM CCR, EXR #IMM EXR Logically exclusive-ORs the CCR or EXR contents with immediate data. PC + 2 PC Only increments the program counter. System control TRAPA instructions RTE SLEEP LDC STC B/W ANDC B ORC B XORC B NOP -- Note: * Size refers to the operand size. B: Byte W: Word 49 Table 2-3 Type Block data transfer instruction Instructions Classified by Function (cont) Instruction EEPMOV.B Size* -- Function if R4L 0 then Repeat @ER5+ @ER6+ R4L-1 R4L Until R4L = 0 else next; if R4 0 then Repeat @ER5+ @ER6+ R4-1 R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6. R4L or R4: size of block (bytes) ER5: starting source address ER6: starting destination address Execution of the next instruction begins as soon as the transfer is completed. EEPMOV.W -- 50 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2-12 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rn rm ADD.B Rn, Rm, etc. (3) Operation field, register fields, and effective address extension op EA (disp) (4) Operation field, effective address extension, and condition field op cc EA (disp) BRA d:16, etc rn rm MOV.B @(d:16, Rn), Rm, etc. Figure 2-12 Instruction Formats (Examples) (1) Operation Field: Indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. The operation field always includes the first four bits of the instruction. Some instructions have two operation fields. (2) Register Field: Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or 4 bits. Some instructions have two register fields. Some have no register field. (3) Effective Address Extension: Eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) Condition Field: Specifies the branching condition of Bcc instructions. 51 2.7 2.7.1 Addressing Modes and Effective Address Calculation Addressing Mode The CPU supports the eight addressing modes listed in table 2-4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect. Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. Table 2-4 No. 1 2 3 4 5 6 7 8 Addressing Modes Symbol Rn @ERn @(d:16,ERn)/@(d:32,ERn) @ERn+ @-ERn @aa:8/@aa:16/@aa:24/@aa:32 #xx:8/#xx:16/#xx:32 @(d:8,PC)/@(d:16,PC) @@aa:8 Addressing Mode Register direct Register indirect Register indirect with displacement Register indirect with post-increment Register indirect with pre-decrement Absolute address Immediate Program-counter relative Memory indirect (1) Register Direct--Rn: The register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers. (2) Register Indirect--@ERn: The register field of the instruction code specifies an address register (ERn) which contains the address of the operand on memory. If the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (H'00). (3) Register Indirect with Displacement--@(d:16, ERn) or @(d:32, ERn): A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn) specified by the register field of the instruction, and the sum gives the address of a memory operand. A 16-bit displacement is sign-extended when added. 52 (4) Register Indirect with Post-Increment or Pre-Decrement--@ERn+ or @-ERn: * Register indirect with post-increment--@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. * Register indirect with pre-decrement--@-ERn The value 1, 2, or 4 is subtracted from an address register (ERn) specified by the register field in the instruction code, and the result becomes the address of a memory operand. The result is also stored in the address register. The value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. For word or longword transfer instruction, the register value should be even. (5) Absolute Address--@aa:8, @aa:16, @aa:24, or @aa:32: The instruction code contains the absolute address of a memory operand. The absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF). For a 16-bit absolute address the upper 16 bits are a sign extension. A 32-bit absolute address can access the entire address space. A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8 bits are all assumed to be 0 (H'00). Table 2-5 indicates the accessible absolute address ranges. Table 2-5 Absolute Address Access Ranges Normal Mode 8 bits (@aa:8) 16 bits (@aa:16) 32 bits (@aa:32) Program instruction address 24 bits (@aa:24) H'FF00 to H'FFFF H'0000 to H'FFFF Advanced Mode H'FFFF00 to H'FFFFFF H'000000 to H'007FFF, H'FF8000 to H'FFFFFF H'000000 to H'FFFFFF Absolute Address Data address 53 (6) Immediate--#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) Program-Counter Relative--@(d:8, PC) or @(d:16, PC): This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is -126 to +128 bytes (-63 to +64 words) or -32766 to +32768 bytes (-16383 to +16384 words) from the branch instruction. The resulting value should be an even number. (8) Memory Indirect--@@aa:8: This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit absolute address specifying a memory operand. This memory operand contains a branch address. The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode). In normal mode the memory operand is a word operand and the branch address is 16 bits long. In advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For further details, refer to section 4, Exception Handling. Specified by @aa:8 Branch address Specified by @aa:8 Reserved Branch address (a) Normal Mode (b) Advanced Mode Figure 2-13 Branch Address Specification in Memory Indirect Mode 54 If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2-6 indicates how effective addresses are calculated in each addressing mode. In normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address. 55 56 Effective Address Calculation Effective Address (EA) rm rn Operand is general register contents. 31 General register contents r Don't care 0 31 24 23 31 General register contents 31 r disp 31 Sign extension disp 0 24 23 Don't care 0 31 General register contents r 1, 2, or 4 31 General register contents 31 r Operand Size Value added Byte Word Longword 1 2 4 1, 2, or 4 24 23 Don't care 0 0 31 24 23 Don't care Table 2-6 Effective Address Calculation No. Addressing Mode and Instruction Format 1 Register direct (Rn) op 2 Register indirect (@ERn) 0 op 3 Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) 0 op 4 Register indirect with post-increment or pre-decrement * Register indirect with post-increment @ERn+ 0 op * Register indirect with pre-decrement @-ERn 0 op Table 2-6 Effective Address Calculation (cont) Effective Address Calculation Effective Address (EA) No. Addressing Mode and Instruction Format 5 31 abs Absolute address 24 23 H'FFFF Don't care @aa:8 op 87 0 @aa:16 op abs 31 24 23 Don't care 16 15 Sign extension 0 @aa:24 op abs 31 24 23 Don't care 0 @aa:32 op abs 31 24 23 Don't care 0 6 op IMM Immediate #xx:8/#xx:16/#xx:32 Operand is immediate data. 57 58 Effective Address Calculation 23 PC contents 0 Effective Address (EA) op 23 0 disp 31 24 23 0 Sign extension disp Don't care Table 2-6 Effective Address Calculation (cont) No. Addressing Mode and Instruction Format 7 Program-counter relative @(d:8, PC)/@(d:16, PC) 8 Memory indirect @@aa:8 * Normal mode op 31 H'000000 abs 87 abs 0 31 24 23 Don't care 16 15 H'00 15 Memory contents 0 0 * Advanced mode op abs 31 H'000000 31 Memory contents 87 abs 0 31 24 23 Don't care 0 0 2.8 2.8.1 Processing States Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2-14 shows a diagram of the processing states. Figure 2-15 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped. Exception-handling state A transient state in which the CPU changes the normal processing flow in response to a reset, interrupt, or trap instruction. Processing states Program execution state The CPU executes program instructions in sequence. Bus-released state The external bus has been released in response to a bus request signal from a bus master other than the CPU. Sleep mode Power-down state CPU operation is stopped to conserve power.* Software standby mode Hardware standby mode Note: * The power-down state also includes a medium-speed mode, module stop mode etc. Figure 2-14 Processing States 59 End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 0 Bus-released state End of exception handling Request for exception handling SLEEP instruction with SSBY = 1 Sleep mode Interrupt request Exception-handling state External interrupt RES = high Software standby mode Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low. A transition can also be made to the reset state when the watchdog timer overflows. 2. From any state, a transition to hardware standby mode occurs when STBY goes low. Figure 2-15 State Transitions 2.8.2 Reset State When the RES input goes low all current processing stops and the CPU enters the reset state. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. All interrupts are masked in the reset state. Reset exception handling starts when the RES signal changes from low to high. The reset state can also be entered by a watchdog timer overflow. For details, refer to section 12, Watchdog Timer. 60 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2-7 indicates the types of exception handling and their priority. Trap instruction exception handling is always accepted, in the program execution state. Exception handling and the stack structure depend on the interrupt control mode set in SYSCR. Table 2-7 Priority High Exception Handling Types and Priority Type of Exception Reset Detection Timing Synchronized with clock Start of Exception Handling Exception handling starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. When the trace (T) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence When an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence Exception handling starts when a trap (TRAPA) instruction is executed* 3 Trace End of instruction execution or end of exception-handling sequence* 1 End of instruction execution or end of exception-handling sequence* 2 When TRAPA instruction is executed Interrupt Trap instruction Low Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception-handling is not executed at the end of the RTE instruction. 2. Interrupts are not detected at the end of the ANDC, ORC, XORC, and LDC instructions, or immediately after reset exception handling. 3. Trap instruction exception handling is always accepted, in the program execution state. 61 (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2. Trace mode is entered when the T bit of EXR is set to 1. When trace mode is established, trace exception handling starts at the end of each instruction. At the end of a trace exception-handling sequence, the T bit of EXR is cleared to 0 and trace mode is cleared. Interrupt masks are not affected. The T bit saved on the stack retains its value of 1, and when the RTE instruction is executed to return from the trace exception-handling routine, trace mode is entered again. Trace exceptionhandling is not executed at the end of the RTE instruction. Trace mode is not entered in interrupt control mode 0, regardless of the state of the T bit. (4) Interrupt Exception Handling and Trap Instruction Exception Handling When interrupt or trap-instruction exception handling begins, the CPU references the stack pointer (ER7) and pushes the program counter and other control registers onto the stack. Next, the CPU alters the settings of the interrupt mask bits in the control registers. Then the CPU fetches a start address (vector) from the exception vector table and program execution starts from that start address. Figure 2-16 shows the stack after exception handling ends. 62 Normal mode SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 (b) Interrupt control mode 2 Advanced mode SP SP CCR PC (24 bits) EXR Reserved* CCR PC (24 bits) (c) Interrupt control mode 0 Note: *Ignored when returning. (d) Interrupt control mode 2 Figure 2-16 Stack Structure after Exception Handling (Examples) 63 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU. While the bus is released, the CPU halts. There is one other bus master in addition to the CPU: the data transfer controller (DTC). For further details, refer to section 6, Bus Controller. 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock. Module stop mode permits halting of the operation of individual modules, other than the CPU. For details, refer to section 20, Power-Down State. (1) Sleep Mode: A transition to sleep mode is made if the SLEEP instruction is executed while the software standby bit (SSBY) in the standby control register (SBYCR) is cleared to 0. In sleep mode, CPU operations stop immediately after execution of the SLEEP instruction. The contents of CPU registers are retained. (2) Software Standby Mode: A transition to software standby mode is made if the SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1. In software standby mode, the CPU and clock halt and all MCU operations stop. As long as a specified voltage is supplied, the contents of CPU registers and on-chip RAM are retained. The I/O ports also remain in their existing states. (3) Hardware Standby Mode: A transition to hardware standby mode is made when the STBY pin goes low. In hardware standby mode, the CPU and clock halt and all MCU operations stop. The on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip RAM contents are retained. 64 2.9 2.9.1 Basic Timing Overview The CPU is driven by a system clock, denoted by the symbol o. The period from one rising edge of o to the next is referred to as a "state." The memory cycle or bus cycle consists of one, two, or three states. Different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 On-Chip Memory (ROM, RAM) On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and word transfer instruction. Figure 2-17 shows the on-chip memory access cycle. Figure 2-18 shows the pin states. Bus cycle T1 o Internal address bus Internal read signal Internal data bus Internal write signal Write access Internal data bus Write data Read data Address Read access Figure 2-17 On-Chip Memory Access Cycle 65 Bus cycle T1 o Address bus AS RD HWR, LWR Data bus Unchanged High High High High-impedance state Figure 2-18 Pin States during On-Chip Memory Access 66 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2-19 shows the access timing for the on-chip supporting modules. Figure 2-20 shows the pin states. Bus cycle T1 T2 o Internal address bus Address Internal read signal Read access Internal data bus Internal write signal Write access Internal data bus Write data Read data Figure 2-19 On-Chip Supporting Module Access Cycle 67 Bus cycle T1 T2 o Address bus Unchanged AS RD HWR, LWR High High High Data bus High-impedance state Figure 2-20 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 68 Section 3 MCU Operating Modes 3.1 3.1.1 Overview H8S/2350 Operating Mode Selection The H8S/2350 has three operating modes (modes 1, 4, and 5). These modes are determined by the mode pin (MD2 to MD0) settings. The CPU operating mode and initial bus width can be selected as shown in table 3-1. Table 3-1 lists the MCU operating modes. Table 3-1 MCU Operating Mode Selection (H8S/2350) External Data Bus On-Chip Initial ROM Width -- -- 16 bits -- Max. Width MCU CPU Operating Operating Description Mode MD2 MD1 MD0 Mode 0 1 2 3 4 5 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 -- Normal -- -- On-chip ROM disabled, Disabled 8 bits expanded mode -- -- -- Advanced On-chip ROM disabled, Disabled 16 bits expanded mode 8 bits -- -- -- -- 16 bits 16 bits -- The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2350 actually accesses a maximum of 16 Mbytes. Modes 1, 4, and 5 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. 69 The H8S/2350 can be used only in modes 1, 4, and 5. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.2 H8S/2351 Operating Mode Selection The H8S/2351 has seven operating modes (modes 1 to 7). These modes enable selection of the CPU operating mode, enabling/disabling of on-chip ROM, and the initial bus width setting, by setting the mode pins (MD2 to MD0). Table 3-2 lists the MCU operating modes. Table 3-2 MCU Operating Mode Selection (H8S/2351) External Data Bus On-Chip Initial ROM Width -- -- 16 bits 16 bits Max. Width MCU CPU Operating Operating Description Mode MD2 MD1 MD0 Mode 0 1 2 3 4 5 6 7 1 1 0 1 0 0 0 1 0 1 0 1 0 1 -- Normal -- On-chip ROM disabled, Disabled 8 bits expanded mode On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode -- Advanced On-chip ROM disabled, Disabled 16 bits expanded mode 8 bits On-chip ROM enabled, Enabled 8 bits expanded mode Single-chip mode -- 16 bits 16 bits 16 bits The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2351 actually accesses a maximum of 16 Mbytes. Modes 1, 2, and 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. If 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. Note that the functions of each pin depend on the operating mode. 70 The H8S/2351 can be used only in modes 1 to 7. This means that the mode pins must be set to select one of these modes. Do not change the inputs at the mode pins during operation. 3.1.3 Register Configuration The H8S/2350 Series has a mode control register (MDCR) that indicates the inputs at the mode pins (MD 2 to MD0), and a system control register (SYSCR) that controls the operation of the H8S/2350 Series. Table 3-3 summarizes these registers. Table 3-3 Name Mode control register System control register MCU Registers Abbreviation MDCR SYSCR R/W R R/W Initial Value Undetermined H'01 Address* H'FF3B H'FF39 Note: * Lower 16 bits of the address. 3.2 3.2.1 Bit Register Descriptions Mode Control Register (MDCR) : 7 -- 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MDS0 --* R Initial value: R/W : Note: * Determined by pins MD2 to MD0. MDCR is an 8-bit read-only register that indicates the current operating mode of the H8S/2350 Series. Bit 7--Reserved: Read-only bit, always read as 1. Bits 6 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--Mode Select 2 to 0 (MDS2 to MDS0): These bits indicate the input levels at pins MD2 to MD0 (the current operating mode). Bits MDS2 to MDS0 correspond to MD2 to MD0. MDS2 to MDS0 are read-only bits, they cannot be written to. The mode pin (MD2 to MD0) input levels are latched into these bits when MDCR is read. These latches are canceled by a power-on reset, but are retained after a manual reset. 71 3.2.2 Bit System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W Initial value: R/W : Bit 7--Reserved: Only 0 should be written to this bit. Bit 6--Reserved: Read-only bit, always read as 0. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller. For details of the interrupt control modes, see section 5.4.1, Interrupt Control Modes and Interrupt Operation. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode Description 0 -- 2 -- Control of interrupts by I bit Setting prohibited Control of interrupts by I2 to I0 bits and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the valid edge of the NMI interrupt input. Bit 3 NMIEG 0 1 Description An interrupt is requested at the falling edge of NMI input An interrupt is requested at the rising edge of NMI input (Initial value) Bit 2--Reserved: Read-only bit, always read as 0. Bit 1--Reserved: Only 0 should be written to this bit. Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset status is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 72 3.3 3.3.1 Operating Mode Descriptions Mode 1 The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is disabled, and 8-bit bus mode is set, immediately after a reset. Ports B and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.2 Mode 2 (H8S/2351 Only) The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, and 8-bit bus mode is set. immediately after a reset. Ports B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. However, note that if 16-bit access is designated by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.3 Mode 3 (H8S/2351 Only) The CPU can access a 64-kbyte address space in normal mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. The amount of on-chip ROM that can be used is limited to 56 kbytes. 3.3.4 Mode 4 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, ports D and E function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 73 3.3.5 Mode 5 The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B and C function as an address bus, port D function as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16-bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.6 Mode 6 (H8S/2351 Only) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled. Ports A, B and C function as input ports immediately after a reset. They can each be set to output addresses by setting the corresponding bits in the data direction register (DDR) to 1. Port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, note that if at least one area is designated for 16 bit access by the bus controller, the bus mode switches to 16 bits and port E becomes a data bus. 3.3.7 Mode 7 (H8S/2351 Only) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled, but external addresses cannot be accessed. All I/O ports are available for use as input-output ports. 74 3.4 Pin Functions in Each Operating Mode The pin functions of ports A to F vary depending on the operating mode. Table 3-4 shows their functions in each operating mode. Table 3-4 Port Port A PA7 to PA 5 PA4 to PA 0 Port B Port C Port D Port E Port F PF 7 PF 6 to PF3 PF 2 to PF0 A A D P* /D P/C* C P* /C 1 1 1 Pin Functions in Each Mode Mode 1 P Mode 2* 2 Mode 3* 2 Mode 4 P P P* 1/A A P* /A P* /A D P* /D P/C* C P* /C 1 1 1 1 1 Mode 5 P* 1/A A A A D Mode 6* 2 Mode 7* 2 P* 1/A P P P P P P* /C P 1 A A D P/D* P/C* C P* /C 1 1 1 P* 1/A P* /A D 1 1 P P P P* /D P/C* C P* /C 1 1 P* /D P/C* C P* /C 1 1 1 P P* 1/C P Legend P: I/O port A: Address bus output D: Data bus I/O C: Control signals, clock I/O *1: After reset *2: Only applies to the H8S/2351 3.5 Memory Map in Each Operating Mode Figure 3-1 shows a memory map for each of the operating modes. The address space is 64 kbytes in modes 1 to 3 (normal modes), and 16 Mbytes in modes 4 to 7 (advanced modes). The H8S/2351's on-chip ROM contains 64 kbytes, but only 56 kbytes are available in modes 2 and 3 (normal modes). The address space is divided into eight areas for modes 4 to 7. For details, see section 6, Bus Controller. 75 Mode 1 (normal expanded mode with on-chip ROM disabled) H'0000 Mode 2*1 (normal expanded mode with on-chip ROM enabled) H'0000 Mode 3*1 (normal single-chip mode) H'0000 On-chip ROM External address space On-chip ROM H'DFFF H'E000 External address space H'F400 On-chip RAM*2 space H'F400 H'FC00 On-chip RAM*2 External address space H'F400 H'FBFF On-chip RAM H'FC00 External address H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF08 External address space H'FE40 Internal I/O registers H'FF07 H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF H'FF28 Internal I/O registers H'FFFF Notes: 1. Modes 2 and 3 only apply to the H8S/2351. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-1 Memory Map in Each Operating Mode 76 Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6*1 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7*1 (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM External address space H'010000 H'00FFFF External address space H'FFF400 On-chip RAM*2 space H'FFF400 On-chip RAM*2 space H'FFF400 H'FFFBFF On-chip RAM H'FFFC00 External address H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFC00 External address H'FFFE40 Internal I/O registers H'FFFF08 External address space H'FFFE40 Internal I/O registers H'FFFF07 H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF H'FFFF28 Internal I/O registers H'FFFFFF Notes: 1. Modes 6 and 7 only apply to the H8S/2351. 2. External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3-1 Memory Map in Each Operating Mode (cont) 77 78 Section 4 Exception Handling 4.1 4.1.1 Overview Exception Handling Types and Priority As table 4-1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4-1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times, in the program execution state. Exception handling sources, the stack structure, and the operation of the CPU vary depending on the interrupt control mode set by the INTM0 and INTM1 bits of SYSCR. Table 4-1 Priority High Exception Types and Priority Exception Type Reset Start of Exception Handling Starts immediately after a low-to-high transition at the RES pin, or when the watchdog timer overflows. The CPU enters the power-on reset state when the NMI pin is high, or the manual reset state when the NMI pin is low. Starts when execution of the current instruction or exception handling ends, if the trace (T) bit is set to 1 Starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued* 2 Trace* 1 Interrupt Low Trap instruction (TRAPA)*3 Started by execution of a trap instruction (TRAPA) Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not executed after execution of an RTE instruction. 2. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC instruction execution, or on completion of reset exception handling. 3. Trap instruction exception handling requests are accepted at all times in program execution state. 79 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extended register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address. For a reset exception, steps 2 and 3 above are carried out. 4.1.3 Exception Vector Table The exception sources are classified as shown in figure 4-1. Different vector addresses are assigned to different exception sources. Table 4-2 lists the exception sources and their vector addresses. Reset Trace Exception sources Interrupts Power-on reset Manual reset External interrupts: NMI, IRQ7 to IRQ0 Internal interrupts: 42 interrupt sources in on-chip supporting modules Trap instruction Figure 4-1 Exception Sources In modes 6 and 7 in the H8S/2351, the on-chip ROM available for use after a power-on reset is the 64-kbyte area comprising addresses H'000000 to H'00FFFF. Care is required when setting vector addresses. 80 Table 4-2 Exception Vector Table Vector Address* 1 Exception Source Power-on reset Manual reset Reserved for system use Vector Number 0 1 2 3 4 Normal Mode H'0000 to H'0001 H'0002 to H'0003 H'0004 to H'0006 H'0006 to H'0007 H'0008 to H'0009 H'000A to H'000B H'000C to H'000D H'000E to H'000F H'0010 to H'0011 H'0012 to H'0013 H'0014 to H'0015 H'0016 to H'0017 H'0018 to H'0019 H'001A to H'001B H'001C to H'001D H'001E to H'001F H'0020 to H'0021 H'0022 to H'0023 H'0024 to H'0025 H'0026 to H'0027 H'0028 to H'0029 H'002A to H'002B H'002C to H'002D H'002E to H'002F H'0030 to H'0031 H'00B6 to H'00B7 Advanced Mode H'0000 to H'0003 H'0004 to H'0007 H'0008 to H'000B H'000C to H'000F H'0010 to H'0013 H'0014 to H'0017 H'0018 to H'001B H'001C to H'001F H'0020 to H'0023 H'0024 to H'0027 H'0028 to H'002B H'002C to H'002F H'0030 to H'0033 H'0034 to H'0037 H'0038 to H'003B H'003C to H'003F H'0040 to H'0043 H'0044 to H'0047 H'0048 to H'004B H'004C to H'004F H'0050 to H'0053 H'0054 to H'0057 H'0058 to H'005B H'005C to H'005F H'0060 to H'0063 H'016C to H'016F Trace Reserved for system use External interrupt NMI 5 6 7 8 9 10 11 Trap instruction (4 sources) Reserved for system use 12 13 14 15 External interrupt IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 16 17 18 19 20 21 22 23 24 91 Internal interrupt* 2 Notes: 1. Lower 16 bits of the address. 2. For details of internal interrupt vectors, see section 5.3.3, Interrupt Exception Handling Vector Table. 81 4.2 4.2.1 Reset Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the H8S/2350 Series enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. The level of the NMI pin at reset determines whether the type of reset is a power-on reset or a manual reset. The H8S/2350 Series can also be reset by overflow of the watchdog timer. For details see section 12, Watchdog Timer. 4.2.2 Reset Types A reset can be of either of two types: a power-on reset or a manual reset. Reset types are shown in table 4-3. A power-on reset should be used when powering on. The internal state of the CPU is initialized by either type of reset. A power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and I/O ports, which retain their previous states. With a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module I/O pins are switched to I/O ports controlled by DDR and DR. Table 4-3 Reset Types Reset Transition Conditions Type Power-on reset Manual reset NMI High Low RES Low Low CPU Initialized Initialized Internal State On-Chip Supporting Modules Initialized Initialized, except for bus controller and I/O ports A reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset. 82 4.2.3 Reset Sequence The H8S/2350 Series enters the reset state when the RES pin goes low. To ensure that the H8S/2350 Series is reset, hold the RES pin low for at least 20 ms at power-up. To reset the H8S/2350 Series during operation, hold the RES pin low for at least 20 states. When the RES pin goes high after being held low for the necessary time, the H8S/2350 Series starts reset exception handling as follows: 1. The internal state of the CPU and the registers of the on-chip supporting modules are initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR. 2. The reset exception handling vector address is read and transferred to the PC, and program execution starts from the address indicated by the PC. Figures 4-2 and 4-3 show examples of the reset sequence. Vector Internal Prefetch of first program fetch processing instruction o RES Internal address bus Internal read signal Internal write signal Internal data bus (2) (1) (3) High (4) (1) Reset exception handling vector address ((1) = H'0000) (2) Start address (contents of reset exception handling vector address) (3) Start address ((3) = (2)) (4) First program instruction Figure 4-2 Reset Sequence (Modes 2 and 3) 83 Vector fetch Internal Prefetch of first processing program instruction * * * o RES Address bus RD HWR, LWR D15 to D0 (2) (1) (3) (5) High (4) (6) (1) (3) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) (2) (4) Start address (contents of reset exception handling vector address) (5) Start address ((5) = (2) (4)) (6) First program instruction Note: * 3 program wait states are inserted. Figure 4-3 Reset Sequence (Mode 4) 4.2.4 Interrupts after Reset If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests, including NMI, are disabled immediately after a reset. Since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: MOV.L #xx:32, SP). 4.2.5 State of On-Chip Supporting Modules after Reset Release After reset release, MSTPCR is initialized to H'3FFF and all modules except the DMAC and DTC enter module stop mode. Consequently, on-chip supporting module registers cannot be read or written to. Register reading and writing is enabled when module stop mode is exited. 84 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4-4 shows the state of CCR and EXR after execution of trace exception handling. Interrupts are accepted even within the trace exception handling routine. The T bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the RTE instruction, trace mode resumes. Trace exception handling is not carried out after execution of the RTE instruction. Table 4-4 Status of CCR and EXR after Trace Exception Handling CCR Interrupt Control Mode 0 2 1 I UI EXR I2 to I0 T Trace exception handling cannot be used. -- -- 0 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 85 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 42 internal sources in the on-chip supporting modules. Figure 4-4 classifies the interrupt sources and the number of interrupts of each type. The on-chip supporting modules that can request interrupts include the watchdog timer (WDT), refresh timer, 16-bit timer-pulse unit (TPU), serial communication interface (SCI), data transfer controller (DTC), DMA controller (DMAC), and A/D converter. Each interrupt source has a separate vector address. NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt control modes and can assign interrupts other than NMI to eight priority/mask levels to enable multiplexed interrupt control. For details of interrupts, see section 5, Interrupt Controller. External interrupts Interrupts NMI (1) IRQ7 to IRQ0 (8) Internal interrupts WDT*1 (1) Refresh timer*2 (1) TPU (26) SCI (8) DTC (1) DMAC (4) A/D converter (1) Notes: Numbers in parentheses are the numbers of interrupt sources. 1. When the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. 2. When the refresh timer is used as an interval timer, it generates an interrupt request at each compare match. Figure 4-4 Interrupt Sources and Number of Interrupts 86 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4-5 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4-5 Status of CCR and EXR after Trap Instruction Exception Handling CCR Interrupt Control Mode 0 2 I 1 1 UI -- -- I2 to I0 -- -- EXR T -- 0 Legend 1: Set to 1 0: Cleared to 0 --: Retains value prior to execution. 87 4.6 Stack Status after Exception Handling Figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. SP SP CCR CCR* PC (16 bits) EXR Reserved* CCR CCR* PC (16 bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-5 (1) Stack Status after Exception Handling (Normal Modes) SP SP CCR PC (24bits) EXR Reserved* CCR PC (24bits) (a) Interrupt control mode 0 Note: * Ignored on return. (b) Interrupt control mode 2 Figure 4-5 (2) Stack Status after Exception Handling (Advanced Modes) 88 4.7 Notes on Use of the Stack When accessing word data or longword data, the H8S/2350 Series assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W PUSH.L Rn ERn (or MOV.W Rn, @-SP) (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.W POP.L Rn ERn (or MOV.W @SP+, Rn) (or MOV.L @SP+, ERn) Setting SP to an odd value may lead to a malfunction. Figure 4-6 shows an example of what happens when the SP value is odd. CCR SP PC SP R1L PC H'FFFEFA H'FFFEFB H'FFFEFC H'FFFEFD H'FFFEFF SP TRAP instruction executed MOV.B R1L, @-ER7 SP set to H'FFFEFF Data saved above SP Contents of CCR lost Legend CCR: Condition code register PC: Program counter R1L: General register R1L SP: Stack pointer Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. Figure 4-6 Operation when SP Value is Odd 89 90 Section 5 Interrupt Controller 5.1 5.1.1 Overview Features The H8S/2350 Series controls interrupts by means of an interrupt controller. The interrupt controller has the following features: * Two interrupt control modes Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the system control register (SYSCR). * Priorities settable with IPR An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority levels can be set for each module for all interrupts except NMI. NMI is assigned the highest priority level of 8, and can be accepted at all times. * Independent vector addresses All interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. * Nine external interrupts NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can be selected for IRQ7 to IRQ0. * DTC and DMAC control DTC and DMAC activation is performed by means of interrupts. 91 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in Figure 5-1. INTM1 INTM0 SYSCR NMIEG NMI input IRQ input NMI input unit IRQ input unit ISR ISCR IER Priority determination I, UI I2 to I0 Interrupt request Vector number CPU Internal interrupt request WOVI to TEI CCR EXR IPR Interrupt controller Legend ISCR IER ISR IPR SYSCR : IRQ sense control register : IRQ enable register : IRQ status register : Interrupt priority register : System control register Figure 5-1 Block Diagram of Interrupt Controller 92 5.1.3 Pin Configuration Table 5-1 summarizes the pins of the interrupt controller. Table 5-1 Name Nonmaskable interrupt External interrupt requests 7 to 0 Interrupt Controller Pins Symbol NMI I/O Input Function Nonmaskable external interrupt; rising or falling edge can be selected Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected IRQ7 to IRQ0 Input 5.1.4 Register Configuration Table 5-2 summarizes the registers of the interrupt controller. Table 5-2 Name System control register IRQ sense control register H IRQ sense control register L IRQ enable register IRQ status register Interrupt priority register A Interrupt priority register B Interrupt priority register C Interrupt priority register D Interrupt priority register E Interrupt priority register F Interrupt priority register G Interrupt priority register H Interrupt priority register I Interrupt priority register J Interrupt priority register K Interrupt Controller Registers Abbreviation SYSCR ISCRH ISCRL IER ISR IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 Initial Value H'01 H'00 H'00 H'00 H'00 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 H'77 Address* 1 H'FF39 H'FF2C H'FF2D H'FF2E H'FF2F H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 93 5.2 5.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W Initial value: R/W : SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, System Control Register (SYSCR). SYSCR is initialized to H'01 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 5 and 4--Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select one of two interrupt control modes for the interrupt controller. Bit 5 INTM1 0 Bit 4 INTM0 0 1 1 0 1 Interrupt Control Mode 0 -- 2 -- Description Interrupts are controlled by I bit Setting prohibited Interrupts are controlled by bits I2 to I0, and IPR Setting prohibited (Initial value) Bit 3--NMI Edge Select (NMIEG): Selects the input edge for the NMI pin. Bit 3 NMIEG 0 1 Description Interrupt request generated at falling edge of NMI input Interrupt request generated at rising edge of NMI input (Initial value) 94 5.2.2 Bit Interrupt Priority Registers A to K (IPRA to IPRK) : 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W 3 -- 0 -- 2 IPR2 1 R/W 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value: R/W : The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5-3. The IPR registers set a priority (level 7 to 0) for each interrupt source other than NMI. The IPR registers are initialized to H'77 by a reset and in hardware standby mode. Bits 7 and 3--Reserved: Read-only bits, always read as 0. Table 5-3 Correspondence between Interrupt Sources and IPR Settings Bits Register IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK 6 to 4 IRQ0 IRQ2 IRQ3 IRQ6 IRQ7 Watchdog timer --* TPU channel 0 TPU channel 2 TPU channel 4 --* DMAC SCI channel 1 2 to 0 IRQ1 IRQ4 IRQ5 DTC Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 --* SCI channel 0 --* Note: * Reserved bits. These bits cannot be modified and are always read as 1. 95 As shown in table 5-3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected. This interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (I2 to I0) in the extend register (EXR) in the CPU, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the CPU. 5.2.3 IRQ Enable Register (IER) IER is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests IRQ7 to IRQ0. Bit : 7 IRQ7E Initial value: R/W : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 IRQ4E 0 R/W 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IER is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 Enable (IRQ7E to IRQ0E): These bits select whether IRQ7 to IRQ0 are enabled or disabled. Bit n IRQnE 0 1 Description IRQn interrupts disabled IRQn interrupts enabled (n = 7 to 0) (Initial value) 96 5.2.4 ISCRH Bit IRQ Sense Control Registers H and L (ISCRH, ISCRL) : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value: R/W ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W : IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value: R/W : ISCR registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins IRQ7 to IRQ0. ISCR registers are initialized to H'0000 by a reset and in hardware standby mode. Bits 15 to 0: IRQ7 Sense Control A and B (IRQ7SCA, IRQ7SCB) to IRQ0 Sense Control A and B (IRQ0SCA, IRQ0SCB) Bits 15 to 0 IRQ7SCB to IRQ0SCB 0 IRQ7SCA to IRQ0SCA 0 1 1 0 1 Description Interrupt request generated at IRQ7 to IRQ0 input low level (initial value) Interrupt request generated at falling edge of IRQ7 to IRQ0 input Interrupt request generated at rising edge of IRQ7 to IRQ0 input Interrupt request generated at both falling and rising edges of IRQ7 to IRQ0 input 97 5.2.5 Bit IRQ Status Register (ISR) : 7 IRQ7F 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 IRQ4F 0 R/(W)* 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* Initial value: R/W : Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode. Bits 7 to 0--IRQ7 to IRQ0 flags (IRQ7F to IRQ0F): These bits indicate the status of IRQ7 to IRQ0 interrupt requests. Bit n IRQnF 0 Description [Clearing conditions] (Initial value) * * * * Cleared by reading IRQnF flag when IRQnF = 1, then writing 0 to IRQnF flag When interrupt exception handling is executed when low-level detection is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high When IRQn interrupt exception handling is executed when falling, rising, or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1) When the DTC is activated by an IRQn interrupt, and the DISEL bit in MRB of the DTC is cleared to 0 1 [Setting conditions] * * * * When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA = 0) When a falling edge occurs in IRQn input when falling edge detection is set (IRQnSCB = 0, IRQnSCA = 1) When a rising edge occurs in IRQn input when rising edge detection is set (IRQnSCB = 1, IRQnSCA = 0) When a falling or rising edge occurs in IRQn input when both-edge detection is set (IRQnSCB = IRQnSCA = 1) (n = 7 to 0) 98 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (42 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. Of these, NMI and IRQ2 to IRQ0 can be used to restore the H8S/2350 Series from software standby mode. NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU regardless of the status of the CPU interrupt mask bits. The NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling edge on the NMI pin. The vector number for NMI interrupt exception handling is 7. IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7 to IRQ0. Interrupts IRQ7 to IRQ0 have the following features: * Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins IRQ7 to IRQ0. * Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER. * The interrupt priority level can be set with IPR. * The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0 by software. A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5-2. IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn input Clear signal Note: n: 7 to 0 IRQn interrupt S R Q request Figure 5-2 Block Diagram of Interrupts IRQ7 to IRQ0 99 Figure 5-3 shows the timing of setting IRQnF. o IRQn input pin IRQnF Figure 5-3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16. Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for input or output. However, when a pin is used as an external interrupt input pin, do not clear the corresponding DDR to 0 and use the pin as an I/O pin for another function. 5.3.2 Internal Interrupts There are 42 sources for internal interrupts from on-chip supporting modules. * For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. * The interrupt priority level can be set by means of IPR. * The DMAC and DTC can be activated by a TPU, SCI, or other interrupt request. When the DMAC or DTC is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 Interrupt Exception Handling Vector Table Table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. For default priorities, the lower the vector number, the higher the priority. Priorities among modules can be set by means of the IPR. The situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table 5-4. 100 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities Origin of Interrupt Source External pin Vector Address* Vector Normal Number Mode 7 16 17 18 19 20 21 22 23 DTC 24 H'000E H'0020 H'0022 H'0024 H'0026 H'0028 H'002A H'002C H'002E H'0030 H'0032 H'0034 H'0036 H'0038 H'003A H'003C H'003E H'0040 H'0042 H'0044 H'0046 H'0048 H'004A H'004C H'004E Advanced Mode H'001C H'0040 H'0044 H'0048 H'004C H'0050 H'0054 H'0058 H'005C H'0060 H'0064 H'0068 H'006C H'0070 H'0074 H'0078 H'007C H'0080 H'0084 H'0088 H'008C H'0090 H'0094 H'0098 H'009C IPRF6 to 4 IPRA6 to 4 IPRA2 to 0 IPRB6 to 4 IPRB2 to 0 IPRC6 to 4 IPRC2 to 0 IPRD6 to 4 IPRD2 to 0 IPRE6 to 4 IPRE2 to 0 IPR Priority High Interrupt Source NMI IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 SWDTEND (software activation interrupt end) WOVI (interval timer) CMI (compare match) Reserved ADI (A/D conversion end) Reserved Watchdog 25 timer Refresh controller -- A/D -- 26 27 28 29 30 31 TGI0A (TGR0A input capture/compare match) TGI0B (TGR0B input capture/compare match) TGI0C (TGR0C input capture/compare match) TGI0D (TGR0D input capture/compare match) TCI0V (overflow 0) Reserved TPU 32 channel 0 33 34 35 36 -- 37 38 39 Low Note: * Lower 16 bits of the start address. 101 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Interrupt Source Vector Address* Vector Normal Number Mode H'0050 H'0052 H'0054 H'0056 H'0058 H'005A H'005C H'005E H'0060 H'0062 H'0064 H'0066 H'0068 H'006A H'006C H'006E H'0070 H'0072 H'0074 H'0076 H'0078 H'007A H'007C H'007E Advanced Mode H'00A0 H'00A4 H'00A8 H'00AC H'00B0 H'00B4 H'00B8 H'00BC H'00C0 H'00C4 H'00C8 H'00CC H'00D0 H'00D4 H'00D8 H'00DC H'00E0 H'00E4 H'00E8 H'00EC H'00F0 H'00F4 H'00F8 H'00FC IPRH2 to 0 IPRH6 to 4 IPRG2 to 0 IPRG6 to 4 IPR IPRF2 to 0 Priority High Interrupt Source TGI1A (TGR1A input capture/compare match) TGI1B (TGR1B input capture/compare match) TCI1V (overflow 1) TCI1U (underflow 1) TGI2A (TGR2A input capture/compare match) TGI2B (TGR2B input capture/compare match) TCI2V (overflow 2) TCI2U (underflow 2) TGI3A (TGR3A input capture/compare match) TGI3B (TGR3B input capture/compare match) TGI3C (TGR3C input capture/compare match) TGI3D (TGR3D input capture/compare match) TCI3V (overflow 3) Reserved TPU 40 channel 1 41 42 43 TPU 44 channel 2 45 46 47 TPU 48 channel 3 49 50 51 52 -- 53 54 55 TGI4A (TGR4A input capture/compare match) TGI4B (TGR4B input capture/compare match) TCI4V (overflow 4) TCI4U (underflow 4) TGI5A (TGR5A input capture/compare match) TGI5B (TGR5B input capture/compare match) TCI5V (overflow 5) TCI5U (underflow 5) TPU 56 channel 4 57 58 59 TPU 60 channel 5 61 62 63 Low Note: * Lower 16 bits of the start address. 102 Table 5-4 Interrupt Sources, Vector Addresses, and Interrupt Priorities (cont) Origin of Interrupt Source -- Vector Address* Vector Normal Number Mode 64 65 66 67 68 69 70 71 72 73 74 75 -- H'0080 H'0082 H'0084 H'0086 H'0088 H'008A H'008C H'008E H'0090 H'0092 H'0094 H'0096 H'0098 H'009A H'009C H'009E H'00A0 H'00A2 H'00A4 H'00A6 H'00A8 H'00AA H'00AC H'00AE H'00B0 H'00B2 H'00B4 H'00B6 Advanced Mode H'0100 H'0104 H'0108 H'010C H'0110 H'0114 H'0118 H'011C H'0120 H'0124 H'0128 H'012C H'0130 H'0134 H'0138 H'013C H'0140 H'0144 H'0148 H'014C H'0150 H'0154 H'0158 H'015C H'0160 H'0164 H'0168 H'016C IPRJ6 to 4 IPR Priority High Interrupt Source Reserved DEND0A (channel 0/ channel 0A transfer end) DEND0B (channel 0B transfer end) DEND1A (channel 1/ channel 1A transfer end) DEND1B (channel 1B transfer end) Reserved DMAC 76 77 78 79 SCI 80 ERI0 (receive error 0) RXI0 (reception completed 0) channel 0 81 82 TXI0 (transmit data empty 0) 83 TEI0 (transmission end 0) SCI ERI1 (receive error 1) RXI1 (reception completed 1) channel 1 TXI1 (transmit data empty 1) TEI1 (transmission end 1) Reserved -- 84 85 86 87 88 89 90 91 IPRJ2 to 0 IPRK6 to 4 IPRK2 to 0 Low Note: * Lower 16 bits of the start address. 103 5.4 5.4.1 Interrupt Operation Interrupt Control Modes and Interrupt Operation Interrupt operations in the H8S/2350 Series differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. Table 5-5 shows the interrupt control modes. The interrupt controller performs interrupt control according to the interrupt control mode set by the INTM1 and INTM0 bits in SYSCR, the priorities set in IPR, and the masking state indicated by the I and UI bits in the CPU's CCR, and bits I2 to I0 in EXR. Table 5-5 Interrupt Control Modes Interrupt Mask Bits Description I -- I2 to I0 Interrupt mask control is performed by the I bit. Setting prohibited 8-level interrupt mask control is performed by bits I2 to I0. 8 priority levels can be set with IPR. Setting prohibited SYSCR Interrupt Priority Setting Control Mode INTM1 INTM0 Registers 0 -- 2 1 0 0 1 0 -- -- IPR -- 1 -- -- 104 Figure 5-4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Interrupt source Default priority determination 8-level mask control Vector number IPR I2 to I0 Interrupt control mode 2 Figure 5-4 Block Diagram of Interrupt Control Operation (1) Interrupt Acceptance Control In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5-6 shows the interrupts selected in each interrupt control mode. Table 5-6 Interrupts Selected in Each Interrupt Control Mode (1) Interrupt Mask Bits Interrupt Control Mode 0 I 0 1 2 Legend * : Don't care * Selected Interrupts All interrupts NMI interrupts All interrupts 105 (2) 8-Level Control In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5-7 Interrupts Selected in Each Interrupt Control Mode (2) Selected Interrupts All interrupts Highest-priority-level (IPR) interrupt whose priority level is greater than the mask level (IPR > I2 to I0). Interrupt Control Mode 0 2 (3) Default Priority Determination When an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. If the same value is set for IPR, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. Interrupt sources with a lower priority than the accepted interrupt source are held pending. Table 5-8 shows operations and control signal functions in each interrupt control mode. Table 5-8 Operations and Control Signal Functions in Each Interrupt Control Mode Interrupt Acceptance Control I IM X --* 1 Interrupt Control Setting Mode INTM1 INTM0 0 2 0 1 0 0 Default 8-Level Control Priority I2 to I0 IPR Determination X -- IM --* 2 PR T (Trace) -- T Legend : Interrupt operation control performed X : No operation. (All interrupts enabled) IM : Used as interrupt mask bit PR : Sets priority. -- : Not used. * 1 : Set to 1 when interrupt is accepted. * 2 : Keep the initial setting. 106 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU's CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending. [3] Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] Next, the I bit in CCR is set to 1. This masks all interrupts except NMI. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 107 Program execution status Interrupt generated? Yes Yes No NMI No No I=0 Yes Hold pending No IRQ0 Yes No IRQ1 Yes TEI2 Yes Save PC and CCR I1 Read vector address Branch to interrupt handling routine Figure 5-5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 108 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] When interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in IPR is selected, and lower-priority interrupt requests are held pending. If a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] Next, the priority of the selected interrupt request is compared with the interrupt mask level set in EXR. An interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] When an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of the accepted interrupt. If the accepted interrupt is NMI, the interrupt mask level is set to H'7. [7] A vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address. 109 Program execution status Interrupt generated? Yes Yes NMI No No No Level 7 interrupt? Yes Mask level 6 or below? Yes Level 6 interrupt? No Yes Mask level 5 or below? Yes No Level 1 interrupt? No Yes No Mask level 0 Yes No Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5-6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 110 5.4.4 Interrupt Exception Handling Sequence Figure 5-7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. 111 112 Interrupt acceptance Instruction prefetch Stack Vector fetch Internal operation Internal operation Interrupt service routine instruction prefetch (1) (7) Interrupt level determination Wait for end of instruction o Interrupt request signal Internal address bus (3) (5) (9) (11) (13) Internal read signal Internal write signal (2) (4) (6) (8) (10) (12) (14) Figure 5-7 Interrupt Exception Handling Internal data us (1) Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2) (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.) (5) SP-2 (7) SP-4 (6) (8) Saved PC and saved CCR (9) (11) Vector address (10) (12) Interrupt handling routine start address (vector address contents) (13) Interrupt handling routine start address ((13) = (10) (12)) (14) First instruction of interrupt handling routine 5.4.5 Interrupt Response Times The H8S/2350 Series is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM* and the stack area in on-chip RAM, enabling highspeed processing. Table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5-9 are explained in table 5-10. Note: * Only applies to the H8S/2351. Table 5-9 Interrupt Response Times Normal Mode No. 1 2 3 4 5 6 Execution Status Interrupt priority determination* 1 Advanced Mode INTM1 = 0 3 1 to 19+2*SI 2*S K 2*S I 2*S I 2 12 to 32 INTM1 = 1 3 1 to 19+2*SI 3*S K 2*S I 2*S I 2 13 to 33 INTM1 = 0 3 INTM1 = 1 3 1 to 19+2*SI 3*S K SI 2*S I 2 12 to 32 Number of wait states until executing 1 to instruction ends* 2 19+2*SI PC, CCR, EXR stack save Vector fetch Instruction fetch* 3 4 2*S K SI 2*S I 2 11 to 31 Internal processing* Total (using on-chip memory) Notes: 1. 2. 3. 4. Two states in case of internal interrupt. Refers to MULXS and DIVXS instructions. Prefetch after interrupt acceptance and interrupt handling routine prefetch. Internal processing after interrupt acceptance and internal processing after vector fetch. Table 5-10 Number of States in Interrupt Handling Routine Execution Statuses Object of Access External Device 8 Bit Bus Symbol Instruction fetch Branch address read Stack manipulation SI SJ SK Internal Memory 1 2-State Access 4 3-State Access 6+2m 16 Bit Bus 2-State Access 2 3-State Access 3+m Legend m : Number of wait states in an external device access. 113 5.5 5.5.1 Usage Notes Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. However, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt source flag is cleared. Figure 5-8 shows an example in which the TGIEA bit in the TPU's TIER0 register is cleared to 0. TIER0 write cycle by CPU TGI0A exception handling o Internal address bus TIER0 address Internal write signal TGIEA TGFA TGI0A interrupt signal Figure 5-8 Contention between Interrupt Generation and Disabling The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 114 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 Times when Interrupts are Disabled There are times when interrupt acceptance is disabled by the interrupt controller. The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has updated the mask level with an LDC, ANDC, ORC, or XORC instruction. 5.5.4 Interrupts during Execution of EEPMOV Instruction Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction. With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer is not accepted until the move is completed. With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this case is the address of the next instruction. Therefore, if an interrupt is generated during execution of an EEPMOV.W instruction, the following coding should be used. L1: EEPMOV.W MOV.W BNE R4,R4 L1 115 5.6 5.6.1 DTC and DMAC Activation by Interrupt Overview The DTC and DMAC can be activated by an interrupt. In this case, the following options are available: * * * * Interrupt request to CPU Activation request to DTC Activation request to DMAC Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC, see section 8, Data Transfer Controller, and section 7, DMA Controller. 5.6.2 Block Diagram Figure 5-9 shows a block diagram of the DTC and DMAC interrupt controller. DMAC Disable signal Clear signal Interrupt request IRQ interrupt Interrupt source clear signal Selection circuit Select signal Clear signal DTCER DTC activation request vector number Control logic Clear signal DTC On-chip supporting module DTVECR SWDTE clear signal Determination of priority CPU interrupt request vector number CPU I, I2 to I0 Interrupt controller Figure 5-9 Interrupt Control for DTC and DMAC 116 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC control. (1) Selection of Interrupt Source: With the DMAC, the activation source is input directly to each channel. The activation source for each DMAC channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC can be selected with the DTA bit of DMABCR. When the DTA bit is set to 1, the interrupt source constituting that DMAC activation source is not a DTC activation source or CPU interrupt source. For interrupt sources other than interrupts managed by the DMAC, it is possible to select DTC activation request or CPU interrupt request with the DTCE bit of DTCEA to DTCEF in the DTC. After a DTC data transfer, the DTCE bit can be cleared to 0 and an interrupt request sent to the CPU in accordance with the specification of the DISEL bit of MRB in the DTC. When the DTC has performed the specified number of data transfers and the transfer counter value is zero, the DTCE bit is cleared to 0 and an interrupt request is sent to the CPU after the DTC data transfer. (2) Determination of Priority: The DTC activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. See section 7.6, Interrupts, and section 8.3.3, DTC Vector Table, for the respective priorities. With the DMAC, the activation source is input directly to each channel. (3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception handling. If the same interrupt is selected as a DMAC activation source and a DTC activation source or CPU interrupt source, operations are performed for them independently according to their respective operating statuses and bus mastership priorities. Table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the DTA bit of DMABCR in the DMAC, the DTCE bit of DTCEA to DTCEF in the DTC and the DISEL bit of MRB in the DTC. 117 Table 5-12 Interrupt Source Selection and Clearing Control Settings DMAC DTA 0 DTC DTCE 0 1 DISEL * 0 1 1 * * Interrupt Source Selection/Clearing Control DMAC DTC X CPU X X X Legend : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X : The relevant bit cannot be used. * : Don't care (4) Notes on Use: SCI and A/D converter interrupt sources are cleared when the DMAC or DTC reads or writes to the prescribed register, and are not dependent upon the DTA bit or DISEL bit. 118 Section 6 Bus Controller 6.1 Overview The H8S/2350 Series has a built-in bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. The bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the CPU, DMA controller (DMAC), and data transfer controller (DTC). 6.1.1 Features The features of the bus controller are listed below. * Manages external address space in area units In advanced mode, manages the external space as 8 areas of 2-Mbytes In normal mode, manages the external space as a single area Bus specifications can be set independently for each area DRAM/burst ROM interfaces can be set * Basic bus interface Chip select (CS0 to CS7) can be output for areas 0 to 7 8-bit access or 16-bit access can be selected for each area 2-state access or 3-state access can be selected for each area Program wait states can be inserted for each area * DRAM interface DRAM interface can be set for areas 2 to 5 (in advanced mode) Row address/column address multiplexed output (8/9/10 bits) Two byte access methods (2-CAS) Burst operation (fast page mode) TP cycle insertion to secure RAS precharging time Choice of CAS-before-RAS refreshing or self-refreshing * Burst ROM interface Burst ROM interface can be set for area 0 Choice of 1- or 2-state burst access 119 * Idle cycle insertion An idle cycle can be inserted in case of an external read cycle between different areas An idle cycle can be inserted in case of an external write cycle immediately after an external read cycle * Write buffer functions External write cycle and internal access can be executed in parallel DMAC single-address mode and internal access can be executed in parallel * Bus arbitration function Includes a bus arbiter that arbitrates bus mastership among the CPU, DMAC, and DTC * Other features Refresh counter (refresh timer) can be used as an interval timer External bus release function 120 6.1.2 Block Diagram Figure 6-1 shows a block diagram of the bus controller. CS0 to CS7 Area decoder Internal address bus ABWCR External bus control signals ASTCR BCRH BCRL BREQ BACK BREQO Bus controller Internal control signals Bus mode signal WAIT WCRH WCRL DRAM/PSRAM controller MCR External DRAM signals DRAMCR RTCNT RTCOR CPU bus request signal DTC bus request signal Bus arbiter DMAC bus request signal CPU bus acknowledge signal DTC bus acknowledge signal DMAC bus acknowledge signal Figure 6-1 Block Diagram of Bus Controller Internal data bus Wait controller 121 6.1.3 Pin Configuration Table 6-1 summarizes the pins of the bus controller. Table 6-1 Name Address strobe Read High write/write enable Bus Controller Pins Symbol I/O AS RD HWR Output Output Output Function Strobe signal indicating that address output on address bus is enabled. Strobe signal indicating that external space is being read. Strobe signal indicating that external space is to be written, and upper half (D 15 to D8) of data bus is enabled. 2-CAS DRAM write enable signal. Strobe signal indicating that external space is to be written, and lower half (D7 to D0) of data bus is enabled. Strobe signal indicating that area 0 is selected. Strobe signal indicating that area 1 is selected. Strobe signal indicating that area 2 is selected. DRAM row address strobe signal when area 2 is in DRAM space. Strobe signal indicating that area 3 is selected. DRAM row address strobe signal when area 3 is in DRAM space. Strobe signal indicating that area 4 is selected. DRAM row address strobe signal when area 4 is in DRAM space. Strobe signal indicating that area 5 is selected. DRAM row address strobe signal when area 5 is in DRAM space. Strobe signal indicating that area 6 is selected. Strobe signal indicating that area 7 is selected. Low write LWR Output Chip select 0 Chip select 1 Chip select 2/row address strobe 2 CS0 CS1 CS2 Output Output Output Chip select 3/row address strobe 3 CS3 Output Chip select 4/row address strobe 4 CS4 Output Chip select 5/row address strobe 5 CS5 Output Chip select 6 Chip select 7 CS6 CS7 Output Output 122 Table 6-1 Name Bus Controller Pins (cont) Symbol I/O CAS LCAS WAIT BREQ BACK Output Output Input Input Output Function 2-CAS DRAM upper column address strobe signal. DRAM lower column address strobe signal. Wait request signal when accessing external 3-state access space. Request signal that releases bus to external device. Acknowledge signal indicating that bus has been released. External bus request signal used when internal bus master accesses external space when external bus is released. Upper column address strobe Lower column strobe Wait Bus request Bus request acknowledge Bus request output BREQO Output 6.1.4 Register Configuration Table 6-2 summarizes the registers of the bus controller. Table 6-2 Bus Controller Registers Initial Value Name Bus width control register Access state control register Wait control register H Wait control register L Bus control register H Bus control register L Memory control register DRAM control register Refresh timer/counter Refresh time constant register Abbreviation ABWCR ASTCR WCRH WCRL BCRH BCRL MCR DRAMCR RTCNT RTCOR R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Power-On Reset H'FF/H'00* 2 H'FF H'FF H'FF H'D0 H'3C H'00 H'00 H'00 H'FF Manual Reset Retained Retained Retained Retained Retained Retained Retained Retained Retained Retained Address* 1 H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 Notes: 1. Lower 16 bits of the address. 2. Determined by the MCU operating mode. 123 6.2 6.2.1 Bit Register Descriptions Bus Width Control Register (ABWCR) : 7 ABW7 6 ABW6 1 R/W 0 R/W 5 ABW5 1 R/W 0 R/W 4 ABW4 1 R/W 0 R/W 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 ABW1 1 R/W 0 R/W 0 ABW0 1 R/W 0 R/W Modes 1 to 3, 5 to 7* Initial value : 1 RW Mode 4 Initial value : RW : 0 R/W : R/W ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. ABWCR sets the data bus width for the external memory space. The bus width for on-chip memory and internal I/O registers is fixed regardless of the settings in ABWCR. In normal mode, the settings of bits ABW7 to ABW1 have no effect on operation. After a power-on reset and in hardware standby mode, ABWCR is initialized to H'FF in modes 1, 2, 3, and 5, 6, 7*, and to H'00 in mode 4. It is not initialized by a manual reset or in software standby mode. Note: * Modes 2, 3, 6 and 7 only apply to the H8S/2351. Bits 7 to 0--Area 7 to 0 Bus Width Control (ABW7 to ABW0): These bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. In normal mode, only part of area 0 is enabled, and the ABW0 bit selects whether external space is to be designated for 8-bit access or 16-bit access . Bit n ABWn 0 1 Description Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) 124 6.2.2 Bit Access State Control Register (ASTCR) : 7 AST7 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W 3 AST3 1 R/W 2 AST2 1 R/W 1 AST1 1 R/W 0 AST0 1 R/W Initial value : R/W : ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space. The number of access states for on-chip memory and internal I/O registers is fixed regardless of the settings in ASTCR. In normal mode, the settings of bits AST7 to AST1 have no effect on operation. ASTCR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bits 7 to 0--Area 7 to 0 Access State Control (AST7 to AST0): These bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. In normal mode, only part of area 0 is enabled, and the AST0 bit selects whether external space is to be designated for 2-state access or 3-state access. Wait state insertion is enabled or disabled at the same time. Bit n ASTn 0 1 Description Area n is designated for 2-state access Wait state insertion in area n external space is disabled Area n is designated for 3-state access Wait state insertion in area n external space is enabled (Initial value) (n = 7 to 0) 125 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. In normal mode, only part of area is 0 is enabled, and bits W01 and W00 select the number of program wait states for the external space . The settings of bits W71, W70 to W11, and W10 have no effect on operation. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a power-on reset and in hardware standby mode. They are not initialized by a manual reset or in software standby mode. (1) WCRH Bit : 7 W71 Initial value : R/W : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 W51 1 R/W 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bits 7 and 6--Area 7 Wait Control 1 and 0 (W71, W70): These bits select the number of program wait states when area 7 in external space is accessed while the AST7 bit in ASTCR is set to 1. Bit 7 W71 0 Bit 6 W70 0 1 1 0 1 Description Program wait not inserted when external space area 7 is accessed 1 program wait state inserted when external space area 7 is accessed 2 program wait states inserted when external space area 7 is accessed 3 program wait states inserted when external space area 7 is accessed (Initial value) 126 Bits 5 and 4--Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1. Bit 5 W61 0 Bit 4 W60 0 1 1 0 1 Description Program wait not inserted when external space area 6 is accessed 1 program wait state inserted when external space area 6 is accessed 2 program wait states inserted when external space area 6 is accessed 3 program wait states inserted when external space area 6 is accessed (Initial value) Bits 3 and 2--Area 5 Wait Control 1 and 0 (W51, W50): These bits select the number of program wait states when area 5 in external space is accessed while the AST5 bit in ASTCR is set to 1. Bit 3 W51 0 Bit 2 W50 0 1 1 0 1 Description Program wait not inserted when external space area 5 is accessed 1 program wait state inserted when external space area 5 is accessed 2 program wait states inserted when external space area 5 is accessed 3 program wait states inserted when external space area 5 is accessed (Initial value) Bits 1 and 0--Area 4 Wait Control 1 and 0 (W41, W40): These bits select the number of program wait states when area 4 in external space is accessed while the AST4 bit in ASTCR is set to 1. Bit 1 W41 0 Bit 0 W40 0 1 1 0 1 Description Program wait not inserted when external space area 4 is accessed 1 program wait state inserted when external space area 4 is accessed 2 program wait states inserted when external space area 4 is accessed 3 program wait states inserted when external space area 4 is accessed (Initial value) 127 (2) WCRL Bit : 7 W31 Initial value : R/W : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 W11 1 R/W 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bits 7 and 6--Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1. Bit 7 W31 0 Bit 6 W30 0 1 1 0 1 Description Program wait not inserted when external space area 3 is accessed 1 program wait state inserted when external space area 3 is accessed 2 program wait states inserted when external space area 3 is accessed 3 program wait states inserted when external space area 3 is accessed (Initial value) Bits 5 and 4--Area 2 Wait Control 1 and 0 (W21, W20): These bits select the number of program wait states when area 2 in external space is accessed while the AST2 bit in ASTCR is set to 1. Bit 5 W21 0 Bit 4 W20 0 1 1 0 1 Description Program wait not inserted when external space area 2 is accessed 1 program wait state inserted when external space area 2 is accessed 2 program wait states inserted when external space area 2 is accessed 3 program wait states inserted when external space area 2 is accessed (Initial value) 128 Bits 3 and 2--Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1. Bit 3 W11 0 Bit 2 W10 0 1 1 0 1 Description Program wait not inserted when external space area 1 is accessed 1 program wait state inserted when external space area 1 is accessed 2 program wait states inserted when external space area 1 is accessed 3 program wait states inserted when external space area 1 is accessed (Initial value) Bits 1 and 0--Area 0 Wait Control 1 and 0 (W01, W00): These bits select the number of program wait states when area 0 in external space is accessed while the AST0 bit in ASTCR is set to 1. Bit 1 W01 0 Bit 0 W00 0 1 1 0 1 Description Program wait not inserted when external space area 0 is accessed 1 program wait state inserted when external space area 0 is accessed 2 program wait states inserted when external space area 0 is accessed 3 program wait states inserted when external space area 0 is accessed (Initial value) 129 6.2.4 Bit Bus Control Register H (BCRH) : 7 ICIS1 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 Initial value : R/W : BCRH is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for areas 2 to 5 and area 0. BCRH is initialized to H'D0 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. Bit 7 ICIS1 0 1 Description Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas (Initial value) Bit 6--Idle Cycle Insert 0 (ICIS0): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed. Bit 6 ICIS0 0 1 Description Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles (Initial value) Bit 5--Burst ROM Enable (BRSTRM): Selects whether area 0 is used as a burst ROM interface. In normal mode, the selection can be made from the entire external space. Bit 5 BRSTRM 0 1 Description Area 0 is basic bus interface Area 0 is burst ROM interface (Initial value) 130 Bit 4--Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycles for the burst ROM interface. Bit 4 BRSTS1 0 1 Description Burst cycle comprises 1 state Burst cycle comprises 2 states (Initial value) Bit 3--Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a burst ROM interface burst access. Bit 3 BRSTS0 0 1 Description Max. 4 words in burst access Max. 8 words in burst access (Initial value) Bits 2 to 0--RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as DRAM interface. Bit 2 RMTS2 0 Bit 1 RMTS1 0 Bit 0 RMTS0 0 1 1 0 1 1 -- -- Description Area 5 Normal space Normal space Normal space DRAM space -- DRAM space DRAM space Area 4 Area 3 Area 2 Note: When areas selected in DRAM space are all 8-bit space, the PF 2 pin can be used as an I/O port, BREQO, or WAIT. 131 6.2.5 Bit Bus Control Register L (BCRL) : 7 BRLE 0 R/W 6 BREQOE 0 R/W 5 -- 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W 2 -- 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Initial value : R/W : BCRL is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, the LCAS signal, DMAC single address transfer, enabling or disabling of the write data buffer function, and enabling or disabling of WAIT pin input. BCRL is initialized to H'3C by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Bus Release Enable (BRLE): Enables or disables external bus release. Bit 7 BRLE 0 1 Description External bus release is disabled. BREQ, BACK, and BREQO can be used as I/O ports. (Initial value) External bus release is enabled. Bit 6--BREQO Pin Enable (BREQOE): Outputs a signal that requests the external bus master to drop the bus request signal (BREQ) in the external bus release state, when an internal bus master performs an external space access, or when a refresh request is generated. Bit 6 BREQOE 0 1 Description BREQO output disabled. BREQO can be used as I/O port. BREQO output enabled. (Initial value) Bit 5--Reserved: Only 1 should be written to this bit. Bit 4--LCAS Select (LCASS): Write 0 to this bit when using the DRAM interface. LCAS pin used for 2-CAS type DRAM interface LCAS signal. BREQO output and WAIT input cannot be used when LCAS signal is used. 132 Bit 3--DACK Timing Select (DDS): Selects the DMAC single address transfer bus timing for the DRAM interface. Bit 3 DDS 0 Description When DMAC single address transfer is performed in DRAM space, full access is always executed DACK signal goes low from T r or T1 cycle 1 Burst access is possible when DMAC single address transfer is performed in DRAM space DACK signal goes low from T c1 or T2 cycle (Initial value) Bit 2--Reserved: Only 1 should be written to this bit. Bit 1--Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. Bit 1 WDBE 0 1 Description Write data buffer function not used Write data buffer function used (Initial value) Bit 0--WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin. Bit 0 WAITE 0 1 Description Wait input by WAIT pin disabled. WAIT pin can be used as I/O port. Wait input by WAIT pin enabled (Initial value) 133 6.2.6 Bit Memory Control Register (MCR) : 7 TPC 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W Initial value : R/W : MCR is an 8-bit readable/writable register that selects the DRAM strobe control method, number of precharge cycles, access mode, address multiplexing shift size, and the number of wait states inserted during refreshing, when areas 2 to 5 are designated as DRAM interface. MCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be used when areas 2 to 5 designated as DRAM space are accessed. Bit 7 TPC 0 1 Description 1-state precharge cycle is inserted 2-state precharge cycle is inserted (Initial value) Bit 6--Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space. DRAM space burst access is performed in fast page mode. Bit 6 BE 0 1 Description Burst disabled (always full access) For DRAM space access, access in fast page mode (Initial value) 134 Bit 5--RAS Down Mode (RCDM): When areas 2 to 5 are designated as DRAM space and access to DRAM is interrupted, RCDM selects whether the next DRAM access is waited for with the RAS signal held low (RAS down mode), or the RAS signal is driven high again (RAS up mode). RAS down mode cannot be used with the 2-CAS method. When selecting RAS down mode, set the BE bit to 1. Bit 5 RCDM 0 1 Description DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected (Initial value) Bit 4--2-CAS Method Select (CW2): Write 1 to this bit when areas 2 to 5 are designated as 8-bit DRAM space, and 0 otherwise. Bit 4 CW2 0 1 Description 16-bit DRAM space selected 8-bit DRAM space selected (Initial value) 135 Bits 3 and 2--Multiplex Shift Count 1 and 0 (MXC1, MXC0): These bits select the size of the shift to the lower half of the row address in row address/column address multiplexing for the DRAM interface. In burst operation on the DRAM interface, these bits also select the row address to be used for comparison. Bit 3 MXC1 0 Bit 2 MXC0 0 Description 8-bit shift * * 1 (Initial value) When 8-bit access space is designated: Row address A23 to A 8 used for comparison When 16-bit access space is designated: Row address A23 to A 9 used for comparison 9-bit shift * * When 8-bit access space is designated: Row address A23 to A 9 used for comparison When 16-bit access space is designated: Row address A23 to A 10 used for comparison 1 0 10-bit shift * * When 8-bit access space is designated: Row address A 23 to A 10 used for comparison When 16-bit access space is designated: Row address A23 to A 11 used for comparison 1 -- Bits 1 and 0--Refresh Cycle Wait Control 1 and 0 (RLW1, RLW0): These bits select the number of wait states to be inserted in a DRAM interface CAS-before-RAS refresh cycle. This setting is used for all areas designated as DRAM space. Wait input by the WAIT pin is disabled. Bit 1 RLW1 0 Bit 0 RLW0 0 1 1 0 1 Description No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted (Initial value) 136 6.2.7 Bit DRAM Control Register (DRAMCR) : 7 RFSHE 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. Bit 7--Refresh Control (RFSHE): Selects whether or not refresh control is performed. When refresh control is not performed, the refresh timer can be used as an interval timer. Refresh control is not performed in normal mode. Bit 7 RFSHE 0 1 Description Refresh control is not performed Refresh control is performed (Initial value) Bit 6--RAS-CAS Wait (RCW): Controls wait state insertion in DRAM interface CAS-beforeRAS refreshing. Bit 6 RCW 0 1 Description Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle (Initial value) 137 Bit 5--Refresh Mode (RMODE): When refresh control is performed (RFSHE = 1), this bit selects whether normal refreshing (CAS-before-RAS refreshing for the DRAM interface) or selfrefreshing is performed. Bit 5 RMODE 0 1 Description DRAM interface CAS-before-RAS refreshing used Self-refreshing used (Initial value) Bit 4--Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR. Bit 4 CMF 0 Description [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag (Initial value) [Setting condition] Set when RTCNT = RTCOR 1 Bit 3--Compare Match Interrupt Enable (CMIE): Enables or disables interrupt requests (CMI) by the CMF flag when the CMF flag in DRAMCR is set to 1. When refresh control is performed (RFSHE = 1), the CMIE bit is always cleared to 0. Bit 3 CMIE 0 1 Description Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled (Initial value) 138 Bits 2 to 0--Refresh Counter Clock Select (CKS2 to CKS0): These bits select the clock to be input to RTCNT from among 7 internal clocks obtained by dividing the system clock (o). When the input clock is selected with bits CKS2 to CKS0, RTCNT begins counting up. Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Count operation disabled Count uses o/2 Count uses o/8 Count uses o/32 Count uses o/128 Count uses o/512 Count uses o/2048 Count uses o/4096 (Initial value) 139 6.2.8 Bit Refresh Timer/Counter (RTCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started. Also, if the CMIE bit in DRAMCR is set to 1, a compare match interrupt (CMI) is generated. RTCNT is initialized to H'00 by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 6.2.9 Bit Refresh Time Constant Register (RTCOR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : RTCOR is an 8-bit readable/writable register that sets the period for compare match operations with RTCNT. The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. RTCOR is initialized to H'FF by a power-on reset and in hardware standby mode. It is not initialized by a manual reset or in software standby mode. 140 6.3 6.3.1 Overview of Bus Control Area Partitioning In advanced mode, the bus controller partitions the 16 Mbytes address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. In normal mode, it controls a 64-kbyte address space comprising part of area 0. Figure 6-2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area. H'000000 Area 0 (2Mbytes) H'1FFFFF H'200000 Area 1 (2Mbytes) H'3FFFFF H'400000 Area 2 (2Mbytes) H'5FFFFF H'600000 Area 3 (2Mbytes) H'7FFFFF H'800000 Area 4 (2Mbytes) H'9FFFFF H'A00000 Area 5 (2Mbytes) H'BFFFFF H'C00000 Area 6 (2Mbytes) H'DFFFFF H'E00000 Area 7 (2Mbytes) H'FFFFFF H'0000 H'FFFF (1) Advanced mode (2) Normal mode Figure 6-2 Overview of Area Partitioning 141 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. (1) Bus Width: A bus width of 8 or 16 bits can be selected with ADWCR. An area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. If all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. When the burst ROM interface is designated, 16-bit bus mode is always set. (2) Number of Access States: Two or three access states can be selected with ASTCR. An area for which 2-state access is selected functions as a 2-state access space, and an area for which 3state access is selected functions as a 3-state access space. With the DRAM interface and burst ROM interface, the number of access states may be determined without regard to ASTCR. When 2-state access space is designated, wait insertion is disabled. (3) Number of Program Wait States: When 3-state access space is designated by ASTCR, the number of program wait states to be inserted automatically is selected with WCRH and WCRL. From 0 to 3 program wait states can be selected. Table 6-3 shows the bus specifications for each basic bus interface area. 142 Table 6-3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) Bus Width 16 Program Wait Access States States 2 3 0 0 1 2 3 8 2 3 0 0 1 2 3 ABWCR ABWn 0 ASTCR ASTn 0 1 Wn1 -- 0 Wn0 -- 0 1 1 0 1 1 0 1 -- 0 -- 0 1 1 0 1 6.3.3 Memory Interfaces The H8S/2350 Series memory interfaces comprise a basic bus interface that allows direct connection of ROM, SRAM, and so on; a DRAM interface that allows direct connection of DRAM; and a burst ROM interface that allows direct connection of burst ROM. The interface can be selected independently for each area. An area for which the basic bus interface is designated functions as normal space, an area for which the DRAM interface is designated functions as DRAM space, and an area for which the burst ROM interface is designated functions as burst ROM space. 143 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4, 6.5, and 6.7) should be referred to for further details. Area 0: Area 0 includes on-chip ROM*, and in ROM-disabled expansion mode, all of area 0 is external space. In ROM-enabled expansion mode, the space excluding on-chip ROM* is external space. When area 0 external space is accessed, the CS0 signal can be output. Either basic bus interface or burst ROM interface can be selected for area 0. Note: * Only applies to the H8S/2351. Areas 1 and 6: In external expansion mode, all of areas 1 and 6 is external space. When area 1 and 6 external space is accessed, the CS1 and CS6 pin signals respectively can be output. Only the basic bus interface can be used for areas 1 and 6. Areas 2 to 5: In external expansion mode, all of areas 2 to 5 is external space. When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output. Basic bus interface or DRAM interface can be selected for areas 2 to 5. With the DRAM interface, signals CS2 to CS5 are used as RAS signals. Area 7: Area 7 includes the on-chip RAM and internal I/O registers. In external expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When area 7 external space is accessed, the CS7 signal can be output. Only the basic bus interface can be used for the area 7 memory interface. 144 6.3.5 Areas in Normal Mode In normal mode, a 64-kbyte address space comprising part of area 0 is controlled. Area partitioning is not performed in normal mode. In ROM-disabled expansion mode, the space excluding the on-chip RAM and internal I/O registers is external space. In ROM-enabled expansion mode* the space excluding the on-chip ROM*, on-chip RAM, and internal I/O registers is external space. The on-chip RAM is enabled when the RAME bit in the system control register (SYSCR) is set to 1; when the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding space becomes external space . When external space is accessed, the CS0 signal can be output. The basic bus interface or burst ROM interface can be selected. Note: * Only applies to the H8S/2351. 145 6.3.6 Chip Select Signals The H8S/2350 Series can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. In normal mode, only the CS0 signal can be output. Figure 6-3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin. In ROM-disabled expansion mode, the CS0 pin is placed in the output state after a power-on reset. Pins CS1 to CS7 are placed in the input state after a power-on reset, and so the corresponding DDR should be set to 1 when outputting signals CS1 to CS7. In the H8S/2351's ROM-enabled expansion mode, pins CS0 to CS7 are all placed in the input state after a power-on reset, and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to CS7. For details, see section 9, I/O Ports. When areas 2 to 5 are designated as DRAM space, outputs CS2 to CS5 are used as RAS signals. Bus cycle T1 o T2 T3 Address bus Area n external address CSn Figure 6-3 CSn Signal Output Timing (n = 0 to 7) 146 6.4 6.4.1 Basic Bus Interface Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL (see table 6-3). 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-Bit Access Space: Figure 6-4 illustrates data alignment control for the 8-bit access space. With the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. Upper data bus Lower data bus D15 D8 D7 D0 Byte size 1st bus cycle 2nd bus cycle 1st bus cycle Longword size 2nd bus cycle 3rd bus cycle 4th bus cycle Word size Figure 6-4 Access Sizes and Data Alignment Control (8-Bit Access Space) 147 16-Bit Access Space: Figure 6-5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. The upper data bus is used for an even address, and the lower data bus for an odd address. Upper data bus Lower data bus D15 D8 D7 D0 Byte size Byte size Word size Longword size 1st bus cycle 2nd bus cycle * Even address * Odd address Figure 6-5 Access Sizes and Data Alignment Control (16-Bit Access Space) 148 6.4.3 Valid Strobes Table 6-4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6-4 Area 8-bit access space Data Buses Used and Valid Strobes Access Read/ Size Write Byte Read Write Read Address -- -- Even Odd Write Even Odd Word Read Write -- -- HWR LWR RD Valid Strobe RD HWR RD Valid Invalid Valid Hi-Z Valid Upper Data Bus (D15 to D8) Valid Lower data bus (D7 to D0) Invalid Hi-Z Invalid Valid Hi-Z Valid Valid Valid 16-bit access Byte space HWR, LWR Valid Note: Hi-Z: High impedance Invalid: Input state; input value is ignored. 149 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6-6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6-6 Bus Timing for 8-Bit 2-State Access Space 150 8-Bit 3-State Access Space: Figure 6-7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6-7 Bus Timing for 8-Bit 3-State Access Space 151 16-Bit 2-State Access Space: Figures 6-8 to 6-10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid D7 to D0 High impedance Note: n = 0 to 7 Figure 6-8 Bus Timing for 16-Bit 2-State Access Space (1) (Even Address Byte Access) 152 Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Valid Note: n = 0 to 7 Figure 6-9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) 153 Bus cycle T1 o T2 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6-10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) 154 16-Bit 3-State Access Space: Figures 6-11 to 6-13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR Write D15 to D8 High Valid High impedance D7 to D0 Note: n = 0 to 7 Figure 6-11 Bus Timing for 16-Bit 3-State Access Space (1) (Even Address Byte Access) 155 Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 High impedance D7 to D0 Note: n = 0 to 7 Valid Figure 6-12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) 156 Bus cycle T1 o T2 T3 Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Note: n = 0 to 7 Valid Figure 6-13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) 157 6.4.5 Wait Control When accessing external space, the H8S/2350 Series can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL. Pin Wait Insertion Setting the WAITE bit in BCRL to 1 enables wait insertion by means of the WAIT pin. Program wait insertion is first carried out according to the settings in WCRH and WCRL. Then , if the WAIT pin is low at the falling edge of o in the last T2 or Tw state, a Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. This is useful when inserting four or more Tw states, or when changing the number of Tw states for different external devices. The WAITE bit setting applies to all areas. 158 Figure 6-14 shows an example of wait state insertion timing. By program wait T1 o T2 Tw By WAIT pin Tw Tw T3 WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Write data Note: indicates the timing of WAIT pin sampling. Figure 6-14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. When a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset. 159 6.5 6.5.1 DRAM Interface Overview When the H8S/2350 Series is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the H8S/2350 Series. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.2 Setting DRAM Space Areas 2 to 5 are designated as DRAM space by setting bits RMTS2 to RMTS0 in BCRH. The relation between the settings of bits RMTS2 to RMTS0 and DRAM space is shown in table 6-5. Possible DRAM space settings are: one area (area 2), two areas (areas 2 and 3), and four areas (areas 2 to 5). Table 6-5 RMTS2 0 Settings of Bits RMTS2 to RMTS0 and Corresponding DRAM Spaces RMTS1 0 1 RMTS0 1 0 1 Area 5 Normal space Normal space DRAM space DRAM space Area 4 Area 3 Area 2 DRAM space 6.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6-6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6-6 Address Multiplexing Settings by Bits MXC1 and MXC0 MCR 0 1 0 1 Column -- address -- Address Pins A23 to A 13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 to A 13 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A23 to A 13 A12 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A23 to A 13 A12 A11 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 -------------------------- Shift MXC1 MXC0 Size Row 0 address 1 8 bits 9 bits 10 bits Setting -- prohibited -- A23 to A 13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 160 6.5.4 Data Bus If the bit in ABWCR corresponding to an area designated as DRAM space is set to 1, that area is designated as 8-bit DRAM space; if the bit is cleared to 0, the area is designated as 16-bit DRAM space. In 16-bit DRAM space, x 16-bit configuration DRAM can be connected directly. In 8-bit DRAM space the upper half of the data bus, D15 to D8, is enabled, while in 16-bit DRAM space both the upper and lower halves of the data bus, D15 to D0, are enabled. Access sizes and data alignment are the same as for the basic bus interface: see section 6.4.2, Data Size and Data Alignment. 6.5.5 Pins Used for DRAM Interface Table 6-7 shows the pins used for DRAM interfacing and their functions. Table 6-7 DRAM Interface Pins With DRAM Setting WE Pin HWR Name Write enable I/O Function Output When 2-CAS system is set, write enable for DRAM space access. LCAS CS2 LCAS RAS2 Lower column address strobe Output Lower column address strobe for 16-bit DRAM space access Row address strobe 2 Output Row address strobe when area 2 is designated as DRAM space. Output Row address strobe when area 3 is designated as DRAM space. Output Row address strobe when area 4 is designated as DRAM space. Output Row address strobe when area 5 is designated as DRAM space. CS3 RAS3 Row address strobe 3 CS4 RAS4 Row address strobe 4 CS5 RAS5 Row address strobe 5 CAS WAIT A12 to A 0 D15 to D0 UCAS WAIT A12 to A 0 D15 to D0 Upper column address strobe Output Upper column address strobe for DRAM space access Wait Address pins Data pins Input Wait request signal Output Row address/column address multiplexed output I/O Data input/output pins 161 6.5.6 Basic Timing Figure 6-15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle. The 4 states of the basic timing consist of one T p (precharge cycle) state, one Tr (row address output cycle), and two Tc (column address output cycle) states, Tc1 and T c2 . Tp Tr Tc1 Tc2 o A23 to A0 row column CSn (RAS) CAS, LCAS HWR, LWR (UWE, LWE) Read D15 to D0 Write HWR, LWR (UWE, LWE) D15 to D0 Note: n = 2 to 5 Figure 6-15 Basic Access Timing (2-WE System) 162 6.5.7 Precharge State Control When DRAM is accessed, RAS precharging time must be secured. With the H8S/2350 Series, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of T p cycles according to the DRAM connected and the operating frequency of the H8S/2350 Series. Figure 6-16 shows the timing when two Tp states are inserted. When the TCP bit is set to 1, two T p states are also used for refresh cycles. Tp1 Tp2 Tr Tc1 Tc2 o A23 to A0 row column CSn (RAS) CAS, LCAS HWR, LWR (UWE, LWE) Read D15 to D0 HWR, LWR (UWE, LWE) Write D15 to D0 Note: n = 2 to 5 Figure 6-16 Timing with Two Precharge States (2-WE System) 163 6.5.8 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL. Pin Wait Insertion When the WAITE bit in BCRH is set to 1, wait input by means of the WAIT pin is enabled regardless of the setting of the AST bit in ASTCR. When DRAM space is accessed in this state, a program wait is first inserted. If the WAIT pin is low at the falling edge of o in the last Tc1 or Tw state, another Tw state is inserted. If the WAIT pin is held low, Tw states are inserted until it goes high. Figure 6-17 shows an example of wait state insertion timing. 164 By program wait Tp o Tr Tc1 Tw By WAIT pin Tw Tc2 WAIT Address bus CSn (RAS) CAS Read Data bus Read data CAS Write Data bus Write data Notes: indicates the timing of WAIT pin sampling. n = 2 to 5 Figure 6-17 Example of Wait State Insertion Timing (CW2 = 1, 8-Bit Area Setting for Entire Space) 165 6.5.9 Byte Access Control When DRAM with a x16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. When the CW2 bit is cleared to 0 in MCR, the 2-CAS system is selected. Figure 6-18 shows the control timing in the 2-CAS system, and figure 6-19 shows an example 2-CAS system DRAM connection. When only DRAM with a x8 configuration is connected, set the CW2 bit to 1 in MCR. Tp Tr Tc1 Tc2 o A23 to A0 Row Column CSn (RAS) CAS Byte control LCAS HWR (WE) Note: n = 2 to 5 Figure 6-18 2-CAS System Control Timing (Upper Byte Write Access) 166 H8S/2350 (Address shift size set to 9 bits) CS (RAS) CAS LCAS HWR (WE) A9 A8 A7 A6 A5 A4 A3 A2 A1 D15 to D0 2-CAS type 4-Mbit DRAM 256-kbyte x 16-bit configuration 9-bit column address RAS UCAS LCAS WE A8 A7 A6 A5 A4 A3 A2 A1 A0 D15 to D0 OE Low address input: A8 to A0 Column address input: A8 to A0 Figure 6-19 Example of 2-CAS System Connection 167 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1. (1) Burst Access (Fast Page Mode) Operation Timing Figure 6-20 shows the operation timing for burst access. When there are consecutive access cycles for DRAM space, the CAS signal and column address output cycles (two states) continue as long as the row address is the same for consecutive access cycles. The row address used for the comparison is set with bits MXC1 and MXC0 in MCR. Tp o A23 to A0 CSn (RAS) CAS, LCAS HWR (WE) Read D15 to D0 HWR (WE) Write D15 to D0 Note: n = 2 to 5 Tr Tc1 Tc2 Tc1 Tc2 row column1 column2 Figure 6-20 Operation Timing in Fast Page Mode (2-WE System) The bus cycle can also be extended in burst access by inserting wait states. The wait state insertion method and timing are the same as for full access. For details, see section 6.5.8, Wait Control. 168 (2) RAS Down Mode and RAS Up Mode Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. * RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1. If access to DRAM space is interrupted and another space is accessed, the RAS signal is held low during the access to the other space, and burst access is performed if the row address of the next DRAM space access is the same as the row address of the previous DRAM space access. Figure 6-21 shows an example of the timing in RAS down mode. Note, however, that the RAS signal will go high if a refresh operation interrupts RAS down mode. External space access T1 T2 DRAM access Tp o Tr Tc1 Tc2 DRAM access Tc1 Tc2 A23 to A0 CSn (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 6-21 Example of Operation Timing in RAS Down Mode 169 * RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6-22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level. External space access T1 T2 DRAM access Tp o Tr Tc1 Tc2 DRAM access Tc1 Tc2 A23 to A0 CSn (RAS) CAS, LCAS D15 to D0 Note: n = 2 to 5 Figure 6-22 Example of Operation Timing in RAS Up Mode 170 6.5.11 Refresh Control The H8S/2350 Series is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. (1) CAS-before-RAS (CBR) Refreshing To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0. With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in DRAMCR, and when the count matches the value set in RTCOR (compare match), refresh control is performed. At the same time, RTCNT is reset and starts counting again from H'00. Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. Set a value in RTCOR and bits CKS2 to CKS0 that will meet the refreshing interval specification for the DRAM used. When bits CKS2 to CKS0 are set, RTCNT starts counting up. RTCNT and RTCOR settings should therefore be completed before setting bits CKS2 to CKS0. Do not clear the CMF flag when refresh control is being performed (RFSHE = 1). RTCNT operation is shown in figure 6-23, compare match timing in figure 6-24, and CBR refresh timings in figure 6-25. RTCNT RTCOR H'00 Refresh request Figure 6-23 RTCNT Operation 171 o RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6-24 Compare Match Timing TRp TRr TRc1 TRc2 o CS (RAS) CAS, LCAS Figure 6-25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh operations. Figure 6-26 shows the timing when the RCW bit is set to 1. 172 TRp TRr TRc1 TRw TRc2 o CSn (RAS) CAS, LCAS Figure 6-26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1) (2) Self-Refreshing A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1. Then, when a SLEEP instruction is executed to enter software standby mode, the CAS and RAS signals are output and DRAM enters self-refresh mode, as shown in figure 6-27. When software standby mode is exited, the RMODE bit is cleared to 0 and self-refresh mode is cleared. When switching to software standby mode, if there is a CBR refresh request, CBR refreshing is executed before self-refresh mode is entered. Software standby TRp o TRcr TRc3 CSn (RAS) CAS, LCAS HWR (WE) High Note: n = 2 to 5 Figure 6-27 Self-Refresh Timing (When CW2 = 1, or CW2 = 0 and LCASS = 0) 173 6.6 DMAC Single Address Mode and DRAM Interface When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, whether or not burst access is to be performed is selected. 6.6.1 When DDS = 1 Burst access is performed by determining the address only, irrespective of the bus master. The DACK output goes low from the TC1 state in the case of the DRAM interface. Figure 6-28 shows the DACK output timing for the DRAM interface when DDS = 1. Tp o A23 to A0 CSn (RAS) CAS, (UCAS) LCAS (LCAS) HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 DACK Row Column Tr Tc1 Tc2 Figure 6-28 DACK Output Timing when DDS = 1 (Example of DRAM Access) 174 6.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6-29 shows the DACK output timing for the DRAM interface when DDS = 0. Tp o A23 to A0 CSn (RAS) CAS, (UCAS) LCAS (LCAS) HWR, (WE) Read D15 to D0 HWR, (WE) Write D15 to D0 DACK Row Column Tr Tc1 Tc2 Figure 6-29 DACK Output Timing when DDS = 0 (Example of DRAM Access) 175 6.7 6.7.1 Burst ROM Interface Overview With the H8S/2350 Series, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only. One or two states can be selected for burst access. 6.7.2 Basic Timing The number of states in the initial cycle (full access) of the burst ROM interface is in accordance with the setting of the AST0 bit in ASTCR. Also, when the AST0 bit is set to 1, wait state insertion is possible. One or two states can be selected for the burst cycle, according to the setting of the BRSTS1 bit in BCRH. Wait states cannot be inserted. When area 0 is designated as burst ROM space, it becomes 16-bit access space regardless of the setting of the ABW0 bit in ABWCR. When the BRSTS0 bit in BCRH is cleared to 0, burst access of up to 4 words is performed; when the BRSTS0 bit is set to 1, burst access of up to 8 words is performed. The basic access timing for burst ROM space is shown in figures 6-30 (a) and (b). The timing shown in figure 6-30 (a) is for the case where the AST0 and BRSTS1 bits are both set to 1, and that in figure 6-30 (b) is for the case where both these bits are cleared to 0. 176 Full access T1 o T2 T3 T1 Burst access T2 T1 T2 Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6-30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) 177 Full access T1 T2 Burst access T1 T1 o Address bus Only lower address changed CS0 AS RD Data bus Read data Read data Read data Figure 6-30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control. Wait states cannot be inserted in a burst cycle. 178 6.8 6.8.1 Idle Cycle Operation When the H8S/2350 Series accesses external space , it can insert a 1-state idle cycle (T I) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and high-speed memory, I/O interfaces, and so on. (1) Consecutive Reads between Different Areas If consecutive reads between different areas occur while the ICIS1 bit in BCRH is set to 1, an idle cycle is inserted at the start of the second read cycle. This is enabled in advanced mode. Figure 6-31 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a read cycle from SRAM, each being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus CS (area A) CS (area B) RD Data bus T2 T3 Bus cycle B T1 T2 o Address bus CS (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 , CS (area B) RD Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) Long output floating time (a) Idle cycle not inserted (ICIS1 = 0) Figure 6-31 Example of Idle Cycle Operation (1) 179 (2) Write after Read If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6-32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented. Bus cycle A T1 o Address bus CS (area A) CS (area B) RD HWR Data bus T2 T3 Bus cycle B T1 T2 o Address bus CS (area A) Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Long output floating time , CS (area B) RD HWR Data bus Data collision (b) Idle cycle inserted (Initial value ICIS1 = 1) (a) Idle cycle not inserted (ICIS1 = 0) Figure 6-32 Example of Idle Cycle Operation (2) 180 (3) Relationship between Chip Select (CS) Signal and Read (RD) Signal Depending on the system's load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6-33. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the initial state after reset release, idle cycle insertion (b) is set. Bus cycle A T1 o Address bus CS (area A) CS (area B) RD T2 T3 Bus cycle B T1 T2 o Address bus CS (area A) CS (area B) RD Bus cycle A T1 T2 T3 Bus cycle B TI T1 T2 Possibility of overlap between CS (area B) and RD (a) Idle cycle not inserted (ICIS1 = 0) (b) Idle cycle inserted (Initial value ICIS1 = 1) Figure 6-33 Relationship between Chip Select (CS) and Read (RD) (4) Usage Notes When DRAM space is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access, only a Tp cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6-34. However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this case is shown in figures 6-35 (a) and (b). 181 External read T1 o Address bus RD Data bus T2 T3 Tp DRAM space read Tr Tc1 Tc2 Figure 6-34 Example of DRAM Access after External Read DRAM space read Tp EXTAL Address RD RAS CAS, LCAS Data bus Tr Tc1 Tc2 T1 External read T1 T2 T3 DRAM space read Tc1 Tc1 Tc2 Idle cycle Figure 6-35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) 182 DRAM space read Tp EXTAL Address RD HWR RAS CAS, LCAS Data bus Tr Tc1 Tc2 T1 External read T1 T2 T3 DRAM space write Tc1 Tc1 Tc2 Idle cycle Figure 6-35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) 6.8.2 Pin States in Idle Cycle Table 6-8 shows pin states in an idle cycle. Table 6-8 Pins A23 to A 0 D15 to D0 CSn CAS AS RD HWR LWR DACKn Pin States in Idle Cycle Pin State Contents of next bus cycle High impedance High* High High High High High High Note: * Remains low in DRAM space RAS down mode or a refresh cycle. 183 6.9 Write Data Buffer Function The H8S/2350 Series has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6-36 shows an example of the timing when the write data buffer function is used. When this function is used, if an external write or DMA single address mode transfer continues for 2 states or longer, and there is an internal access next, only an external write is executed in the first state, but from the next state onward an internal access (on-chip memory or internal I/O register read/write) is executed in parallel with the external write rather than waiting until it ends. On-chip memory read Internal I/O register read External write cycle T1 T2 TW TW T3 Internal address bus Internal memory Internal read signal Internal I/O register address A23 to A0 External address External space write CSn HWR, LWR D15 to D0 Figure 6-36 Example of Timing when Write Data Buffer Function is Used 184 6.10 6.10.1 Bus Release Overview The H8S/2350 Series can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request is generated, it can issue a bus request off-chip. 6.10.2 Operation In external expansion mode, the bus can be released to an external device by setting the BRLE bit in BCRL to 1. Driving the BREQ pin low issues an external bus request to the H8S/2350 Series. When the BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus, data bus, and bus control signals are placed in the high-impedance state, establishing the external bus-released state. In the external bus released state, an internal bus master can perform accesses using the internal bus. When an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. Even if a refresh request is generated in the external bus released state, refresh control is deferred until the external bus master drops the bus request. If the BREQOE bit in BCRL is set to 1, when an internal bus master wants to make an external access in the external bus released state, or when a refresh request is generated, the BREQO pin is driven low and a request can be made off-chip to drop the bus request. When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the external bus released state is terminated. If an external bus release request and external access occur simultaneously, the order of priority is as follows: (High) External bus release > Internal bus master external access (Low) If a refresh request and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh > External bus release (Low) As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. 185 6.10.3 Pin States in External Bus Released State Table 6-9 shows pin states in the external bus released state. Table 6-9 Pins A23 to A 0 D15 to D0 CSn CAS AS RD HWR LWR DACKn Pin States in Bus Released State Pin State High impedance High impedance High impedance High impedance High impedance High impedance High impedance High impedance High 186 6.10.4 Transition Timing Figure 6-37 shows the timing for transition to the bus-released state. CPU cycle CPU cycle T0 o T1 T2 External bus released state High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK Minimum 1 state [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] Low level of BREQ pin is sampled at rise of T2 state. BACK pin is driven low at end of CPU read cycle, releasing bus to external bus master. BREQ pin state is still sampled in external bus released state. High level of BREQ pin is sampled. BACK pin is driven high, ending bus release cycle. Figure 6-37 Bus-Released State Transition Timing 187 6.10.5 Usage Note When MSTPCR is set to H'FFFF or H'EFFF and a transition is made to sleep mode, the external bus release function halts. Therefore, MSTPCR should not be set to H'FFFF or H'EFFF if the external bus release function is to be used in sleep mode. 6.11 6.11.1 Bus Arbitration Overview The H8S/2350 Series has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC, which perform read/write operations when they have possession of the bus. Each bus master requests the bus by means of a bus request signal. The bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. The selected bus master then takes possession of the bus and begins its operation. 6.11.2 Operation The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. If there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. The order of priority of the bus masters is as follows: (High) DMAC > DTC > CPU (Low) An internal bus access by an internal bus master, external bus release, and refreshing, can be executed in parallel. In the event of simultaneous external bus release request, refresh request, and internal bus master external access request generation, the order of priority is as follows: (High) Refresh > External bus release (Low) (High) External bus release > Internal bus master external access (Low) As a refresh and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. 188 6.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. There are specific times at which each bus master can relinquish the bus. CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC or DMAC, the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of the bus is as follows: * The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. See Appendix A-5, Bus States During Instruction Execution, for timings at which the bus is not transferred. * If the CPU is in sleep mode, it transfers the bus immediately. DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated. The DTC can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). It does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is generated. In the case of an external request in short address mode or normal mode, and in cycle steal mode, the DMAC releases the bus after a single transfer. In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after completion of a transfer. 6.11.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The RD signal, DRAM interface RAS and CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change from the low level to the high-impedance state. 189 6.12 Resets and the Bus Controller In a power-on reset, the H8S/2350, including the bus controller, enters the reset state at that point, and an executing bus cycle is discontinued. In a manual reset, the bus controller's registers and internal state are maintained, and an executing external bus cycle is completed. In this case, WAIT input is ignored. Also, since the DMAC is initialized by a manual reset, DACK and TEND output is disabled and these pins become I/O ports controlled by DDR and DR. 190 Section 7 DMA Controller 7.1 Overview The H8S/2350 Series has a built-in DMA controller (DMAC) which can carry out data transfer on up to 4 channels. 7.1.1 Features The features of the DMAC are listed below. * Choice of short address mode or full address mode Short address mode Maximum of 4 channels can be used Choice of dual address mode or single address mode In dual address mode, one of the two addresses, transfer source and transfer destination, is specified as 24 bits and the other as16 bits In single address mode, transfer source or transfer destination address only is specified as 24 bits In single address mode, transfer can be performed in one bus cycle Choice of sequential mode, idle mode, or repeat mode for dual address mode and single address mode Full address mode Maximum of 2 channels can be used Transfer source and transfer destination address specified as 24 bits Choice of normal mode or block transfer mode * 16-Mbyte address space can be specified directly * Byte or word can be set as the transfer unit * Activation sources: internal interrupt, external request, auto-request (depending on transfer mode) Six 16-bit timer-pulse unit (TPU) compare match/input capture interrupts Serial communication interface (SCI0, SCI1) transmission complete interrupt, reception complete interrupt A/D converter conversion end interrupt External request Auto-request 191 * Module stop mode can be set The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7-1. Internal address bus Internal interrupts TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A TXI0 RXI0 TXI1 RXI1 ADI External pins DREQ0 DREQ1 TEND0 TEND1 DACK0 DACK1 Interrupt signals DEND0A DEND0B DEND1A DEND1B Address buffer Processor Channel 1B Channel 1A Channel 0B Channel 0A MAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B Module data bus IOAR0A Control logic DMAWER DMATCR DMACR0A DMACR0B DMACR1A DMACR1B DMABCR Data buffer Channel 1 Internal data bus Legend DMAWER DMATCR DMABCR DMACR MAR IOAR ETCR : DMA write enable register : DMA terminal control register : DMA band control register (for all channels) : DMA control register : Memory address register : I/O address register : Executive transfer counter register Figure 7-1 Block Diagram of DMAC 192 Channel 0 7.1.3 Overview of Functions Tables 7-1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7-1 (1) Overview of DMAC Functions (Short Address Mode) Address Register Bit Length Transfer Mode Dual address mode * Sequential mode 1-byte or 1-word transfer executed for one transfer request * Memory address incremented/decremented by 1 or 2 1 to 65536 transfers * Idle mode 1-byte or 1-word transfer executed for one transfer request * Memory address fixed 1 to 65536 transfers * Repeat mode 1-byte or 1-word transfer executed for one transfer request Memory address incremented/ decremented by 1 or 2 After specified number of transfers (1 to 256), initial state is restored and operation continues Single address mode * * * 1-byte or 1-word transfer executed for one transfer request Transfer in 1 bus cycle using DACK pin in place of address specifying I/O Specifiable for sequential, idle, and repeat modes * External request 24/DACK DACK/24 * * Transfer Source * Source Destination 16/24 24/16 TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt A/D converter conversion end interrupt External request 193 Table 7-1 (2) Overview of DMAC Functions (Full Address Mode) Address Register Bit Length Transfer Mode Normal mode * Auto-request Transfer request retained internally Transfers continue for the specified number of times (1 to 65536) Choice of burst or cycle steal transfer * External request 1-byte or 1-word transfer executed for one transfer request 1 to 65536 transfers Block transfer mode * * * * Specified block size transfer executed for one transfer request 1 to 65536 transfers Either source or destination specifiable as block area Block size: 1 to 256 bytes or words Transfer Source * Source 24 Destination 24 Auto-request * External request * 24 TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt External request A/D converter conversion end interrupt 24 * * * * 194 7.1.4 Pin Configuration Table 7-2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output. With regard to the DACK pins, setting single address transfer automatically sets the corresponding port to output, functioning as a DACK pin. With regard to the TEND pins, whether or not the corresponding port is used as a TEND pin can be specified by means of a register setting. Table 7-2 Channel 0 DMAC Pins Pin Name DMA request 0 DMA transfer acknowledge 0 DMA transfer end 0 Symbol DREQ0 DACK0 TEND0 DREQ1 DACK1 TEND1 I/O Input Output Output Input Output Output Function DMAC channel 0 external request DMAC channel 0 single address transfer acknowledge DMAC channel 0 transfer end DMAC channel 1 external request DMAC channel 1 single address transfer acknowledge DMAC channel 1 transfer end 1 DMA request 1 DMA transfer acknowledge 1 DMA transfer end 1 195 7.1.5 Register Configuration Table 7-3 summarizes the DMAC registers. Table 7-3 DMAC Registers Abbreviation R/W MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Initial Value Address* Bus Width 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits 8 bits 16 bits 16 bits 16 bits 16 bits 16 bits 8 bits Channel Name 0 Memory address register 0A I/O address register 0A Transfer count register 0A Memory address register 0B I/O address register 0B Transfer count register 0B 1 Memory address register 1A I/O address register 1A Transfer count register 1A Memory address register 1B I/O address register 1B Transfer count register 1B 0, 1 DMA write enable register Undefined H'FEE0 Undefined H'FEE4 Undefined H'FEE6 Undefined H'FEE8 Undefined H'FEEC Undefined H'FEEE Undefined H'FEF0 Undefined H'FEF4 Undefined H'FEF6 Undefined H'FEF8 Undefined H'FEFC Undefined H'FEFE H'00 H'00 H'00 H'00 H'00 H'00 H'0000 H'3FFF H'FF00 H'FF01 H'FF02 H'FF03 H'FF04 H'FF05 H'FF06 H'FF3C DMA terminal control register DMATCR DMA control register 0A DMA control register 0B DMA control register 1A DMA control register 1B DMA band control register Module stop control register Note: * Lower 16 bits of the address. DMACR0A DMACR0B DMACR1A DMACR1B DMABCR MSTPCR 196 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7-4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7-4 Short Address Mode and Full Address Mode (For 1 Channel: Example of Channel 0) FAE0 0 Description Short address mode specified (channels A and B operate independently) Channel 0A MAR0A IOAR0A ETCR0A DMACR0A MAR0B IOAR0B ETCR0B DMACR0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. Channel 0B Specifies transfer source/transfer destination address Specifies transfer destination/transfer source address Specifies number of transfers Specifies transfer size, mode, activation source, etc. 1 Full address mode specified (channels A and B operate in combination) MAR0A MAR0B Channel 0 IOAR0A IOAR0B ETCR0A ETCR0B DMACR0A DMACR0B Specifies transfer source address Specifies transfer destination address Not used Not used Specifies number of transfers Specifies number of transfers (used in block transfer mode only) Specifies transfer size, mode, activation source, etc. 197 7.2.1 Bit MAR R/W Bit MAR R/W Memory Address Registers (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 -- 0 -- 15 30 -- 0 -- 14 29 -- 0 -- 13 28 -- 0 -- 12 27 -- 0 -- 11 26 -- 0 -- 10 25 -- 0 -- 9 24 -- 0 * * * * * * * * -- R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register that specifies the transfer source address or destination address. The upper 8 bits of MAR are reserved: they are always read as 0, and cannot be modified. Whether MAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. MAR is incremented or decremented each time a byte or word transfer is executed, so that the address specified by MAR is constantly updated. For details, see section 7.2.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 198 7.2.2 Bit IOAR R/W I/O Address Register (IOAR) : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address. The upper 8 bits of the transfer address are automatically set to H'FF. Whether IOAR functions as the source address register or as the destination address register can be selected by means of the DTDIR bit in DMACR. IOAR is invalid in single address mode. IOAR is not incremented or decremented each time a transfer is executed, so that the address specified by IOAR is fixed. IOAR is not initialized by a reset or in standby mode. 7.2.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The setting of this register is different for sequential mode and idle mode on the one hand, and for repeat mode on the other. (1) Sequential Mode and Idle Mode Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends. 199 (2) Repeat Mode Transfer Number Storage Bit ETCRH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8 Initial value : Transfer Counter Bit ETCRL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 7 6 5 4 3 2 1 0 Initial value : *: Undefined In repeat mode, ETCR functions as transfer counter ETCRL (with a count range of 1 to 256) and transfer number storage register ETCRH. ETCRL is decremented by 1 each time a transfer is performed, and when the count reaches H'00, ETCRL is loaded with the value in ETCRH. At this point, MAR is automatically restored to the value it had when the count was started. The DTE bit in DMABCR is not cleared, and so transfers can be performed repeatedly until the DTE bit is cleared by the user. ETCR is not initialized by a reset or in standby mode. 7.2.4 Bit DMACR R/W DMA Control Register (DMACR) : : : 7 DTSZ 0 R/W 6 DTID5 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. 200 Bit 7--Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 7 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 6--Data Transfer Increment/Decrement (DTID): Selects incrementing or decrementing of MAR every data transfer in sequential mode or repeat mode. In idle mode, MAR is neither incremented nor decremented. Bit 6 DTID 0 Description MAR is incremented after a data transfer * * 1 When DTSZ = 0, MAR is incremented by 1 after a transfer When DTSZ = 1, MAR is incremented by 2 after a transfer (Initial value) MAR is decremented after a data transfer * * When DTSZ = 0, MAR is decremented by 1 after a transfer When DTSZ = 1, MAR is decremented by 2 after a transfer Bit 5--Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed. Bit 5 RPE 0 DMABCR DTIE 0 1 1 0 1 Description Transfer in sequential mode (no transfer end interrupt) Transfer in sequential mode (with transfer end interrupt) Transfer in repeat mode (no transfer end interrupt) Transfer in idle mode (with transfer end interrupt) (Initial value) For details of operation in sequential, idle, and repeat mode, see section 7.5.2, Sequential Mode, section 7.5.3, Idle Mode, and section 7.5.4, Repeat Mode. 201 Bit 4--Data Transfer Direction (DTDIR): Used in combination with the SAE bit in DMABCR to specify the data transfer direction (source or destination). The function of this bit is therefore different in dual address mode and single address mode. DMABCR SAE 0 Bit 4 DTDIR 0 1 1 0 1 Description Transfer with MAR as source address and IOAR as destination address (Initial value) Transfer with IOAR as source address and MAR as destination address Transfer with MAR as source address and DACK pin as write strobe Transfer with DACK pin as read strobe and MAR as destination address 202 Bits 3 to 0--Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B. Channel A Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description -- (Initial value) Activated by A/D converter conversion end interrupt -- -- Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt -- -- 203 Channel B Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description -- (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt -- -- Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. 204 7.2.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W 11 0 R/W 10 0 R/W 9 0 R/W 8 DTA0A 0 R/W DMABCRH : Initial value : R/W : DTA1B DATA1A DTA0B Bit : 7 DTE1B 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DMABCRL : Initial value : R/W : DTIE1B DTIE1A DTIE0B DTIE0A DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15--Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In short address mode, channels 1A and 1B are used as independent channels. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14--Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B are used as independent channels. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) 205 Bit 13--Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode. Bit 13 SAE1 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) This bit is invalid in full address mode. Bit 12--Single Address Enable 0 (SAE0): Specifies whether channel 0B is to be used for transfer in dual address mode or single address mode. Bit 12 SAE0 0 1 Description Transfer in dual address mode Transfer in single address mode (Initial value) This bit is invalid in full address mode. Bits 11 to 8--Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. 206 Bit 11--Data Transfer Acknowledge 1B (DTA1B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1B data transfer factor setting. Bit 11 DTA1B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 10--Data Transfer Acknowledge 1A (DTA1A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1A data transfer factor setting. Bit 10 DTA1A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9--Data Transfer Acknowledge 0B (DTA0B): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0B data transfer factor setting. Bit 9 DTA0B 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 8--Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting. Bit 8 DTA0A 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled 207 Bits 7 to 4--Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. The conditions for the DTE bit being cleared to 0 are as follows: * When initialization is performed * When the specified number of transfers have been completed in a transfer mode other than repeat mode * When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: * When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 7--Data Transfer Enable 1B (DTE1B): Enables or disables data transfer on channel 1B. Bit 7 DTE1B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 6--Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) 208 Bit 5--Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B. Bit 5 DTE0B 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 4--Data Transfer Enable 0A (DTE0A): Enables or disables data transfer on channel 0A. Bit 4 DTE0A 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 to 0--Data Transfer End Interrupt Enable (DTIE): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIE bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 3--Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1B transfer end interrupt. Bit 3 DTIE1B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 2--Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) 209 Bit 1--Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt. Bit 1 DTIE0B 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0--Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0A transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) 210 7.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7-4. 7.3.1 Bit MAR R/W Bit MAR R/W Memory Address Register (MAR) : : : : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 31 -- 0 -- 15 30 -- 0 -- 14 29 -- 0 -- 13 28 -- 0 -- 12 27 -- 0 -- 11 26 -- 0 -- 10 25 -- 0 -- 9 24 -- 0 * * * * * * * * -- R/W R/W R/W R/W R/W R/W R/W R/W 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 Initial value : Initial value : MAR is a 32-bit readable/writable register; MARA functions as the transfer source address register, and MARB as the destination address register. MAR is composed of two 16-bit registers, MARH and MARL. The upper 8 bits of MARH are reserved: they are always read as 0, and cannot be modified. MAR is incremented or decremented each time a byte or word transfer is executed, so that the source or destination memory address can be updated automatically. For details, see section 7.3.4, DMA Control Register (DMACR). MAR is not initialized by a reset or in standby mode. 7.3.2 I/O Address Register (IOAR) IOAR is not used in full address transfer. 211 7.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode. (1) Normal Mode ETCRA Transfer Counter Bit ETCR R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In normal mode, ETCRA functions as a 16-bit transfer counter. ETCRA is decremented by 1 each time a transfer is performed, and transfer ends when the count reaches H'0000. ETCRB is not used at this time. ETCRB ETCRB is not used in normal mode. (2) Block Transfer Mode ETCRA Holds block size Bit ETCRAH R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 15 14 13 12 11 10 9 8 Initial value : Block size counter Bit ETCRAL R/W : : * R/W * R/W * R/W * R/W * R/W * R/W * R/W * R/W : 7 6 5 4 3 2 1 0 Initial value : *: Undefined 212 ETCRB Block Transfer Counter Bit ETCRB R/W : : * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : In block transfer mode, ETCRAL functions as an 8-bit block size counter and ETCRAH holds the block size. ETCRAL is decremented each time a 1-byte or 1-word transfer is performed, and when the count reaches H'00, ETCRAL is loaded with the value in ETCRAH. So by setting the block size in ETCRAH and ETCRAL, it is possible to repeatedly transfer blocks consisting of any desired number of bytes or words. ETCRB functions in block transfer mode, as a 16-bit block transfer counter. ETCRB is decremented by 1 each time a block is transferred, and transfer ends when the count reaches H'0000. 7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in standby mode. DMACRA Bit DMACRA R/W : : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W 11 BLKE 0 R/W 10 -- 0 R/W 9 -- 0 R/W 8 -- 0 R/W Initial value : DMACRB Bit DMACRB R/W : : : 7 -- 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 -- 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : 213 Bit 15--Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time. Bit 15 DTSZ 0 1 Description Byte-size transfer Word-size transfer (Initial value) Bit 14--Source Address Increment/Decrement (SAID) Bit 13--Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 14 SAID 0 Bit 13 SAIDE 0 1 Description MARA is fixed MARA is incremented after a data transfer * * 1 0 1 When DTSZ = 0, MARA is incremented by 1 after a transfer When DTSZ = 1, MARA is incremented by 2 after a transfer (Initial value) MARA is fixed MARA is decremented after a data transfer * * When DTSZ = 0, MARA is decremented by 1 after a transfer When DTSZ = 1, MARA is decremented by 2 after a transfer Bit 12--Block Direction (BLKDIR) Bit 11--Block Enable (BLKE): These bits specify whether normal mode or block transfer mode is to be used. If block transfer mode is specified, the BLKDIR bit specifies whether the source side or the destination side is to be the block area. Bit 12 BLKDIR 0 Bit 11 BLKE 0 1 1 0 1 Description Transfer in normal mode (Initial value) Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area For operation in normal mode and block transfer mode, see section 7.5, Operation. 214 Bits 10 to 7--Reserved: Can be read or written to. Bit 6--Destination Address Increment/Decrement (DAID) Bit 5--Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed. Bit 6 DAID 0 Bit 5 DAIDE 0 1 Description MARB is fixed MARB is incremented after a data transfer * * 1 0 1 When DTSZ = 0, MARB is incremented by 1 after a transfer When DTSZ = 1, MARB is incremented by 2 after a transfer (Initial value) MARB is fixed MARB is decremented after a data transfer * * When DTSZ = 0, MARB is decremented by 1 after a transfer When DTSZ = 1, MARB is decremented by 2 after a transfer Bit 4--Reserved: Can be read or written to. Bits 3 to 0--Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). The factors that can be specified differ between normal mode and block transfer mode. * Normal Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 1 * 0 1 1 * * * Description -- -- Activated by DREQ pin falling edge input Activated by DREQ pin low-level input -- Auto-request (cycle steal) Auto-request (burst) -- *: Don't care (Initial value) 215 * Block Transfer Mode Bit 3 DTF3 0 Bit 2 DTF2 0 Bit 1 DTF1 0 Bit 0 DTF0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Description -- (Initial value) Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt -- -- Note: * Detected as a low level in the first transfer after transfer is enabled. The same factor can be selected for more than one channel. In this case, activation starts with the highest-priority channel according to the relative channel priorities. For relative channel priorities, see section 7.5.13, DMAC Multi-Channel Operation. 216 7.3.5 Bit DMA Band Control Register (DMABCR) : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 -- 0 R/W 12 -- 0 R/W 11 DTA1 0 R/W 10 -- 0 R/W 9 DTA0 0 R/W 8 -- 0 R/W DMABCRH : Initial value : R/W : Bit : 7 DTME1 0 R/W 6 DTE1 0 R/W 5 DTME0 0 R/W 4 DTE0 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DMABCRL : Initial value : R/W : DTIE1B DTIE1A DTIE0B DTIE0A DMABCR is a 16-bit readable/writable register that controls the operation of each DMAC channel. DMABCR is initialized to H'0000 by a reset, and in standby mode. Bit 15--Full Address Enable 1 (FAE1): Specifies whether channel 1 is to be used in short address mode or full address mode. In full address mode, channels 1A and 1B are used together as a single channel. Bit 15 FAE1 0 1 Description Short address mode Full address mode (Initial value) Bit 14--Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 0 1 Description Short address mode Full address mode (Initial value) 217 Bits 13 and 12--Reserved: Can be read or written to. Bits 11 and 9--Data Transfer Acknowledge (DTA): These bits enable or disable clearing, when DMA transfer is performed, of the internal interrupt source selected by the data transfer factor setting. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting is cleared automatically by DMA transfer. When DTE = 1 and DTA = 1, the internal interrupt source selected by the data transfer factor setting does not issue an interrupt request to the CPU or DTC. When the DTE = 1 and the DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer. When the DTE = 0, the internal interrupt source selected by the data transfer factor setting issues an interrupt request to the CPU or DTC regardless of the DTA bit setting. The state of the DTME bit does not affect the above operations. Bit 11--Data Transfer Acknowledge 1 (DTA1): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 1 data transfer factor setting. Bit 11 DTA1 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled Bit 9--Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting. Bit 9 DTA0 0 1 Description Clearing of selected internal interrupt source at time of DMA transfer is disabled (Initial value) Clearing of selected internal interrupt source at time of DMA transfer is enabled 218 Bits 10 and 8--Reserved: Can be read or written to. Bits 7 and 5--Data Transfer Master Enable (DTME): Together with the DTE bit, these bits control enabling or disabling of data transfer on the relevant channel. When both the DTME bit and the DTE bit are set to 1, transfer is enabled for the channel. If the relevant channel is in the middle of a burst mode transfer when an NMI interrupt is generated, the DTME bit is cleared, the transfer is interrupted, and bus mastership passes to the CPU. When the DTME bit is subsequently set to 1 again, the interrupted transfer is resumed. In block transfer mode, however, the DTME bit is not cleared by an NMI interrupt, and transfer is not interrupted. The conditions for the DTME bit being cleared to 0 are as follows: * When initialization is performed * When NMI is input in burst mode * When 0 is written to the DTME bit The condition for DTME being set to 1 is as follows: * When 1 is written to DTME after DTME is read as 0 Bit 7--Data Transfer Master Enable 1 (DTME1): Enables or disables data transfer on channel 1. Bit 7 DTME1 0 1 Description Data transfer disabled. In burst mode, cleared to 0 by an NMI interrupt Data transfer enabled (Initial value) Bit 5--Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 0 1 Description Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) Data transfer enabled 219 Bits 6 and 4--Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored. If the activation source is an internal interrupt, an interrupt request is issued to the CPU or DTC. If the DTIE bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU. The conditions for the DTE bit being cleared to 0 are as follows: * When initialization is performed * When the specified number of transfers have been completed * When 0 is written to the DTE bit to forcibly abort the transfer, or for a similar reason When DTE = 1 and DTME = 1, data transfer is enabled and the DMAC waits for a request by the activation source selected by the data transfer factor setting. When a request is issued by the activation source, DMA transfer is executed. The condition for the DTE bit being set to 1 is as follows: * When 1 is written to the DTE bit after the DTE bit is read as 0 Bit 6--Data Transfer Enable 1 (DTE1): Enables or disables data transfer on channel 1. Bit 6 DTE1 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bit 4--Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 0 1 Description Data transfer disabled Data transfer enabled (Initial value) Bits 3 and 1--Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted. If the DTIEB bit is set to 1 when DTME = 0, the DMAC regards this as indicating a break in the transfer, and issues a transfer break interrupt request to the CPU or DTC. A transfer break interrupt can be canceled either by clearing the DTIEB bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the DTME bit to 1. 220 Bit 3--Data Transfer Interrupt Enable 1B (DTIE1B): Enables or disables the channel 1 transfer break interrupt. Bit 3 DTIE1B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bit 1--Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0 transfer break interrupt. Bit 1 DTIE0B 0 1 Description Transfer break interrupt disabled Transfer break interrupt enabled (Initial value) Bits 2 and 0--Data Transfer End Interrupt Enable A (DTIEA): These bits enable or disable an interrupt to the CPU or DTC when transfer ends. If DTIEA bit is set to 1 when DTE = 0, the DMAC regards this as indicating the end of a transfer, and issues a transfer end interrupt request to the CPU or DTC. A transfer end interrupt can be canceled either by clearing the DTIEA bit to 0 in the interrupt handling routine, or by performing processing to continue transfer by setting the transfer counter and address register again, and then setting the DTE bit to 1. Bit 2--Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) Bit 0--Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A 0 1 Description Transfer end interrupt disabled Transfer end interrupt enabled (Initial value) 221 7.4 7.4.1 Register Descriptions (3) DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned. The restrictions applied by DMAWER are valid for the DTC. Figure 7-2 shows the transfer areas for activating the DTC with a channel 0A transfer end interrupt, and reactivating channel 0A. The address register and count register area is re-set by the first DTC transfer, then the control register area is re-set by the second DTC chain transfer. When re-setting the control register area, perform masking by setting bits in DMAWER to prevent modification of the contents of the other channels. First transfer area MAR0A IOAR0A ETCR0A MAR0B IOAR0B ETCR0B MAR1A DTC IOAR1A ETCR1A MAR1B IOAR1B ETCR1B DMAWER DMACR0A DMACR1A Second transfer area using chain transfer DMATCR DMACR0B DMACR1B DMABCR Figure 7-2 Areas for Register Re-Setting by DTC (Example: Channel 0A) 222 Bit DMAWER R/W : : : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 WE0A 0 R/W Initial value : DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to the DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in standby mode. Bits 7 to 4--Reserved: Read-only bits, always read as 0. Bit 3--Write Enable 1B (WE1B): Enables or disables writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR by the DTC. Bit 3 WE1B 0 1 Description Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled (Initial value) Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled Bit 2--Write Enable 1A (WE1A): Enables or disables writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR by the DTC. Bit 2 WE1A 0 1 Description Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled (Initial value) Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled 223 Bit 1--Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR. Bit 1 WE0B 0 1 Description Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled (Initial value) Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled Bit 0--Write Enable 0A (WE0A): Enables or disables writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR. Bit 0 WE0A 0 1 Description Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled (Initial value) Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Writes by the DTC to bits 15 to 12 (FAE and SAE) in DMABCR are invalid regardless of the DMAWER settings. These bits should be changed, if necessary, by CPU processing. In writes by the DTC to bits 7 to 4 (DTE) in DMABCR, 1 can be written without first reading 0. To reactivate a channel set to full address mode, write 1 to both Write Enable A and Write Enable B for the channel to be reactivated. MAR, IOAR, and ETCR are always write-enabled regardless of the DMAWER settings. When modifying these registers, the channel for which the modification is to be made should be halted. 224 7.4.2 Bit DMA Terminal Control Register (DMATCR) : : : 7 -- 0 -- 6 -- 0 -- 5 TEE1 0 R/W 4 TEE0 0 R/W 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- DMATCR R/W Initial value : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit. DMATCR is initialized to H'00 by a reset, and in standby mode. Bits 7 and 6--Reserved: Read-only bits, always read as 0. Bit 5--Transfer End Enable 1 (TEE1): Enables or disables transfer end pin 1 (TEND1) output. Bit 5 TEE1 0 1 Description TEND1 pin output disabled TEND1 pin output enabled (Initial value) Bit 4--Transfer End Enable 0 (TEE0): Enables or disables transfer end pin 0 (TEND0) output. Bit 4 TEE0 0 1 Description TEND0 pin output disabled TEND0 pin output enabled (Initial value) The TEND pins are assigned only to channel B in short address mode. The transfer end signal indicates the transfer cycle in which the transfer counter reached 0, regardless of the transfer source. An exception is block transfer mode, in which the transfer end signal indicates the transfer cycle in which the block counter reached 0. Bits 3 to 0--Reserved: Read-only bits, always read as 0. 225 7.4.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP15 bit in MSTPCR is set to 1, the DMAC operation stops at the end of the bus cycle and a transition is made to module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 15--Module Stop (MSTP15): Specifies the DMAC module stop mode. Bits 15 MSTP15 0 1 Description DMAC module stop mode cleared DMAC module stop mode set (Initial value) 226 7.5 7.5.1 Operation Transfer Modes Table 7-5 lists the DMAC modes. Table 7-5 DMAC Transfer Modes Transfer Source TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete * interrupt A/D converter conversion end interrupt External request * Remarks * * Up to 4 channels can operate independently External request applies to channel B only Single address mode applies to channel B only Modes (1), (2), and (3) can also be specified for single address mode Transfer Mode Short address mode Dual (1) Sequential mode * address (2) Idle mode mode (3) Repeat mode * * * * (4) Single address mode Full address mode (5) Normal mode * * (6) Block transfer mode * External request Auto-request TPU channel 0 to 5 compare match/input capture A interrupt SCI transmission complete interrupt SCI reception complete interrupt A/D converter conversion end interrupt External request * * * * * Max. 2-channel operation, combining channels A and B With auto-request, burst mode transfer or cycle steal transfer can be selected * 227 Operation in each mode is summarized below. (1) Sequential mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (2) Idle mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer source address and transfer destination address are fixed. The transfer direction is programmable. (3) Repeat mode In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. When the specified number of transfers have been completed, the addresses and transfer counter are restored to their original settings, and operation is continued. No interrupt request is sent to the CPU or DTC. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable. (4) Single address mode In response to a single transfer request, the specified number of transfers are carried out between external memory and an external device, one byte or one word at a time. Unlike dual address mode, source and destination accesses are performed in parallel. Therefore, either the source or the destination is an external device which can be accessed with a strobe alone, using the DACK pin. One address is specified as 24 bits, and for the other, the pin is set automatically. The transfer direction is programmable. Modes (1), (2) and (3) can also be specified for single address mode. (5) Normal mode * Auto-request By means of register settings only, the DMAC is activated, and transfer continues until the specified number of transfers have been completed. An interrupt request can be sent to the CPU or DTC when transfer is completed. Both addresses are specified as 24 bits. Cycle steal mode: The bus is released to another bus master every byte or word transfer. Burst mode: The bus is held and transfer continued until the specified number of transfers have been completed. 228 * External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. (6) Block transfer mode In response to a single transfer request, a block transfer of the specified block size is carried out. This is repeated the specified number of times, once each time there is a transfer request. At the end of each single block transfer, one address is restored to its original setting. An interrupt request can be sent to the CPU or DTC when the specified number of block transfers have been completed. Both addresses are specified as 24 bits. 229 7.5.2 Sequential Mode Sequential mode can be specified by clearing the RPE bit in DMACR to 0. In sequential mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-6 summarizes register functions in sequential mode. Table 7-6 Register Functions in Sequential Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. 230 Figure 7-3 illustrates operation in sequential mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend Address T = L Address B = L + (-1)DTID * (2DTSZ * (N-1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-3 Operation in Sequential Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. 231 Figure 7-4 shows an example of the setting procedure for sequential mode. Sequential mode setting [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Clear the RPE bit to 0 to select sequential mode. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set the DTE bit to 1 to enable transfer. Read DMABCRL [5] Set DMABCRL [6] Sequential mode Figure 7-4 Example of Sequential Mode Setting Procedure 232 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-7 summarizes register functions in idle mode. Table 7-7 Register Functions in Idle Mode Function Register 23 MAR 23 H'FF 15 ETCR 15 IOAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register address register Destination Start address of Fixed address transfer destination register or transfer source address register Start address of Fixed transfer source or transfer destination Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 0 Destination Source 0 Transfer counter Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. 233 Figure 7-5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7-5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCR, is 65,536. Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. When the DMAC is used in single address mode, only channel B can be set. 234 Figure 7-6 shows an example of the setting procedure for idle mode. Idle mode setting [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Set the RPE bit to 1. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Set the DTIE bit to 1. * Set the DTE bit to 1 to enable transfer. Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Idle mode Figure 7-6 Example of Idle Mode Setting Procedure 235 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7-8 summarizes register functions in repeat mode. Table 7-8 Register Functions in Repeat Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Destination Start address of Incremented/ address transfer destination decremented every register or transfer source transfer. Initial setting is restored when value reaches H'0000 address register Start address of Fixed transfer source or transfer destination Number of transfers Fixed 23 H'FF 15 IOAR 7 ETCRH 0 Destination Source address register transfers 0 Holds number of 7 ETCRL 0 Transfer counter Number of transfers Decremented every transfer. Loaded with ETCRH value when count reaches H'00 Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit 236 MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256. In repeat mode, ETCRL functions as the transfer counter, and ETCRH is used to hold the number of transfers. ETCRL is decremented by 1 each time a transfer is executed, and when its value reaches H'00, it is loaded with the value in ETCRH. At the same time, the value set in MAR is restored in accordance with the values of the DTSZ and DTID bits in DMACR. The MAR restoration operation is as shown below. MAR = MAR - (-1)DTID * 2DTSZ * ETCRH The same value should be set in ETCRH and ETCRL. In repeat mode, operation continues until the DTE bit is cleared. To end the transfer operation, therefore, you should clear the DTE bit to 0. A transfer end interrupt request is not sent to the CPU or DTC. By setting the DTE bit to 1 again after it has been cleared, the operation can be restarted from the transfer after that terminated when the DTE bit was cleared. 237 Figure 7-7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend Address T = L Address B = L + (-1)DTID * (2DTSZ * (N-1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-7 Operation in Repeat mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. 238 Figure 7-8 shows an example of the setting procedure for repeat mode. Repeat mode setting [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL. [2] [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Set the RPE bit to 1. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. [6] Set each bit in DMABCRL. * Clear the DTIE bit to 0. * Set the DTE bit to 1 to enable transfer. Set DMABCRH Set transfer source and transfer destination addresses Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Repeat mode Figure 7-8 Example of Repeat Mode Setting Procedure 239 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR in DMACR. Table 7-9 summarizes register functions in single address mode. Table 7-9 Register Functions in Single Address Mode Function Register 23 MAR DTDIR = 0 DTDIR = 1 Initial Setting 0 Source Operation address register Write strobe Destination Start address of * address transfer destination register or transfer source Read strobe (Set automatically Strobe for external by SAE bit; IOAR is device invalid) Number of transfers * DACK pin 15 ETCR 0 Transfer counter Legend MAR : Memory address register IOAR : I/O address register ETCR : Transfer count register DTDIR : Data transfer direction bit DACK : Data transfer acknowledge Note: * See the operation descriptions in sections 7.5.2, Sequential Mode, 7.5.3, Idle Mode, and 7.5.4, Repeat Mode. MAR specifies the start address of the transfer source or transfer destination as 24 bits. IOAR is invalid; in its place the strobe for external devices (DACK) is output. 240 Figure 7-9 illustrates operation in single address mode (when sequential mode is specified). Address T Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Address B Legend Address T = L Address B = L + (-1)DTID * (2DTSZ * (N-1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7-9 Operation in Single Address Mode (When Sequential Mode is Specified) 241 Figure 7-10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH [1] [1] Set each bit in DMABCRH. * Clear the FAE bit to 0 to select short address mode. * Set the SAE bit to 1 to select single address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [2] Set the transfer source address/transfer destination address in MAR. Set transfer source and transfer destination addresses [2] [3] Set the number of transfers in ETCR. [4] Set each bit in DMACR. * Set the transfer data size with the DTSZ bit. * Specify whether MAR is to be incremented or decremented with the DTID bit. * Clear the RPE bit to 0 to select sequential mode. * Specify the transfer direction with the DTDIR bit. * Select the activation source with bits DTF3 to DTF0. [5] Read the DTE bit in DMABCRL as 0. Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set the DTE bit to 1 to enable transfer. Set DMABCRL [6] Single address mode Figure 7-10 Example of Single Address Mode Setting Procedure (When Sequential Mode is Specified) 242 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA. The transfer source is specified by MARA, and the transfer destination by MARB. Table 7-10 summarizes register functions in normal mode. Table 7-10 Register Functions in Normal Mode Register 23 MARA 23 MARB 15 ETCRA Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Transfer counter Start address of Incremented/decremented transfer destination every transfer, or fixed Number of transfers Decremented every transfer; transfer ends when count reaches H'0000 Legend MARA : Memory address register A MARB : Memory address register B ETCRA : Transfer count register A MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. The number of transfers is specified by ETCRA as 16 bits. ETCRA is decremented each time a transfer is performed, and when its value reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum number of transfers, when H'0000 is set in ETCRA, is 65,536. 243 Figure 7-11 illustrates operation in normal mode. Address TA Transfer Address TB Address BA Legend Address Address Address Address Where : Address BB TA TB BA BB LA LB N = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (N-1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (N-1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7-11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests. With auto-request, the DMAC is only activated by register setting, and the specified number of transfers are performed automatically. With auto-request, cycle steal mode or burst mode can be selected. In cycle steal mode, the bus is released to another bus master each time a transfer is performed. In burst mode, the bus is held continuously until transfer ends. 244 For setting details, see section 7.3.4, DMA Controller Register (DMACR). Figure 7-12 shows an example of the setting procedure for normal mode. Normal mode setting [1] Set each bit in DMABCRH. * Set the FAE bit to 1 to select full address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the number of transfers in ETCRA. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] [4] Set each bit in DMACRA and DMACRB. * Set the transfer data size with the DTSZ bit. * Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. * Clear the BLKE bit to 0 to select normal mode. * Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. * Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Read DMABCRL [5] Set DMABCRL [6] [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts with the DTIE bit. * Set both the DTME bit and the DTE bit to 1 to enable transfer. Normal mode Figure 7-12 Example of Normal Mode Setting Procedure 245 7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times. The transfer source is specified by MARA, and the transfer destination by MARB. Either the transfer source or the transfer destination can be selected as a block area (an area composed of a number of bytes or words). Table 7-11 summarizes register functions in block transfer mode. Table 7-11 Register Functions in Block Transfer Mode Register 23 MARA 23 MARB 7 Function 0 Source address Initial Setting Start address of transfer source Operation Incremented/decremented every transfer, or fixed register 0 Destination address register 0 Holds block ETCRAH Start address of Incremented/decremented transfer destination every transfer, or fixed Block size Fixed size Block size Block size Decremented every transfer; ETCRH value copied when count reaches H'00 Decremented every block transfer; transfer ends when count reaches H'0000 7 ETCRAL 15 ETCRB 0 counter 0 Block transfer counter Number of block transfers Legend MARA : Memory address register A MARB : Memory address register B ETCRA : Transfer count register A ETCRB : Transfer count register B MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. 246 Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA. To specify the number of transfers, if M is the size of one block (where M = 1 to 256) and N transfers are to be performed (where N = 1 to 65,536), M is set in both ETCRAH and ETCRAL, and N in ETCRB. Figure 7-13 illustrates operation in block transfer mode when MARB is designated as a block area. Address TA 1st block Transfer Block area Address TB 2nd block Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (M*N-1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (N-1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7-13 Operation in Block Transfer Mode (BLKDIR = 0) 247 Figure 7-14 illustrates operation in block transfer mode when MARA is designated as a block area. Address TA Block area Address BA Address TB Transfer Consecutive transfer of M bytes or words is performed in response to one request 2nd block 1st block Nth block Address BB Legend Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE * (-1)SAID * (2DTSZ * (N-1)) = LB + DAIDE * (-1)DAID * (2DTSZ * (M*N-1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7-14 Operation in Block Transfer Mode (BLKDIR = 1) 248 ETCRAL is decremented by 1 each time a byte or word transfer is performed. In response to a single transfer request, burst transfer is performed until the value in ETCRAL reaches H'00. ETCRAL is then loaded with the value in ETCRAH. At this time, the value in the MAR register for which a block designation has been given by the BLKDIR bit in DMACRA is restored in accordance with the DTSZ, SAID/DAID, and SAIDE/DAIDE bits in DMACR. ETCRB is decremented by 1 every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7-15 shows the operation flow in block transfer mode. 249 Start (DTE = DTME = 1) No Transfer request? Yes Acquire bus Read address specified by MARA MARA=MARA+SAIDE*(-1)SAID*2DTSZ Write to address specified by MARB MARB=MARB+DAIDE*(-1)DAID *2DTSZ ETCRAL=ETCRAL-1 No ETCRAL=H'00 Yes Release bus ETCRAL=ETCRAH BLKDIR=0 No Yes MARB=MARB-DAIDE*(-1)DAID*2DTSZ*ETCRAH MARA=MARA-SAIDE*(-1)SAID*2DTSZ*ETCRAH ETCRB=ETCRB-1 No ETCRB=H'0000 Yes Clear DTE bit to 0 to end transfer Figure 7-15 Operation Flow in Block Transfer Mode Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission complete and reception complete interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. 250 For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7-16 shows an example of the setting procedure for block transfer mode. Block transfer mode setting [1] Set each bit in DMABCRH. * Set the FAE bit to 1 to select full address mode. * Specify enabling or disabling of internal interrupt clearing with the DTA bit. [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB. [3] Set the block size in both ETCRAH and ETCRAL. Set the number of transfers in ETCRB. [4] Set each bit in DMACRA and DMACRB. * Set the transfer data size with the DTSZ bit. * Specify whether MARA is to be incremented, decremented, or fixed, with the SAID and SAIDE bits. * Set the BLKE bit to 1 to select block transfer mode. * Specify whether the transfer source or the transfer destination is a block area with the BLKDIR bit. * Specify whether MARB is to be incremented, decremented, or fixed, with the DAID and DAIDE bits. * Select the activation source with bits DTF3 to DTF0. [5] Read DTE = 0 and DTME = 0 in DMABCRL. Set DMABCRH Set transfer source and transfer destination addresses [2] Set number of transfers [3] Set DMACR [4] Read DMABCRL [5] Set DMABCRL [6] Block transfer mode [6] Set each bit in DMABCRL. * Specify enabling or disabling of transfer end interrupts to the CPU with the DTIE bit. * Set both the DTME bit and the DTE bit to 1 to enable transfer. Figure 7-16 Example of Block Transfer Mode Setting Procedure 251 7.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7-12. Table 7-12 DMAC Activation Sources Short Address Mode Channels 0A and 1A Channels 0B and 1B Full Address Mode Normal Mode X X X X X X X X X X X X X X X X Block Transfer Mode Activation Source Internal Interrupts ADI TXI0 RXI0 TXI1 RXI1 TGI0A TGI1A TGI2A TGI3A TGI4A TGI5A External Requests DREQ pin falling edge input DREQ pin low-level input Auto-request Legend : Can be specified X : Cannot be specified Activation by Internal Interrupt: An interrupt request selected as a DMAC activation source can be sent simultaneously to the CPU and DTC. For details, see section 5, Interrupt Controller. With activation by an internal interrupt, the DMAC accepts the request independently of the interrupt controller. Consequently, interrupt controller priority settings are not accepted. If the DMAC is activated by a CPU interrupt source or an interrupt source that is not used as a DTC activation source (DTA = 1), the interrupt source flag is cleared automatically by the DMA transfer. With ADI, TXI, and RXI interrupts, however, the interrupt source flag is not cleared unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an 252 activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority. When DTE = 0, such as after completion of a transfer, a request from the selected activation source is not sent to the DMAC, regardless of the DTA bit. In this case, the relevant interrupt request is sent to the CPU or DTC. In case of overlap with a CPU interrupt source or DTC activation source (DTA = 0), the interrupt request flag is not cleared by the DMAC. Activation by External Request: If an external request (DREQ pin) is specified as an activation source, the relevant port should be set to input mode in advance. Level sensing or edge sensing can be used for external requests. External request operation in normal mode (short address mode or full address mode) is described below. When edge sensing is selected, a 1-byte or 1-word transfer is executed each time a high-to-low transition is detected on the DREQ pin. The next transfer may not be performed if the next edge is input before transfer is completed. When level sensing is selected, the DMAC stands by for a transfer request while the DREQ pin is held high. While the DREQ pin is held low, transfers continue in succession, with the bus being released each time a byte or word is transferred. If the DREQ pin goes high in the middle of a transfer, the transfer is interrupted and the DMAC stands by for a transfer request. Activation by Auto-Request: Auto-request activation is performed by register setting only, and transfer continues to the end. With auto-request activation, cycle steal mode or burst mode can be selected. In cycle steal mode, the DMAC releases the bus to another bus master each time a byte or word is transferred. DMA and CPU cycles usually alternate. In burst mode, the DMAC keeps possession of the bus until the end of the transfer, and transfer is performed continuously. Single Address Mode: The DMAC can operate in dual address mode in which read cycles and write cycles are separate cycles, or single address mode in which read and write cycles are executed in parallel. In dual address mode, transfer is performed with the source address and destination address specified separately. 253 In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7-16 shows the data bus in single address mode. RD HWR, LWR A23 to A0 Address bus (Read) External memory D15 to D0 (high impedance) Data bus H8S/2350 Series (Write) External device DACK Figure 7-17 Data Bus in Single Address Mode When using the DMAC for single address mode reading, transfer is performed from external memory to the external device, and the DACK pin functions as a write strobe for the external device. When using the DMAC for single address mode writing, transfer is performed from the external device to external memory, and the DACK pin functions as a write strobe for the external device. Since there is no directional control for the external device, one or other of the above single directions should be used. Bus cycles in single address mode are in accordance with the settings of the bus controller for the external memory area. On the external device side, DACK is output in synchronization with the address strobe. For details of bus cycles, see section 7.5.11, DMAC Bus Cycles (Single Address Mode). Do not specify internal space for transfer addresses in single address mode. 254 7.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7-18. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations. As with CPU cycles, DMA cycles conform to the bus controller settings. CPU cycle T1 o DMAC cycle (1-word transfer) T2 T1 T2 T3 T1 T2 T3 CPU cycle Source address Address bus RD HWR LWR Destination address Figure 7-18 Example of DMA Transfer Bus Timing The address is not output to the external address bus in an access to on-chip memory or an internal I/O register. 255 7.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7-19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead o Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-19 Example of Short Address Mode Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. In repeat mode, when TEND output is enabled, TEND output goes low in the transfer cycle in which the transfer counter reaches 0. 256 Full Address Mode (Cycle Steal Mode): Figure 7-20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read o Address bus RD HWR LWR TEND DMA write DMA read DMA write DMA read DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-20 Example of Full Address Mode (Cycle Steal) Transfer A one-byte or one-word transfer is performed, and after the transfer the bus is released. While the bus is released one bus cycle is inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. 257 Full Address Mode (Burst Mode): Figure 7-21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead o Address bus RD HWR LWR TEND Bus release Burst transfer Last transfer cycle Bus release Figure 7-21 Example of Full Address Mode (Burst Mode) Transfer In burst mode, one-byte or one-word transfers are executed consecutively until transfer ends. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. If a request from another higher-priority channel is generated after burst transfer starts, that channel has to wait until the burst transfer ends. If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state, the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer has already been activated inside the DMAC, the bus is released on completion of a one-byte or one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer cycle of the burst transfer has already been activated inside the DMAC, execution continues to the end of the transfer even if the DTME bit is cleared. 258 Full Address Mode (Block Transfer Mode): Figure 7-22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space. DMA read o Address bus RD HWR LWR TEND Bus release DMA write DMA read DMA write DMA dead DMA read DMA write DMA read DMA write DMA dead Block transfer Bus release Last block transfer Bus release Figure 7-22 Example of Full Address Mode (Block Transfer Mode) Transfer A one-block transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a onestate DMA dead cycle is inserted after the DMA write cycle. One block is transmitted without interruption. NMI generation does not affect block transfer operation. 259 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-23 shows an example of DREQ pin falling edge activated normal mode transfer. Bus release o DREQ Address bus DMA control Channel Idle Request DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Request Read Write Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of o, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of o starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of o, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-23 Example of DREQ Pin Falling Edge Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next o cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA write cycle ends, acceptance resumes after the end of the write cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 260 Figure 7-24 shows an example of DREQ pin falling edge activated block transfer mode transfer. 1 block transfer Bus release o DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination 1 block transfer DMA Bus dead release DMA read DMA write DMA dead Bus release DMA read DMA write Transfer source Transfer destination Read Write Dead Idle Read Request Write Dead Idle Request clear period Request clear period Minimun of 2 cycles [1] [2] [3] Minimun of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of o, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of o starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of o, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-24 Example of DREQ Pin Falling Edge Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next o cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA dead cycle ends, acceptance resumes after the end of the dead cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 261 DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-25 shows an example of DREQ level activated normal mode transfer. Bus release o DREQ Address bus DMA control Channel Idle Request DMA read DMA write Bus release DMA read DMA write Bus release Transfer source Transfer destination Transfer source Transfer destination Read Write Idle Request Read Write Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of o, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the write cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of o, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-25 Example of DREQ Level Activated Normal Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next o cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the write cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 262 Figure 7-26 shows an example of DREQ level activated block transfer mode transfer. 1 block transfer Bus release o DREQ Address bus DMA control Channel Idle Request Transfer source Transfer destination 1 block transfer DMA Bus dead release DMA read DMA right DMA dead Bus release DMA read DMA right Transfer source Transfer destination Read Write Dead Idle Read Request Write Dead Idle Request clear period Request clear period Minimum of 2 cycles [1] [2] [3] Minimum of 2 cycles [4] [5] [6] [7] Acceptance resumes Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of o, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMA cycle is started. [4] [7] Acceptance is resumed after the dead cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of o, and the request is held.) [1] Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-26 Example of DREQ Level Activated Block Transfer Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next o cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the dead cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 263 7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7-27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read o Address bus RD DACK TEND DMA read DMA read DMA DMA read dead Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7-27 Example of Single Address Mode (Byte Read) Transfer 264 Figure 7-28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read o Address bus RD DACK TEND DMA read DMA read DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-28 Example of Single Address Mode (Word Read) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. 265 Single Address Mode (Write): Figure 7-29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write o Address bus HWR LWR DACK TEND DMA write DMA write DMA DMA write dead Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7-29 Example of Single Address Mode (Byte Write) Transfer 266 Figure 7-30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write o Address bus HWR LWR DACK TEND DMA write DMA write DMA dead Bus release Bus release Bus release Last transfer cycle Bus release Figure 7-30 Example of Single Address Mode (Word Write) Transfer A one-byte or one-word transfer is performed for one transfer request, and after the transfer the bus is released. While the bus is released one or more bus cycles are inserted by the CPU or DTC. In the transfer end cycle (the cycle in which the transfer counter reaches 0), a one-state DMA dead cycle is inserted after the DMA write cycle. 267 DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-31 shows an example of DREQ pin falling edge activated single address mode transfer. Bus release o DREQ Address bus DACK DMA single Bus release DMA single Bus release Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of o, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] Start of DMA cycle; DREQ pin high level sampling on the rising edge of o starts. [4] [7] When the DREQ pin high level has been sampled, acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of o, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-31 Example of DREQ Pin Falling Edge Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next o cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared, and DREQ pin high level sampling for edge detection is started. If DREQ pin high level sampling has been completed by the time the DMA single cycle ends, acceptance resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 268 DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7-32 shows an example of DREQ pin low level activated single address mode transfer. Bus release o DREQ Address bus DACK DMA single Bus release DMA single Bus release Transfer source/ destination Transfer source/ destination DMA control Idle Single Idle Single Idle Channel Request Minimum of 2 cycles Request clear period Request Minimum of 2 cycles Request clear period [1] [2] [3] [4] [5] [6] [7] Acceptance resumes [1] Acceptance resumes Acceptance after transfer enabling; the DREQ pin low level is sampled on the rising edge of o, and the request is held. [2] [5] The request is cleared at the next bus break, and activation is started in the DMAC. [3] [6] The DMAC cycle is started. [4] [7] Acceptance is resumed after the single cycle is completed. (As in [1], the DREQ pin low level is sampled on the rising edge of o, and the request is held.) Note: In write data buffer mode, bus breaks from [2] to [7] may be hidden, and not visible. Figure 7-32 Example of DREQ Pin Low Level Activated Single Address Mode Transfer DREQ pin sampling is performed every cycle, with the rising edge of the next o cycle after the end of the DMABCR write cycle for setting the transfer enabled state as the starting point. When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 269 7.5.12 Write Data Buffer Function DMAC internal-to-external dual address transfers and single address transfers can be executed at high speed using the write data buffer function, enabling system throughput to be improved. When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. Internal accesses are independent of the bus master, and DMAC dead cycles are regarded as internal accesses. A low level can always be output from the TEND pin if the bus cycle in which a low level is to be output is an external bus cycle. However, a low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Figure 7-33 shows an example of burst mode transfer from on-chip RAM to external memory using the write data buffer function. DMA read DMA write DMA read DMA write DMA read DMA write DMA read DMA write DMA dead o Internal address Internal read signal External address HWR, LWR TEND Figure 7-33 Example of Dual Address Transfer Using Write Data Buffer Function Figure 7-34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. 270 DMA read DMA single CPU read DMA single CPU read o Internal address Internal read signal External address RD DACK Figure 7-34 Example of Single Address Transfer Using Write Data Buffer Function When the write data buffer function is activated, the DMAC recognizes that the bus cycle concerned has ended, and starts the next operation. Therefore, DREQ pin sampling is started one state after the start of the DMA write cycle or single address transfer. 7.5.13 DMAC Multi-Channel Operation The DMAC channel priority order is: channel 0 > channel 1, and channel A > channel B. Table 713 summarizes the priority order for DMAC channels. Table 7-13 DMAC Channel Priority Order Short Address Mode Channel 0A Channel 0B Channel 1A Channel 1B Channel 1 Low Full Address Mode Channel 0 Priority High 271 If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7-13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer. Figure 7-35 shows a transfer example in which transfer requests are issued simultaneously for channels 0A, 0B, and 1. DMA read o Address bus RD HWR LWR DMA control Idle Read Channel 0A Channel 0B Channel 1 Bus release Write DMA write DMA read DMA write DMA read DMA DMA write read Idle Read Write Idle Read Write Read Request clear Request hold Request hold Selection Nonselection Request clear Request hold Bus release Selection Request clear Bus release Channel 1 transfer Channel 0A transfer Channel 0B transfer Figure 7-35 Example of Multi-Channel Transfer 272 7.5.14 Relation Between External Bus Requests, Refresh Cycles, the DTC, and the DMAC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle. In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh or external bus released state may be inserted after a write cycle. Since the DTC has a lower priority than the DMAC, the DTC does not operate until the DMAC releases the bus. When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these DMA cycles can be executed at the same time as refresh cycles or external bus release. However, simultaneous operation may not be possible when a write buffer is used. 273 7.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested. If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the CPU. The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again. Figure 7-36 shows the procedure for continuing transfer when it has been interrupted by an NMI interrupt on a channel designated for burst mode transfer. Resumption of transfer on interrupted channel [1] [2] [1] No Check that DTE = 1 and DTME = 0 in DMABCRL Write 1 to the DTME bit. DTE= 1 DTME= 0 Yes Set DTME bit to 1 [2] Transfer continues Transfer ends Figure 7-36 Example of Procedure for Continuing Transfer on Channel Interrupted by NMI Interrupt 274 7.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7-37 shows the procedure for forcibly terminating DMAC operation by software. Forced termination of DMAC [1] Clear the DTE bit in DMABCRL to 0. If you want to prevent interrupt generation after forced termination of DMAC operation, clear the DTIE bit to 0 at the same time. Clear DTE bit to 0 [1] Forced termination Figure 7-37 Example of Procedure for Forcibly Terminating DMAC Operation 275 7.5.17 Clearing Full Address Mode Figure 7-38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure. Clearing full address mode Stop the channel [1] [1] Clear both the DTE bit and the DTME bit in DMABCRL to 0; or wait until the transfer ends and the DTE bit is cleared to 0, then clear the DTME bit to 0. Also clear the corresponding DTIE bit to 0 at the same time. [2] Clear all bits in DMACRA and DMACRB to 0. [3] Clear the FAE bit in DMABCRH to 0. Initialize DMACR [2] Clear FAE bit to 0 [3] Initialization; operation halted Figure 7-38 Example of Procedure for Clearing Full Address Mode 276 7.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7-13 shows the interrupt sources and their priority order. Table 7-13 Interrupt Source Priority Order Interrupt Name DEND0A DEND0B DEND1A DEND1B Interrupt Source Short Address Mode Interrupt due to end of transfer on channel 0A Interrupt due to end of transfer on channel 0B Interrupt due to end of transfer on channel 1A Interrupt due to end of transfer on channel 1B Full Address Mode Interrupt due to end of transfer on channel 0 Interrupt due to break in transfer on channel 0 Interrupt due to end of transfer on channel 1 Interrupt due to break in transfer on channel 1 Low Interrupt Priority Order High Enabling or disabling of each interrupt source is set by means of the DTIE bit for the corresponding channel in DMABCR, and interrupts from each source are sent to the interrupt controller independently. The relative priority of transfer end interrupts on each channel is decided by the interrupt controller, as shown in table 7-13. Figure 7-39 shows a block diagram of a transfer end/transfer break interrupt. An interrupt is always generated when the DTIE bit is set to 1 while DTE bit is cleared to 0. DTE/ DTME Transfer end/transfer break interrupt DTIE Figure 7-39 Block Diagram of Transfer End/Transfer Break Interrupt In full address mode, a transfer break interrupt is generated when the DTME bit is cleared to o while DTIEB bit is set to 1. In both short address mode and full address mode, DMABCR should be set so as to prevent the occurrence of a combination that constitutes a condition for interrupt generation during setting. 277 7.7 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, the DMAC register should not be written to in a DMA transfer. Module Stop: When the MSTP15 bit in MSTPCR is set to 1, the DMAC clock stops, and the module stop state is entered. However, 1 cannot be written to the MSTP15 bit if any of the DMAC channels is enabled. This setting should therefore be made when DMAC operation is stopped. When the DMAC clock stops, DMAC register accesses can no longer be made. Since the following DMAC register settings are valid even in the module stop state, they should be invalidated, if necessary, before a module stop. * Transfer end/suspend interrupt (DTE = 0 and DTIE = 1) * TEND pin enable (TEE = 1) * DACK pin enable (FAE = 0 and SAE = 1) Medium-Speed Mode: When the DTA bit is 0, internal interrupt signals specified as DMAC transfer sources are edge-detected. In medium-speed mode, the DMAC operates on a medium-speed clock, while on-chip supporting modules operate on a high-speed clock. Consequently, if the period in which the relevant interrupt source is cleared by the CPU, DTC, or another DMAC channel, and the next interrupt is generated, is less than one state with respect to the DMAC clock (bus master clock), edge detection may not be possible and the interrupt may be ignored. Also, in medium-speed mode, DREQ pin sampling is performed on the rising edge of the mediumspeed clock. 278 Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel. (a) Write Data Buffer Function and DMAC Register Setting If the setting of is changed during execution of an external access by means of the write data buffer function, the external access may not be performed normally. The register that controls external accesses should only be manipulated when external reads, etc., are used with DMAC operation disabled, and the operation is not performed in parallel with external access. (b) Write Data Buffer Function and DMAC Operation Timing The DMAC can start its next operation during external access using the write data buffer function. Consequently, the DREQ pin sampling timing, TEND output timing, etc., are different from the case in which the write data buffer function is disabled. Also, internal bus cycles maybe hidden, and not visible. (c) Write Data Buffer Function and TEND Output A low level is not output from the TEND pin if the bus cycle in which a low level is to be output from the TEND pin is an internal bus cycle, and an external write cycle is executed in parallel with this cycle. Note, for example, that a low level may not be output from the TEND pin if the write data buffer function is used when data transfer is performed between an internal I/O register and on-chip memory. If at least one of the DMAC transfer addresses is an external address, a low level is output from the TEND pin. 279 Figure 7-40 shows an example in which a low level is not output at the TEND pin. DMA read o Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. DMA write Figure 7-40 Example in Which Low Level is Not Output at TEND Pin Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations. The operation is as follows: [1] Activation request wait state: Waits for detection of a low level on the DREQ pin, and switches to [2]. [2] Transfer wait state: Waits for DMAC data transfer to become possible, and switches to [3]. [3] Activation request disabled state: Waits for detection of a high level on the DREQ pin, and switches to [1]. After DMAC transfer is enabled, a transition is made to [1]. Thus, initial activation after transfer is enabled is performed by detection of a low level. Activation Source Acceptance: At the start of activation source acceptance, a low level is detected in both DREQ pin falling edge sensing and low level sensing. Similarly, in the case of an internal interrupt, the interrupt request is detected. Therefore, a request is accepted from an internal interrupt or DREQ pin low level that occurs before execution of the DMABCRL write to enable transfer. When the DMAC is activated, take any necessary steps to prevent an internal interrupt or DREQ pin low level remaining from the end of the previous transfer, etc. 280 Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 by the end of transfer or an abort, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is aborted, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1. An internal interrupt request following the end of transfer or an abort should be handled by the CPU as necessary. Channel Re-Setting: To reactivate a number of channels when multiple channels are enabled, use exclusive handling of transfer end interrupts, and perform DMABCR control bit operations exclusively. Note, in particular, that in cases where multiple interrupts are generated between reading and writing of DMABCR, and a DMABCR operation is performed during new interrupt handling, the DMABCR write data in the original interrupt handling routine will be incorrect, and the write may invalidate the results of the operations by the multiple interrupts. Ensure that overlapping DMABCR operations are not performed by multiple interrupts, and that there is no separation between read and write operations by the use of a bit-manipulation instruction. Also, when the DTE and DTME bits are cleared by the DMAC or are written with 0, they must first be read while cleared to 0 before the CPU can write a 1 to them. 281 282 Section 8 Data Transfer Controller 8.1 Overview The H8S/2350 Series includes a data transfer controller (DTC). The DTC can be activated by an interrupt or software, to transfer data. 8.1.1 Features The features of the DTC are: * Transfer possible over any number of channels Transfer information is stored in memory One activation source can trigger a number of data transfers (chain transfer) * Wide range of transfer modes Normal, repeat, and block transfer modes available Incrementing, decrementing, and fixing of source and destination addresses can be selected * Direct specification of 16-Mbyte address space possible 24-bit transfer source and destination addresses can be specified * Transfer can be set in byte or word units * A CPU interrupt can be requested for the interrupt that activated the DTC An interrupt request can be issued to the CPU after one data transfer ends An interrupt request can be issued to the CPU after the specified data transfers have completely ended * Activation by software is possible * Module stop mode can be set The initial setting enables DTC registers to be accessed. DTC operation is halted by setting module stop mode. 283 8.1.2 Block Diagram Figure 8-1 shows a block diagram of the DTC. The DTC's register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of the DTC register information and hence helping to increase processing speed. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1. Internal address bus Interrupt controller DTC Register information On-chip RAM CPU interrupt request Legend MRA, MRB CRA, CRB SAR DAR DTCERA to DTCERF DTVECR DTC service request : DTC mode registers A and B : DTC transfer count registers A and B : DTC source address register : DTC destination address register : DTC enable registers A to F : DTC vector register Figure 8-1 Block Diagram of DTC 284 MRA MRB CRA CRB DAR SAR Interrupt request Control logic DTCERA to DTCERF DTVECR Internal data bus 8.1.3 Register Configuration Table 8-1 summarizes the DTC registers. Table 8-1 Name DTC mode register A DTC mode register B DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B DTC enable registers DTC vector register Module stop control register DTC Registers Abbreviation MRA MRB SAR DAR CRA CRB DTCER DTVECR MSTPCR R/W --* 2 --* 2 --* 2 --* 2 --* 2 --* 2 R/W R/W R/W Initial Value Undefined Undefined Undefined Undefined Undefined Undefined H'00 H'00 H'3FFF Address* 1 --* 3 --* 3 --* 3 --* 3 --* 3 --* 3 H'FF30 to H'FF35 H'FF37 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Registers within the DTC cannot be read or written to directly. 3. Register information is located in on-chip RAM addresses H'F800 to H'FBFF. It cannot be located in external space. When the DTC is used, do not clear the RAME bit in SYSCR to 0. 285 8.2 8.2.1 Register Descriptions DTC Mode Register A (MRA) MRA is an 8-bit register that controls the DTC operating mode. Bit : 7 SM1 Initial value : R/W : Undefined -- 6 SM0 Undefined -- 5 DM1 Undefined -- 4 DM0 Undefined -- 3 MD1 Undefined -- 2 MD0 Undefined -- 1 DTS Undefined -- 0 Sz Undefined -- Bits 7 and 6--Source Address Mode 1 and 0 (SM1, SM0): These bits specify whether SAR is to be incremented, decremented, or left fixed after a data transfer. Bit 7 SM1 0 1 Bit 6 SM0 -- 0 1 Description SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Bits 5 and 4--Destination Address Mode 1 and 0 (DM1, DM0): These bits specify whether DAR is to be incremented, decremented, or left fixed after a data transfer. Bit 5 DM1 0 1 Bit 4 DM0 -- 0 1 Description DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) 286 Bits 3 and 2--DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 0 Bit 2 MD0 0 1 1 0 1 Description Normal mode Repeat mode Block transfer mode -- Bit 1--DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. Bit 1 DTS 0 1 Description Destination side is repeat area or block area Source side is repeat area or block area Bit 0--DTC Data Transfer Size (Sz): Specifies the size of data to be transferred. Bit 0 Sz 0 1 Description Byte-size transfer Word-size transfer 287 8.2.2 Bit DTC Mode Register B (MRB) : 7 CHNE Undefined -- 6 DISEL Undefined -- 5 -- Undefined -- 4 -- Undefined -- 3 -- Undefined -- 2 -- Undefined -- 1 -- Undefined -- 0 -- Undefined -- Initial value: R/W : MRB is an 8-bit register that controls the DTC operating mode. Bit 7--DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER is not performed. Bit 7 CHNE 0 1 Description End of DTC data transfer (activation waiting state is entered) DTC chain transfer (new register information is read, then data is transferred) Bit 6--DTC Interrupt Select (DISEL): Specifies whether interrupt requests to the CPU are disabled or enabled after a data transfer. Bit 6 DISEL 0 1 Description After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 (the DTC clears the interrupt source flag of the activating interrupt to 0) After a data transfer ends, the CPU interrupt is enabled (the DTC does not clear the interrupt source flag of the activating interrupt to 0) Bits 5 to 0--Reserved: These bits have no effect on DTC operation in the H8S/2350 Series, and should always be written with 0. 288 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.4 Bit DTC Destination Address Register (DAR) : 23 22 21 20 19 4 3 2 1 0 Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- Unde- Unde- Unde- Unde- Undefined fined fined fined fined ---------- DAR is a 24-bit register that designates the destination address of data to be transferred by the DTC. For word-size transfer, specify an even destination address. 8.2.5 Bit DTC Transfer Count Register A (CRA) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRAH CRAL CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC. In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits (CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the contents of CRAH are sent when the count reaches H'00. This operation is repeated. 289 8.2.6 Bit DTC Transfer Count Register B (CRB) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value: R/W : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -------------------------------- CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000. 8.2.7 Bit DTC Enable Registers (DTCER) : 7 DTCE7 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTCE0 0 R/W Initial value: R/W : The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources. The DTC enable registers are initialized to H'00 by a reset and in hardware standby mode. Bit n--DTC Activation Enable (DTCEn) Bit n DTCEn 0 Description DTC activation by this interrupt is disabled [Clearing conditions] * * 1 When the DISEL bit is 1 and the data transfer has ended When the specified number of transfers have ended (Initial value) DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended (n = 7 to 0) A DTCE bit can be set for each interrupt source that can activate the DTC. The correspondence between interrupt sources and DTCE bits is shown in table 8-4, together with the vector number generated for each interrupt controller. 290 For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 8.2.8 Bit DTC Vector Register (DTVECR) : 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value: R/W : Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt. DTVECR is initialized to H'00 by a reset and in hardware standby mode. Bit 7--DTC Software Activation Enable (SWDTE): Enables or disables DTC activation by software. When clearing the SWDTE bit to 0 by software, write 0 to SWDTE after reading SWDTE set to 1. Bit 7 SWDTE 0 Description DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 DTC software activation is enabled [Holding conditions] * * * When the DISEL bit is 1 and data transfer has ended When the specified number of transfers have ended During data transfer due to software activation (Initial value) Bits 6 to 0--DTC Software Activation Vectors 6 to 0 (DTVEC6 to DTVEC0): These bits specify a vector number for DTC software activation. The vector address is expressed as H'0400 + ((vector number) << 1). <<1 indicates a one-bit leftshift. For example, when DTVEC6 to DTVEC0 = H'10, the vector address is H'0420. 291 8.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP14 bit in MSTPCR is set to 1, the DTC operation stops at the end of the bus cycle and a transition is made to module stop mode. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 14--Module Stop (MSTP14): Specifies the DTC module stop mode. Bit 14 MSTP14 0 1 Description DTC module stop mode cleared DTC module stop mode set (Initial value) 292 8.3 8.3.1 Operation Overview When activated, the DTC reads register information that is already stored in memory and transfers data on the basis of that register information. After the data transfer, it writes updated register information back to memory. Pre-storage of register information in memory makes it possible to transfer data over any required number of channels. Setting the CHNE bit to 1 makes it possible to perform a number of transfers with a single activation. Figure 8-2 shows a flowchart of DTC operation. Start Read DTC vector Next transfer Read register information Data transfer Write register information CHNE=1 No Yes Transfer Counter= 0 or DISEL= 1 No Clear an activation flag Yes Clear DTCER End Interrupt exception handling Figure 8-2 Flowchart of DTC Operation The DTC transfer mode can be normal mode, repeat mode, or block transfer mode. 293 The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the transfer destination address. After each transfer, SAR and DAR are independently incremented, decremented, or left fixed. Table 8-2 outlines the functions of the DTC. Table 8-2 DTC Functions Address Registers Transfer Mode * Normal mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 Up to 65,536 transfers possible * Repeat mode One transfer request transfers one byte or one word Memory addresses are incremented or decremented by 1 or 2 After the specified number of transfers (1 to 256), the initial state resumes and operation continues * Block transfer mode One transfer request transfers a block of the specified size Block size is from 1 to 256 bytes or words Up to 65,536 transfers possible A block area can be designated at either the source or destination Transfer Transfer Activation Source Source Destination * * * * * * IRQ TPU TGI SCI TXI or RXI A/D converter ADI DMAC DEND Software 24 bits 24 bits 294 8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding DTCER bit is cleared. Table 8-3 shows activation source and DTCER clearance. The activation source flag, in the case of RXI0, for example, is the RDRF flag of SCI0. Table 8-3 Activation Source and DTCER Clearance When the DISEL Bit Is 1, or when the Specified Number of Transfers Have Ended The SWDTE bit remains set to 1 An interrupt is issued to the CPU Interrupt activation The corresponding DTCER bit remains set to 1 The activation source flag is cleared to 0 The corresponding DTCER bit is cleared to 0 The activation source flag remains set to 1 A request is issued to the CPU for the activation source interrupt When the DISEL Bit Is 0 and the Specified Number of Activation Source Transfers Have Not Ended Software activation The SWDTE bit is cleared to 0 Figure 8-3 shows a block diagram of activation source control. For details see section 5, Interrupt Controller. Source flag cleared Clear controller Clear DTCER Clear request Select On-chip supporting module IRQ interrupt Interrupt request Selection circuit DTC DTVECR Interrupt controller Interrupt mask CPU Figure 8-3 Block Diagram of DTC Activation Source Control 295 When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect. If there is more than one activation source at the same time, the DTC operates in accordance with the default priorities. 8.3.3 DTC Vector Table Figure 8-4 shows the correspondence between DTC vector addresses and register information. Table 8-4 shows the correspondence between activation, vector addresses, and DTCER bits. When the DTC is activated by software, the vector address is obtained from: H'0400 + (DTVECR[6:0] << 1) (where << 1 indicates a 1-bit left shift). For example, if DTVECR is H'10, the vector address is H'0420. The DTC reads the start address of the register information from the vector address set for each activation source, and then reads the register information from that start address. The register information can be placed at predetermined addresses in the on-chip RAM. The start address of the register information should be an integral multiple of four. The configuration of the vector address is the same in both normal and advanced modes, a 2-byte unit being used in both cases. These two bytes specify the lower bits of the address in the on-chip RAM. 296 Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs Origin of Interrupt Source Software Vector Number DTVECR Vector Address H'0400+ (DTVECR [6:0]<<1) H'0420 H'0422 H'0424 H'0426 H'0428 H'042A H'042C H'042E H'0438 H'0440 H'0442 H'0444 H'0446 H'0450 H'0452 H'0458 H'045A Interrupt Source Write to DTVECR DTCE* -- Priority High IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 ADI (A/D conversion end) TGI0A (GR0A compare match/ input capture) TGI0B (GR0B compare match/ input capture) TGI0C (GR0C compare match/ input capture) TGI0D (GR0D compare match/ input capture) TGI1A (GR1A compare match/ input capture) TGI1B (GR1B compare match/ input capture) TGI2A (GR2A compare match/ input capture) TGI2B (GR2B compare match/ input capture) External pin 16 17 18 19 20 21 22 23 DTCEA7 DTCEA6 DTCEA5 DTCEA4 DTCEA3 DTCEA2 DTCEA1 DTCEA0 DTCEB6 DTCEB5 DTCEB4 DTCEB3 DTCEB2 DTCEB1 DTCEB0 DTCEC7 DTCEC6 Low A/D TPU channel 0 28 32 33 34 35 TPU channel 1 40 41 TPU channel 2 44 45 297 Table 8-4 Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs (cont) Origin of Interrupt Source TPU channel 3 Vector Number 48 49 50 51 TPU channel 4 56 57 TPU channel 5 60 61 72 73 74 75 SCI channel 0 SCI channel 1 81 82 85 86 Vector Address H'0460 H'0462 H'0464 H'0466 H'0470 H'0472 H'0478 H'047A H'0490 H'0492 H'0494 H'0496 H'04A2 H'04A4 H'04AA H'04AC Interrupt Source TGI3A (GR3A compare match/ input capture) TGI3B (GR3B compare match/ input capture) TGI3C (GR3C compare match/ input capture) TGI3D (GR3D compare match/ input capture) TGI4A (GR4A compare match/ input capture) TGI4B (GR4B compare match/ input capture) TGI5A (GR5A compare match/ input capture) TGI5B (GR5B compare match/ input capture) DTCE* DTCEC5 DTCEC4 DTCEC3 DTCEC2 DTCEC1 DTCEC0 DTCED5 DTCED4 DTCEE7 DTCEE6 DTCEE5 DTCEE4 DTCEE3 DTCEE2 DTCEE1 DTCEE0 Priority High DMTEND0A (DMAC transfer end 0) DMAC DMTEND0B (DMAC transfer end 1) DMTEND1A (DMAC transfer end 2) DMTEND1B (DMAC transfer end 3) RXI0 (reception complete 0) TXI0 (transmit data empty 0) RXI1 (reception complete 1) TXI1 (transmit data empty 1) Low Note: * DTCE bits with no corresponding interrupt are reserved, and should be written with 0. 298 DTC vector address Register information start address Register information Chain transfer Figure 8-4 Correspondence between DTC Vector Address and Register Information 8.3.4 Location of Register Information in Address Space Figure 8-5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF). Lower address Register information start address 0 MRA MRB CRA MRA MRB CRA 4 bytes SAR DAR CRB Register information for 2nd transfer in chain transfer 1 2 SAR DAR CRB Register information 3 Chain transfer Figure 8-5 Location of Register Information in Address Space 299 8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. Table 8-5 Name DTC source address register DTC destination address register DTC transfer count register A DTC transfer count register B Register Information in Normal Mode Abbreviation SAR DAR CRA CRB Function Designates source address Designates destination address Designates transfer count Not used SAR Transfer DAR Figure 8-6 Memory Mapping in Normal Mode 300 8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. Table 8-6 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Repeat Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates source address Designates destination address Holds number of transfers Designates transfer count (8 bits x 2) Not used SAR or DAR Repeat area Transfer DAR or SAR Figure 8-7 Memory Mapping in Repeat Mode 301 8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt is requested. Table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. Table 8-7 Name DTC source address register DTC destination address register DTC transfer count register AH DTC transfer count register AL DTC transfer count register B Register Information in Block Transfer Mode Abbreviation SAR DAR CRAH CRAL CRB Function Designates transfer source address Designates destination address Holds block size Designates block size count Transfer count 302 First block SAR or DAR * * * Block area Transfer DAR or SAR Nth block Figure 8-8 Memory Mapping in Block Transfer Mode 303 8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8-9 shows the memory map for chain transfer. Source Destination Register information CHNE = 1 DTC vector address Register information start address Register information CHNE = 0 Source Destination Figure 8-9 Chain Transfer Memory Map In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt source flag for the activation source is not affected. 304 8.3.9 Operation Timing Figures 8-10 to 8-12 show an example of DTC operation timing. o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Transfer information write Figure 8-10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) o DTC activation request DTC request Vector read Address Transfer information read Data transfer Read Write Read Write Transfer information write Figure 8-11 DTC Operation Timing (Example of Block Transfer Mode, with Block Size of 2) 305 o DTC activation request DTC request Data transfer Vector read Address Transfer information read Read Write Read Write Data transfer Transfer Transfer information information write read Transfer information write Figure 8-12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for each execution status. Table 8-8 DTC Execution Statuses Vector Read I 1 1 1 Register Information Read/Write Data Read J K 6 6 6 1 1 N Data Write L 1 1 N Internal Operations M 3 3 3 Mode Normal Repeat Block transfer N: Block size (initial setting of CRAH and CRAL) 306 Table 8-9 Number of States Required for Each Execution Status OnChip RAM 32 1 SI SJ -- 1 OnChip ROM 16 1 1 -- On-Chip I/O Registers 8 2 -- -- 16 2 -- -- Object to be Accessed Bus width Access states Vector read Execution status Register information read/write Byte data read Word data read Byte data write Word data write Internal operation External Devices 8 2 4 -- 3 6+2m -- 16 2 2 -- 3 3+m -- SK SK SL SL SM 1 1 1 1 1 1 1 1 1 2 4 2 4 2 2 2 2 2 4 2 4 3+m 6+2m 3+m 6+2m 2 2 2 2 3+m 3+m 3+m 3+m The number of execution states is calculated from the formula below. Note that means the sum of all transfers activated by one activation event (the number in which the CHNE bit is set to 1, plus 1). Number of execution states = I * SI + (J * SJ + K * SK + L * SL ) + M * SM For example, when the DTC vector address table is located in on-chip ROM, normal mode is set, and data is transferred from the on-chip ROM to an internal I/O register, the time required for the DTC operation is 13 states. The time from activation to the end of the data write is 10 states. 307 8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC is activated when an interrupt used as an activation source is generated. [5] After the end of one data transfer, or after the specified number of data transfers have ended, the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue transferring data, set the DTCE bit to 1. Activation by Software: The procedure for using the DTC with software activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Check that the SWDTE bit is 0. [4] Write 1 to SWDTE bit and the vector number to DTVECR. [5] Check the vector number written to DTVECR. [6] After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested, the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the SWDTE bit is held at 1 and a CPU interrupt is requested. 308 8.3.12 Examples of Use of the DTC (1) Normal Mode An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the SCI RDR address in SAR, the start address of the RAM area where the data will be received in DAR, and 128 (H'0080) in CRA. CRB can be set to any value. [2] Set the start address of the register information at the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception complete (RXI) interrupt. Since the generation of a receive error during the SCI reception operation will disable subsequent reception, the CPU should be enabled to accept receive error interrupts. [5] Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is automatically cleared to 0. [6] When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt handling routine should perform wrap-up processing. (2) Chain Transfer An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG's NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU's TGR in the second half. This is because clearing of the activation source and interrupt generation at the end of the specified number of transfers are restricted to the second half of the chain transfer (transfer when CHNE = 0). [1] Perform settings for transfer to the PPG's NDR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0, MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value. 309 [2] Perform settings for transfer to the TPU's TGR. Set MRA to source address incrementing (SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0 = 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in DAR, and the data table size in CRA. CRB can be set to any value. [3] Locate the TPU transfer register information consecutively after the NDR transfer register information. [4] Set the start address of the NDR transfer register information to the DTC vector address. [5] Set the bit corresponding to TGIA in DTCER to 1. [6] Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA interrupt with TIER. [7] Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to be used as the output trigger. [8] Set the CST bit in TSTR to 1, and start the TCNT count operation. [9] Each time a TGRA compare match occurs, the next output value is transferred to NDR and the set value of the next output trigger period is transferred to TGRA. The activation source TGFA flag is cleared. [10] When the specified number of transfers are completed (the TPU transfer CRA value is 0), the TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the CPU. Termination processing should be performed in the interrupt handling routine. (3) Software Activation An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000. The vector number is H'60, so the vector address is H'04C0. [1] Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE = 0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR, and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB. [2] Set the start address of the register information at the DTC vector address (H'04C0). 310 [3] Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated by software. [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. To activate this transfer, go back to step 3. [6] If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred. [7] After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear the SWDTE bit to 0 and perform other wrap-up processing. 8.4 Interrupts An interrupt request is issued to the CPU when the DTC finishes the specified number of data transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation, the interrupt set as the activation source is generated. These interrupts to the CPU are subject to CPU mask level and interrupt controller priority level control. In the case of activation by software, a software activated data transfer end interrupt (SWDTEND) is generated. When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is generated. The interrupt handling routine should clear the SWDTE bit to 0. When the DTC is activated by software, an SWDTEND interrupt is not generated during a data transfer wait or during data transfer even if the SWDTE bit is set to 1. 311 8.5 Usage Notes Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written in the MSTP14 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0. DMAC Transfer End Interrupt: When DTC transfer is activated by a DMAC transfer end interrupt, regardless of the transfer counter and DISEL bit, the DMAC's DTE bit is not subject to DTC control, and the write data has priority. Consequently, an interrupt request may not be sent to the CPU when the DTC transfer counter reaches 0. DTCE Bit Setting: For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 312 Section 9 I/O Ports 9.1 Overview The H8S/2350 Series has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 9-1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states. Ports A to E in the H8S/2351 have a built-in pull-up MOS function, and in addition to DR and DDR, have a MOS input pull-up control register (PCR) to control the on/off state of MOS input pull-up. Port 3, and port A in the H8S/2351, have an open-drain control register (ODR) that controls the on/off state of the output buffer PMOS. Ports A to E can drive a single TTL load and 90 pF capacitive load, and ports 1, 2, 3, 5, 6, F, and G can drive a single TTL load and 30 pF capacitive load. All the I/O ports can drive a Darlington transistor when in output mode. Ports 1, A, B, and C can drive an LED (10 mA sink current). Port 2, and pins 64 to 67 and A 4 to A7, are Schmitt-triggered inputs. For block diagrams of the ports see appendix C, I/O Port Block Diagrams. 313 Table 9-1 Port Port Functions Pins P17/PO15/ TIOCB2/ TCLKD P16/PO14/ TIOCA2 P15/PO13/ TIOCB1/ TCLKC P14/PO12/ TIOCA1 P13/PO11/ TIOCD0/ TCLKB P12/PO10/ TIOCC0/ TCLKA P11/PO9/ TIOCB0/ DACK1 P10/PO8/ TIOCA0/ DACK0 P27/PO7/ TIOCB5 P26/PO6/ TIOCA5 P25/PO5/ TIOCB4 P24/PO4/ TIOCA4 P23/PO3/ TIOCD3 P22/PO2/ TIOCC3 P21/PO1/ TIOCB3 P20/PO0/ TIOCA3 P35/SCK1 P34/SCK0 P33/RxD1 P32/RxD0 P31/TxD1 P30/TxD0 Mode 1 Mode 2*1 Mode 3*1 Mode 4 Mode 5 Mode 6*1 Mode 7*1 Description Port 1 * 8-bit I/O port 8-bit I/O port also functioning as DMA controller output pins (DACK0 and DACK1), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, TIOCB2) and PPG output pins (PO15 to PO8) Port 2 * 8-bit I/O port * Schmitttriggered input 8-bit I/O port also functioning as TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, TIOCB5), and PPG output pins (PO7 to PO0) Port 3 * 6-bit I/O port * Open-drain output capability 6-bit I/O port also functioning as SCI (channels 0 and 1) I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, SCK1) Note: 1. Only applies to the H8S/2351. 314 Table 9-1 Port Port Functions (cont) Pins P47/AN7/ DA1 P46/AN6/ DA0 P45/AN5 P44/AN4 P43/AN3 P42/AN2 P41/AN1 P40/AN0 Mode 1 Mode 2*1 Mode 3*1 Mode 4 Mode 5 Mode 6*1 Mode 7*1 Description Port 4 * 8-bit input port 8-bit input port also functioning as A/D converter analog inputs (AN7 to AN0) and D/A converter analog outputs (DA1 and DA0) Port 5 * 4-bit I/O port P53/ADTRG 4-bit I/O port also functioning as A/D converter input pin (ADTRG) P52 P51 P50 P67/IRQ3/ CS7 P66/IRQ2/ CS6 P65/IRQ1 P64/IRQ0 P63/TEND1 P62/DREQ1 P61/TEND0/ CS5 P60/DREQ0/ CS4 8-bit I/O port also functioning as DMA controller I/O pins (DREQ0, TEND0, DREQ1, TEND1) and interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also functioning as DMA controller I/O pins (DREQ0, TEND0, DREQ1, TEND1), bus control output pins (CS4 to CS7), and interrupt input pins (IRQ0 to IRQ3) 8-bit I/O port also functioning as interrupt input pins (IRQ0 to IRQ3) Port 6 * 8-bit I/O port * Schmitttriggered input (P64 to P67) Note: 1. Only applies to the H8S/2351. 315 Table 9-1 Port Port Functions (cont) Pins PA 7/A 23 / IRQ7 PA 6/A 22 / IRQ6 PA 5/A 21 / IRQ5 Mode 1 Mode 2*1 Mode 3*1 Dual function as I/O ports and interrupt input pins (IRQ7 to IRQ4) Mode 4 Mode 5 Mode 6*1 Mode 7*1 When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ4) When DDR = 1: address output When DDR = 0 (after reset): input ports When DDR = 1: address output I/O ports Dual function as I/O ports and interrupt input pins (IRQ7 to IRQ4) Description Port A * 8-bit I/O port * Built-in MOS input pull-up*1 * Open-drain output capability*1 * Schmitttriggered input (PA4 to PA 7) When DDR = 0 (after reset): dual function as input ports and interrupt input pins (IRQ7 to IRQ5) When DDR = 1: address output PA 4/A 20 / IRQ4 Address output PA 3/A 19 to PA 0/A 16 I/O ports Address output Port B * 8-bit I/O PB 7/A 15 to port*1 PB 0/A 8 * Built-in MOS input pull-up*1 Address output When I/O port DDR = 0 (after reset): input port When DDR = 1: address output Address output When I/O port DDR = 0 (after reset): input port When DDR = 1: address output Port C * 8-bit I/O PC7/A 7 to port*1 PC0/A 0 * Built-in MOS input pull-up*1 Address output When I/O port DDR = 0 (after reset): input port When DDR = 1: address output Address output When I/O port DDR = 0 (after reset): input port When DDR = 1: address output Note: 1. Only applies to the H8S/2351. 316 Table 9-1 Port Port Functions (cont) Pins Mode 1 Mode 2*1 Mode 3*1 Data bus input/ output I/O port Mode 4 Mode 5 Mode 6*1 Mode 7*1 I/O port Description Port D * 8-bit I/O PD7/D15 to port*1 PD0/D8 * Built-in MOS input pull-up*1 Port E * 8-bit I/O PE 7/D7 to port PE 0/D0 * Built-in MOS input pull-up*1 Port F * 8-bit I/O port PF7/o Data bus input/output In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output When DDR = 0: input port I/O port In 8-bit bus mode: I/O port In 16-bit bus mode: data bus input/output I/O port When When DDR = 0: input port DDR = 0 When DDR = 1 (after reset): When DDR = 1 (after (after o output reset): reset): input port o output When DDR = 1: o output When DDR = 0 (after reset): input port When DDR = 1: o output PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/ WAIT/ BREQO AS, RD, HWR, LWR I/O port output AS, RD, HWR, LWR output I/O port When WAITE = 0 I/O port and BREQOE = 0 (after reset): I/O port When WAITE = 1 and BREQOE = 0: WAIT input When WAITE = 0 and BREQOE = 1: BREQO input When WAITE = 0 and BREQOE = 0 (after reset): I/O port When WAITE = 1: and BREQOE = 0: WAIT input When WAITE = 0 and BREQOE = 1: BREQO output When RMTS2 to RMTS0 = B'001 to B'011, CW2 = 0, and LCASS = 0: LCAS output When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output I/O port PF1/BACK PF0/BREQ When BRLE = 0 (after reset): I/O port When BRLE = 1: BREQ input, BACK output Note: 1. Only applies to the H8S/2351. 317 Table 9-1 Port Port Functions (cont) Pins PG 4/CS0 Mode 1 Mode 2*1 Mode 3*1 When DDR= 0*2: input port When DDR= 1*3: CS0 output PG 3/CS1 PG 2/CS2 PG 1/CS3 PG 0/CAS I/O port When DDR = 0 (after reset): input port When DDR = 1: CS1, CS2, CS3 output DRAM space set: CAS output Otherwise (after reset): I/O port I/O port Mode 4 Mode 5 Mode 6*1 Mode 7*1 I/O port Description Port G * 5-bit I/O port When DDR = 0*2: input port When DDR = 1*3: CS0 output Notes: 1. Only applies to the H8S/2351. 2. After a reset in mode 2 or 6 3. After a reset in mode 1, 4 or 5 318 9.2 9.2.1 Port 1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are the same in all operating modes. Figure 9-1 shows the port 1 pin configuration. Port 1 pins P17 (I/O)/PO15 (output)/TIOCB2 (I/O)/TCLKD (input) P16 (I/O)/PO14 (output)/TIOCA2 (I/O) P15 (I/O)/PO13 (output)/TIOCB1 (I/O)/TCLKC (input) P14 (I/O)/PO12 (output)/TIOCA1 (I/O) Port 1 P13 (I/O)/PO11 (output)/TIOCD0 (I/O)/TCLKB (input) P12 (I/O)/PO10 (output)/TIOCC0 (I/O)/TCLKA (input) P11 (I/O)/PO9 (output)/TIOCB0 (I/O)/DACK1 (output) P10 (I/O)/PO8 (output)/TIOCA0 (I/O)/DACK0 (output) Figure 9-1 Port 1 Pin Functions 319 9.2.2 Register Configuration Table 9-2 shows the port 1 register configuration. Table 9-2 Name Port 1 data direction register Port 1 data register Port 1 register Port 1 Registers Abbreviation P1DDR P1DR PORT1 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB0 H'FF60 H'FF50 Note: * Lower 16 bits of the address. Port 1 Data Direction Register (P1DDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. P1DDR cannot be read; if it is, an undefined value will be read. Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P1DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the PPG, TPU, and DMAC are initialized by a manual reset, the pin states are determined by the P1DDR and P1DR specifications. Port 1 Data Register (P1DR) Bit : 7 P17DR Initial value : R/W : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 P14DR 0 R/W 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W 0 P10DR 0 R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 320 Port 1 Register (PORT1) Bit : 7 P17 Initial value : R/W : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R 3 P13 --* R 2 P12 --* R 1 P11 --* R 0 P10 --* R Note: * Determined by state of pins P17 to P10. PORT1 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 1 pins (P17 to P10) must always be performed on P1DR. If a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read. If a port 1 read is performed while P1DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT1 contents are determined by the pin states, as P1DDR and P1DR are initialized. PORT1 retains its prior state after a manual reset, and in software standby mode. 321 9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC output pins (DACK0 and DACK1). Port 1 pin functions are shown in table 9-3. Table 9-3 Pin Port 1 Pin Functions Selection Method and Pin Functions P17/PO15/TIOCB2/ The pin function is switched as shown below according to the combination of TCLKD the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bits TPSC2 to TPSC0 in TCR0 and TCR5, bit NDER15 in NDERH, and bit P17DDR. TPU Channel 2 Setting P17DDR NDER15 Pin function Table Below (1) -- -- TIOCB2 output 0 -- P17 input TCLKD input * 2 Table Below (2) 1 0 P17 output 1 1 PO15 output TIOCB2 input * 1 Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1. 2. TCLKD input when the setting for either TCR0 or TCR5 is: TPSC2 to TPSC0 = B'111. TCLKD input when channels 2 and 4 are set to phase counting mode. TPU Channel 2 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx -- -- (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx CCLR1, CCLR0 Output function -- -- -- -- Other than B'10 PWM mode 2 output B'10 -- x: Don't care 322 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P16/PO14/TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, bits CCLR1 and CCLR0 in TCR2, bit NDER14 in NDERH, and bit P16DDR. TPU Channel 2 Setting P16DDR NDER14 Pin function Table Below (1) -- -- TIOCA2 output 0 -- P16 input Table Below (2) 1 0 P16 output 1 1 PO14 output TIOCA2 input * 1 Note: 1. TIOCA2 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 = 1. TPU Channel 2 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx -- -- (1) (2) B'001x (1) B'0011 (1) B'0011 (2) B'0000, B'01xx B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- -- Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 PWM mode 2 output B'01 -- PWM mode 1 output * 2 x: Don't care Note: 2. TIOCB2 output is disabled. 323 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P15/PO13/TIOCB1/ The pin function is switched as shown below according to the combination of TCLKC the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR. TPU Channel 1 Setting P15DDR NDER13 Pin function Table Below (1) -- -- TIOCB1 output 0 -- P15 input Table Below (2) 1 0 P15 output 1 1 PO13 output TIOCB1 input * 1 TCLKC input * 2 Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000, B'01xx and IOB3 to IOB0 = B'10xx. 2. TCLKC input when the setting for either TCR0 or TCR2 is: TPSC2 to TPSC0 = B'110; or when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101. TCLKC input when channels 2 and 4 are set to phase counting mode. TPU Channel 1 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) B'0000, B'01xx CCLR1, CCLR0 Output function -- -- Other than B'10 PWM mode 2 output B'10 -- Output compare output -- -- -- x: Don't care 324 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P14/PO12/TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, bits CCLR1 and CCLR0 in TCR1, bit NDER12 in NDERH, and bit P14DDR. TPU Channel 1 Setting P14DDR NDER12 Pin function Table Below (1) -- -- TIOCA1 output 0 -- P14 input Table Below (2) 1 0 P14 output 1 1 PO12 output TIOCA1 input * 1 Note: 1. TIOCA1 input when MD3 to MD0 = B'0000, B'01xx, IOA3 to IOA0 = B'10xx. TPU Channel 1 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx -- -- (1) (2) B'001x (1) B'0010 Other than B'xx00 -- PWM mode 1 output* 2 (1) B'0011 (2) B'0000, B'01xx B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 PWM mode 2 output B'01 -- x: Don't care Note: 2. TIOCB1 output is disabled. 325 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P13/PO11/TIOCD0/ The pin function is switched as shown below according to the combination of TCLKB the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR. TPU Channel 0 Setting P13DDR NDER11 Pin function Table Below (1) -- -- TIOCD0 output 0 -- P13 input Table Below (2) 1 0 P13 output 1 1 PO11 output TIOCD0 input * 1 TCLKB input * 2 Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000, IOD3 to IOD0 =B'10xx. 2. TCLKB input when the setting for TCR0 to TCR2 is: TPSC2 to TPSC0 = B'101; TCLKB input when channels 1 and 5 are set to phase counting mode. TPU Channel 0 Setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx -- B'0001 to B'0011 B'0101 to B'0111 -- (1) (2) B'0010 -- B'xx00 (2) (1) B'0011 Other than B'xx00 (2) CCLR2 to CCLR0 Output function -- -- Other than B'110 PWM mode 2 output B'110 -- Output compare output -- -- -- x: Don't care 326 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P12/PO10/TIOCC0/ The pin function is switched as shown below according to the combination of TCLKA the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, bits CCLR2 to CCLR0 in TCR0, bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR. TPU Channel 0 Setting P12DDR NDER10 Pin function Table Below (1) -- -- TIOCC0 output 0 -- P12 input Table Below (2) 1 0 P12 output 1 1 PO10 output TIOCC0 input * 1 TCLKA input * 2 Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. 2. TCLKA input when the setting for TCR0 to TCR5 is: TPSC2 to TPSC0 = B'100; TCLKA input when channels 1 and 5 are set to phase counting mode. TPU Channel 0 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- -- Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 PWM mode 2 output B'101 -- Output compare output -- PWM mode 1 output* 3 -- x: Don't care Note: 3. TIOCD0 output is disabled. When BFA = 1 or BFB = 1 in TMDR0, output is disabled and setting (2) applies. 327 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P11/PO9/TIOCB0/ The pin function is switched as shown below according to the combination of DACK1 the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER9 in NDERH, bit SAE1 in DMABCRH, and bit P11DDR. SAE1 TPU Channel 0 Setting P11DDR NDER9 Pin function Table Below (1) -- -- TIOCB0 output 0 -- P11 input 0 Table Below (2) 1 0 P11 output 1 1 PO9 output -- -- DACK1 output 1 TIOCB0 input * 1 Note: 1. TIOCB0 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. TPU Channel 0 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'010 PWM mode 2 output B'010 -- Output compare output -- -- -- x: Don't care 328 Table 9-3 Pin Port 1 Pin Functions (cont) Selection Method and Pin Functions P10/PO8/TIOCA0/ The pin function is switched as shown below according to the combination of DACK0 the TPU channel 0 setting by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, bits CCLR2 to CCLR0 in TCR0, bit NDER8 in NDERH, bit SAE0 in DMABCRH, and bit P10DDR. SAE0 TPU Channel 0 Setting P10DDR NDER8 Pin function Table Below (1) -- -- TIOCA0 output 0 -- P10 input 0 Table Below (2) 1 0 P10 output 1 1 PO8 output 1 -- -- -- DACK0 output TIOCA0 input * 1 Note: 1. TIOCA0 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. TPU Channel 0 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- -- Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'001 PWM mode 2 output B'001 -- Output compare output -- PWM mode 1 output* 2 -- x: Don't care Note: 2. TIOCB0 output is disabled. 329 9.3 9.3.1 Port 2 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 9-2 shows the port 2 pin configuration. Port 2 pins P27 (I/O)/PO7 (output)/TIOCB5 (I/O) P26 (I/O)/PO6 (output)/TIOCA5 (I/O) P25 (I/O)/PO5 (output)/TIOCB4 (I/O) Port 2 P24 (I/O)/PO4 (output)/TIOCA4 (I/O) P23 (I/O)/PO3 (output)/TIOCD3 (I/O) P22 (I/O)/PO2 (output)/TIOCC3 (I/O) P21 (I/O)/PO1 (output)/TIOCB3 (I/O) P20 (I/O)/PO0 (output)/TIOCA3 (I/O) Figure 9-2 Port 2 Pin Functions 330 9.3.2 Register Configuration Table 9-4 shows the port 2 register configuration. Table 9-4 Name Port 2 data direction register Port 2 data register Port 2 register Port 2 Registers Abbreviation P2DDR P2DR PORT2 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB1 H'FF61 H'FF51 Note: * Lower 16 bits of the address. Port 2 Data Direction Register (P2DDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : R/W : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. P2DDR cannot be read; if it is, an undefined value will be read. Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P2DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the PPG and TPU are initialized by a manual reset, the pin states are determined by the P2DDR and P2DR specifications. Port 2 Data Register (P2DR) Bit : 7 P27DR Initial value : R/W : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 P24DR 0 R/W 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W 0 P20DR 0 R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). P2DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 331 Port 2 Register (PORT2) Bit : 7 P27 Initial value : R/W : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R 3 P23 --* R 2 P22 --* R 1 P21 --* R 0 P20 --* R Note: * Determined by state of pins P27 to P20. PORT2 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 2 pins (P27 to P20) must always be performed on P2DR. If a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read. If a port 2 read is performed while P2DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT2 contents are determined by the pin states, as P2DDR and P2DR are initialized. PORT2 retains its prior state after a manual reset, and in software standby mode. 332 9.3.3 Pin Functions Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5). Port 2 pin functions are shown in table 9-5. Table 9-5 Pin P27/PO7/TIOCB5 Port 2 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER7 in NDERL, and bit P27DDR. TPU Channel 5 Setting P27DDR NDER7 Pin function Table Below (1) -- -- TIOCB5 output 0 -- P27 input Table Below (2) 1 0 P27 output TIOCB5 input * Note: * TIOCB5 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 = 1. TPU Channel 5 Setting MD3 to MD0 IOB3 to IOB0 1 1 PO7 output (2) B'0000 B'0100 B'1xxx -- -- (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) B'0000, B'01xx Other than B'xx00 CCLR1, CCLR0 Output function -- -- -- -- Other than B'10 PWM mode 2 output B'10 -- x: Don't care 333 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 5 setting by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, bits CCLR1 and CCLR0 in TCR5, bit NDER6 in NDERL, and bit P26DDR. TPU Channel 5 Setting P26DDR NDER6 Pin function Table Below (1) -- -- TIOCA5 output 0 -- P26 input Table Below (2) 1 0 P26 output TIOCA5 input * 1 Note: 1. TIOCA5 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 = 1. TPU Channel 5 Setting MD3 to MD0 IOA3 to IOA0 1 1 PO6 output P26/PO6/TIOCA5 (2) B'0000 B'0100 B'1xxx -- -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0000, B'01xx B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- -- Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 PWM mode 2 output B'01 -- PWM mode 1 output* 2 x: Don't care Note: 2. TIOCB5 output is disabled. 334 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4 and bits IOB3 to IOB0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER5 in NDERL, and bit P25DDR. TPU Channel 4 Setting P25DDR NDER5 Pin function Table Below (1) -- -- TIOCB4 output 0 -- P25 input Table Below (2) 1 0 P25 output 1 1 PO5 output P25/PO5/TIOCB4 TIOCB4 input * 1 Note: 1. TIOCB4 input when MD3 to MD0 = B'0000, B'01xx, and IOB3 to IOB0 = B'10xx. TPU Channel 4 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0100 B'1xxx -- -- (1) B'0001 to B'0011 B'0101 to B'0111 -- Output compare output (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) B'0000, B'01xx Other than B'xx00 CCLR1, CCLR0 Output function -- -- -- -- Other than B'10 PWM mode 2 output B'10 -- x: Don't care 335 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 4 setting by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, bits CCLR1 and CCLR0 in TCR4, bit NDER4 in NDERL, and bit P24DDR. TPU Channel 4 Setting P24DDR NDER4 Pin function Table Below (1) -- -- TIOCA4 output 0 -- P24 input Table Below (2) 1 0 P24 output 1 1 PO4 output P24/PO4/TIOCA4 TIOCA4 input * 1 TMRI1 input Note: 1. TIOCA4 input when MD3 to MD0 = B'0000, B'01xx, and IOA3 to IOA0 = B'10xx. TPU Channel 4 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0100 B'1xxx -- -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0000, B'01xx B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- Output compare output -- -- -- Other than B'xx00 CCLR1, CCLR0 Output function Other than B'01 PWM mode 2 output B'01 -- PWM mode 1 output* 2 x: Don't care Note: 2. TIOCB4 output is disabled. 336 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER3 in NDERL, and bit P23DDR. TPU Channel 3 Setting P23DDR NDER3 Pin function Table Below (1) -- -- TIOCD3 output 0 -- P23 input Table Below (2) 1 0 P23 output 1 1 PO3 output P23/PO3/TIOCD3 TIOCD3 input * 1 Note: 1. TIOCD3 input when MD3 to MD0 = B'0000, and IOD3 to IOD0 = B'10xx. TPU Channel 3 Setting MD3 to MD0 IOD3 to IOD0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'110 PWM mode 2 output B'110 -- Output compare output -- -- -- x: Don't care 337 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, bits CCLR2 to CCLR0 in TCR3, bit NDER2 in NDERL, and bit P22DDR. TPU Channel 3 Setting P22DDR NDER2 Pin function Table Below (1) -- -- TIOCC3 output 0 -- P22 input Table Below (2) 1 0 P22 output 1 1 PO2 output P22/PO2/TIOCC3 TIOCC3 input * 1 Note: 1. TIOCC3 input when MD3 to MD0 = B'0000, and IOC3 to IOC0 = B'10xx. TPU Channel 3 Setting MD3 to MD0 IOC3 to IOC0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- -- Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'101 PWM mode 2 output B'101 -- Output compare output -- PWM mode 1 output* 2 -- x: Don't care Note: 2. TIOCD3 output is disabled. When BFA = 1 or BFB = 1 in TMDR3, output is disabled and setting (2) applies. 338 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER1 in NDERL, and bit P21DDR. TPU Channel 3 Setting P21DDR NDER1 Pin function Table Below (1) -- -- TIOCB3 output 0 -- P21 input Table Below (2) 1 0 P21 output 1 1 PO1 output P21/PO1/TIOCB3 TIOCB3 input * 1 Note: 1. TIOCB3 input when MD3 to MD0 = B'0000, and IOB3 to IOB0 = B'10xx. TPU Channel 3 Setting MD3 to MD0 IOB3 to IOB0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) B'0001 to B'0011 B'0101 to B'0111 -- (2) B'0010 -- (2) B'xx00 (1) B'0011 (2) Other than B'xx00 CCLR2 to CCLR0 Output function -- -- Other than B'010 PWM mode 2 output B'010 -- Output compare output -- -- -- x: Don't care 339 Table 9-5 Pin Port 2 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the TPU channel 3 setting by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, bits CCLR2 to CCLR0 in TCR3, bit NDER0 in NDERL, and bit P20DDR. TPU Channel 3 Setting P20DDR NDER0 Pin function Table Below (1) -- -- TIOCA3 output 0 -- P20 input Table Below (2) 1 0 P20 output 1 1 PO0 output P20/PO0/TIOCA3 TIOCA3 input * 1 Note: 1. TIOCA3 input when MD3 to MD0 = B'0000, and IOA3 to IOA0 = B'10xx. TPU Channel 3 Setting MD3 to MD0 IOA3 to IOA0 (2) B'0000 B'0000 B'0100 B'1xxx -- (1) (2) B'001x (1) B'0010 (1) B'0011 (2) B'0001 to B'xx00 B'0011 B'0101 to B'0111 -- -- -- Other than B'xx00 CCLR2 to CCLR0 Output function Other than B'001 PWM mode 2 output B'001 -- Output compare output -- PWM mode 1 output* 2 -- x: Don't care Note: 2. TIOCB3 output is disabled. 340 9.4 9.4.1 Port 3 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 9-3 shows the port 3 pin configuration. Port 3 pins P35 (I/O)/ SCK1 (I/O) P34 (I/O)/ SCK0 (I/O) Port 3 P33 (I/O)/ RxD1 (input) P32 (I/O)/ RxD0 (input) P31 (I/O)/ TxD1 (output) P30 (I/O)/ TxD0 (output) Figure 9-3 Port 3 Pin Functions 9.4.2 Register Configuration Table 9-6 shows the port 3 register configuration. Table 9-6 Name Port 3 data direction register Port 3 data register Port 3 register Port 3 open drain control register Port 3 Registers Abbreviation P3DDR P3DR PORT3 P3ODR R/W W R/W R R/W Initial Value* 2 H'00 H'00 Undefined H'00 Address* 1 H'FEB2 H'FF62 H'FF52 H'FF76 Notes: 1. Lower 16 bits of the address. 2. Value of bits 5 to 0. 341 Port 3 Data Direction Register (P3DDR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read. Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P3DDR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the SCI is initialized, the pin states are determined by the P3DDR and P3DR specifications. Port 3 Data Register (P3DR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 P35DR 0 R/W 4 P34DR 0 R/W 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W 0 P30DR 0 R/W Undefined Undefined P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. P3DR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 342 Port 3 Register (PORT3) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 P35 --* R 4 P34 --* R 3 P33 --* R 2 P32 --* R 1 P31 --* R 0 P30 --* R Undefined Undefined Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. If a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read. If a port 3 read is performed while P3DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT3 contents are determined by the pin states, as P3DDR and P3DR are initialized. PORT3 retains its prior state after a manual reset, and in software standby mode. Port 3 Open Drain Control Register (P3ODR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Undefined Undefined P3ODR is an 8-bit readable/writable register that controls the PMOS on/off status for each port 3 pin (P35 to P30). Bits 7 and 6 are reserved; they return an undetermined value if read, and cannot be modified. Setting a P3ODR bit to 1 makes the corresponding port 3 pin an NMOS open-drain output pin, while clearing the bit to 0 makes the pin a CMOS output pin. P3ODR is initialized to H'00 (bits 5 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 343 9.4.3 Pin Functions Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are shown in table 9-7. Table 9-7 Pin P35/SCK1 Port 3 Pin Functions Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR. CKE1 C/A CKE0 P35DDR Pin function 0 P35 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK1 input pin P35 SCK1 SCK1 output pin* output pin* output pin* Note: * When P35ODR = 1, the pin becomes an NMOS open-drain output. P34/SCK0 The pin function is switched as shown below according to the combination of bit C/A in the SCI0 SMR, bits CKE0 and CKE1 in SCR, and bit P34DDR. CKE1 C/A CKE0 P34DDR Pin function 0 P34 input pin 0 1 0 1 -- 0 1 -- -- 1 -- -- -- SCK0 input pin P34 SCK0 SCK0 output pin* output pin* output pin* Note: * When P34ODR = 1, the pin becomes an NMOS open-drain output. 344 Table 9-7 Pin P33/RxD1 Port 3 Pin Functions (cont) Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE P33DDR Pin function 0 P33 input pin 0 1 P33 output pin* 1 -- RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR. RE P32DDR Pin function 0 P32 input pin 0 1 P32 output pin* 1 -- RxD0 input pin Note: * When P32ODR = 1, the pin becomes an NMOS open-drain output. P31/TxD1 The pin function is switched as shown below according to the combination of bit TE in the SCI1 SCR, and bit P31DDR. TE P31DDR Pin function 0 P31 input pin 0 1 P31 output pin* 1 -- TxD1 output pin Note: * When P31ODR = 1, the pin becomes an NMOS open-drain output. P30/TxD0 The pin function is switched as shown below according to the combination of bit TE in the SCI0 SCR, and bit P30DDR. TE P30DDR Pin function 0 P30 input pin 0 1 P30 output pin* 1 -- TxD0 output pin Note: * When P30ODR = 1, the pin becomes an NMOS open-drain output. 345 9.5 9.5.1 Port 4 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 9-4 shows the port 4 pin configuration. Port 4 pins P47 (input)/ AN7 (input)/DA1 (output) P46 (input)/ AN6 (input)/DA0 (output) P45 (input)/ AN5 (input) Port 4 P44 (input)/ AN4 (input) P43 (input)/ AN3 (input) P42 (input)/ AN2 (input) P41 (input)/ AN1 (input) P40 (input)/ AN0 (input) Figure 9-4 Port 4 Pin Functions 346 9.5.2 Register Configuration Table 9-8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9-8 Name Port 4 register Port 4 Registers Abbreviation PORT4 R/W R Initial Value Undefined Address* H'FF53 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed. Bit : 7 P47 Initial value : R/W : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R 3 P43 --* R 2 P42 --* R 1 P41 --* R 0 P40 --* R Note: * Determined by state of pins P47 to P40. 9.5.3 Pin Functions Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). 347 9.6 9.6.1 Port 5 Overview Port 5 is a 4-bit I/O port. Port 5 pins also function as the A/D converter input pin (ADTRG). Port 5 pin functions are the same in all operating modes. Figure 9-5 shows the port 5 pin configuration. Port 5 pins P53 (I/O)/ADTRG (input) Port 5 P52 (I/O) P51 (I/O) P50 (I/O) Figure 9-5 Port 5 Pin Functions 9.6.2 Register Configuration Table 9-9 shows the port 5 register configuration. Table 9-9 Name Port 5 data direction register Port 5 data register Port 5 register Port 5 Registers Abbreviation P5DDR P5DR PORT5 R/W W R/W R Initial Value* 2 H'0 H'0 Undefined Address* 1 H'FEB4 H'FF64 H'FF54 Notes: 1. Lower 16 bits of the address. 2. Value of bits 3 to 0. 348 Port 5 Data Direction Register (P5DDR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 0 W 2 0 W 1 0 W 0 0 W P53DDR P52DDR P51DDR P50DDR Undefined Undefined Undefined Undefined P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 5. Bits 7 to 4 are reserved. P5DDR cannot be read; if it is, an undefined value will be read. Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P5DDR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port 5 Data Register (P5DR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 P50DR 0 R/W Undefined Undefined Undefined Undefined P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P53 to P50). Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. P5DR is initialized to H'0 (bits 3 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port 5 Register (PORT5) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 -- -- 3 P53 --* R 2 P52 --* R 1 P51 --* R 0 P50 --* R Undefined Undefined Undefined Undefined Note: * Determined by state of pins P53 to P50. PORT5 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 5 pins (P53 to P50) must always be performed on P5DR. 349 Bits 7 to 4 are reserved; they return an undetermined value if read, and cannot be modified. If a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read. If a port 5 read is performed while P5DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT5 contents are determined by the pin states, as P5DDR and P5DR are initialized. PORT5 retains its prior state after a manual reset, and in software standby mode. 9.6.3 Pin Functions Port 5 pins also function as the A/D converter input pin (ADTRG). Port 5 pin functions are shown in table 9-10. Table 9-10 Port 5 Pin Functions Pin P53/ADTRG Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bits TRGS1 and TRGS0 in the A/D converter ADCR, and bit P53DDR. P53DDR Pin function 0 P53 input pin 1 P53 output pin ADTRG input pin* Note: * ADTRG input when TRGS0 = TRGS1 = 1. P52 The pin function is switched as shown below according to bit P52DDR. P52DDR Pin function 0 P52 input pin 1 P52 output pin P51 The pin function is switched as shown below according to bit P51DDR. P51DDR Pin function 0 P51 input pin 1 P51 output pin P50 The pin function is switched as shown below according to bit P50DDR. P50DDR Pin function 0 P50 input pin 1 P50 output pin 350 9.7 9.7.1 Port 6 Overview Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). The functions of pins P65 to P62 are the same in all operating modes, while the functions of pins P67, P6 6, P6 1, and P60 change according to the operating mode. Pins P67 to P64 are schmitt-triggered inputs. Figure 9-6 shows the port 6 pin configuration. Port 6 pins P67 / IRQ3 / CS7 P66 / IRQ2 / CS6 P65 / IRQ1 Port 6 P64 / IRQ0 P63 / TEND1 P62 / DREQ1 P61 / TEND0/ CS5 P60 / DREQ0/ CS4 Pin functions in modes 1, 2, 3, and 7* P67 (I/O)/IRQ3 (input) P66 (I/O)/IRQ2 (input) P65 (I/O)/IRQ1 (input) P64 (I/O)/IRQ0 (input) P63 (I/O)/TEND1 (output) P62 (I/O)/DREQ1 (input) P61 (I/O)/TEND0 (output) P60 (I/O)/DREQ0 (input) Pin functions in modes 4 to 6* P67 (input)/IRQ3 (input)/CS7 (output) P66 (input)/IRQ2 (input)/CS6 (output) P65 (I/O)/IRQ1 (input) P64 (I/O)/IRQ0 (input) P63 (I/O)/TEND1 (output) P62 (I/O)/DREQ1 (input) P61 (input)/TEND0 (output)/CS5 (output) P60 (input)/DREQ0 (input)/CS4 (output) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-6 Port 6 Pin Functions 351 9.7.2 Register Configuration Table 9-11 shows the port 6 register configuration. Table 9-11 Port 6 Registers Name Port 6 data direction register Port 6 data register Port 6 register Abbreviation P6DDR P6DR PORT6 R/W W R/W R Initial Value H'00 H'00 Undefined Address* H'FEB5 H'FF65 H'FF55 Note: * Lower 16 bits of the address. Port 6 Data Direction Register (P6DDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : R/W : P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 6. P6DDR cannot be read; if it is, an undefined value will be read. Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output pin, while clearing the bit to 0 makes the pin an input pin. P6DDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. As the DMAC is initialized by a manual reset, the pin states are determined by the P6DDR and P6DR specifications. Port 6 Data Register (P6DR) Bit : 7 P67DR Initial value : R/W : 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 P64DR 0 R/W 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W 0 P60DR 0 R/W P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). P6DR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 352 Port 6 Register (PORT6) Bit : 7 P67 Initial value : RW : --* R 6 P66 --* R 5 P65 --* R 4 P64 --* R 3 P63 --* R 2 P62 --* R 1 P61 --* R 0 P60 --* R Note: * Determined by state of pins P67 to P60. PORT6 is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port 6 pins (P67 to P60) must always be performed on P6DR. If a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read. If a port 6 read is performed while P6DDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORT6 contents are determined by the pin states, as P6DDR and P6DR are initialized. PORT6 retains its prior state after a manual reset, and in software standby mode. 353 9.7.3 Pin Functions Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 9-12. Table 9-12 Port 6 Pin Functions Pin P67/IRQ3/CS7 Selection Method and Pin Functions The pin function is switched as shown below according to bit P67DDR. Mode P67DDR Pin function Modes 1, 2, 3, 7* 0 P67 input pin 1 Modes 4 to 6* 0 1 P67 output pin P67 input pin CS7 output pin IRQ3 interrupt input pin P66/IRQ2/CS6 The pin function is switched as shown below according to bit P66DDR. Mode P66DDR Pin function Modes 1, 2, 3, 7* 0 P66 input pin 1 Modes 4 to 6* 0 1 P66 output pin P66 input pin CS6 output pin IRQ2 interrupt input pin P65/IRQ1 The pin function is switched as shown below according to bit P65DDR. P65DDR Pin function 0 P65 input pin 1 P65 output pin IRQ1 interrupt input pin P64/IRQ0 The pin function is switched as shown below according to bit P64DDR. P64DDR Pin function 0 P64 input pin 1 P64 output pin IRQ0 interrupt input pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 354 Table 9-12 Port 6 Pin Functions (cont) Pin P63/TEND1 Selection Method and Pin Functions The pin function is switched as shown below according to the combination of bit TEE1 in the DMAC DMATCR, and bit P63DDR. TEE1 P63DDR Pin function 0 P63 input pin 0 1 P63 output pin 1 -- TEND1 output P62/DREQ1 The pin function is switched as shown below according to bit P62DDR. P62DDR Pin function 0 P62 input pin DERQ1 input 1 P62 output pin P61/TEND0/CS5 The pin function is switched as shown below according to the combination of bit TEE0 in the DMAC DMATCR, and bit P61DDR. Mode TEE0 P61DDR Pin function 0 Modes 1, 2, 3, 7* 0 1 1 -- 0 Modes 4 to 6* 0 1 1 -- P61 P61 TEND0 input pin output pin output P61 CS5 TEND0 input pin output pin output P60/DREQ0/CS4 The pin function is switched as shown below according to bit P60DDR. Mode P60DDR Pin function Modes 1, 2, 3, 7* 0 P60 input pin 1 Modes 4 to 6* 0 1 P60 output pin P60 input pin CS4 output pin DREQ0 input Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 355 9.8 9.8.1 Port A Overview Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. Port A has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Pins PA7 to PA 4 are schmitt-triggered inputs. Figure 9-7 shows the port A pin configuration. Port A pins PA7/A23/IRQ7 PA6/A22/IRQ6 PA5/A21/IRQ5 Port A PA4/A20/IRQ4 PA3/A19 PA2/A18 PA1/A17 PA0/A16 Pin functions in modes 1, 2, 3, and 7* PA7 (I/O)/IRQ7 (input) PA6 (I/O)/IRQ6 (input) PA5 (I/O)/IRQ5 (input) PA4 (I/O)/IRQ4 (input) PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O) Pin functions in modes 4 and 5* PA7 (input)/A23 (output)/IRQ7 (input) PA6 (input)/A22 (output)/IRQ6 (input) PA5 (input)/A21 (output)/IRQ5 (input) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) Pin functions in mode 6* PA7 (input)/A23 (output)/IRQ7 (input) PA6 (input)/A22 (output)/IRQ6 (input) PA5 (input)/A21 (output)/IRQ5 (input) PA4 (input)/A20 (output)/IRQ4 (input) PA3 (input)/A19 (output) PA2 (input)/A18 (output) PA1 (input)/A17 (output) PA0 (input)/A16 (output) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-7 Port A Pin Functions 356 9.8.2 Register Configuration Table 9-13 shows the port A register configuration. Table 9-13 Port A Registers Name Port A data direction register Port A data register Port A register 2 Abbreviation PADDR PADR PORTA R/W W R/W R R/W R/W Initial Value H'00 H'00 Undefined H'00 H'00 Address* 1 H'FEB9 H'FF69 H'FF59 H'FF70 H'FF77 Port A MOS pull-up control register* PAPCR Port A open-drain control register* 2 PAODR Notes: 1. Lower 16 bits of the address. 2. Only applies to the H8S/2351. Port A Data Direction Register (PADDR) Bit Initial value R/W : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PADDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port A. PADDR cannot be read; if it is, an undefined value will be read. PADDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 2, 3, and 7* Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 4 and 5 The corresponding port A pins are address outputs irrespective of the value of bits PA4DDR to PA0DDR. Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. 357 * Mode 6* Setting a PADDR bit to 1 makes the corresponding port A pin an address output while clearing the bit to 0 makes the pin an input port. Note: * Modes 2 3, 6, and 7 only applies to the H8S/2351. Port A Data Register (PADR) Bit : 7 PA7DR Initial value : R/W : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4 PA4DR 0 R/W 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W 0 PA0DR 0 R/W PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0). PADR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Register (PORTA) Bit : 7 PA7 Initial value : R/W : --* R 6 PA6 --* R 5 PA5 --* R 4 PA4 --* R 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R 0 PA0 --* R Note: * Determined by state of pins PA7 to PA0. PORTA is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port A pins (PA7 to PA 0) must always be performed on PADR. If a port A read is performed while PADDR bits are set to 1, the PADR values are read. If a port A read is performed while PADDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTA contents are determined by the pin states, as PADDR and PADR are initialized. PORTA retains its prior state after a manual reset, and in software standby mode. 358 Port A MOS Pull-Up Control Register (PAPCR) [H8S/2351 Only] Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : R/W : PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. All the bits are valid in modes 1, 2, 3, 6, and 7, and bits 7 to 5 are valid in modes 4 and 5. When a PADDR bit is cleared to 0 (input port setting), setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PAPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port A Open Drain Control Register (PAODR) [H8S/2351 Only] Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : R/W : PAODR is an 8-bit readable/writable register that controls whether PMOS is on or off for each port A pin (PA7 to PA 0). All bits are valid in modes 1, 2, 3, and 7. Setting a PAODR bit to 1 makes the corresponding port A pin an NMOS open-drain output, while clearing the bit to 0 makes the pin a CMOS output. PAODR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 359 9.8.3 Pin Functions Mode 1 [H8S/2350]; Modes 1, 2, 3 and 7 [H8S/2351]: In mode 1, 2, 3, and 7*, port A pins function as I/O ports and interrupt input pins. Input or output can be specified for each pin on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an output port, while clearing the bit to 0 makes the pin an input port. Port A pin functions in modes 1, 2, 3, and 7* are shown in figure 9-8. Note: * Modes 2, 3, and 7 only apply to the H8S/2351. PA7 (I/O)/IRQ7 (input) PA6 (I/O)/IRQ6 (input) PA5 (I/O)/IRQ5 (input) Port A PA4 (I/O)/IRQ4 (input) PA3 (I/O) PA2 (I/O) PA1 (I/O) PA0 (I/O) Figure 9-8 Port A Pin Functions (Modes 1, 2, 3, and 7) 360 Modes 4 and 5: In modes 4 and 5, the lower 5 bits of port A are designated as address outputs automatically, while the upper 3 bits function as address outputs or input ports and interrupt input pins. Input or output can be specified individually for the upper 3 bits. Setting one of bits PA7DDR to PA5DDR to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Port A pin functions in modes 4 and 5 are shown in figure 9-9. When PADDR = 1 A23 (output) A22 (output) A21 (output) Port A A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) When PADDR = 0 PA7 (input)/IRQ7 (input) PA6 (input)/IRQ6 (input) PA5 (input)/IRQ5 (input) A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) Figure 9-9 Port A Pin Functions (Modes 4 and 5) Mode 6 [H8S/2351 Only]: In mode 6, port A pins function as address outputs or input ports and interrupt input pins. Input or output can be specified on an individual bit basis. Setting a PADDR bit to 1 makes the corresponding port A pin an address output, while clearing the bit to 0 makes the pin an input port. Port A pin functions in mode 6 are shown in figure 9-10. When PADDR = 1 A23 (output) A22 (output) A21 (output) Port A A20 (output) A19 (output) A18 (output) A17 (output) A16 (output) When PADDR = 0 PA7 (input)/IRQ7 (input) PA6 (input)/IRQ6 (input) PA5 (input)/IRQ5 (input) PA4 (input)/IRQ4 (input) PA3 (input) PA2 (input) PA1 (input) PA0 (input) Figure 9-10 Port A Pin Functions (Mode 6) 361 9.8.4 MOS Input Pull-Up Function [H8S/2351 Only] Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA 5 in modes 4 and 5, and by all pins in modes 1, 2, 3, 6, and 7. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-14 summarizes the MOS input pull-up states. Table 9-14 MOS Input Pull-Up States (Port A) Modes 1 to 3, 6, 7 PA7 to PA 0 4, 5 PA7 to PA 5 PA4 to PA 0 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode ON/OFF ON/OFF OFF In Other Operations Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PADDR = 0 and PAPCR = 1; otherwise off. 362 9.9 9.9.1 Port B Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. However, in the H8S/2350, port B pins function only as address outputs. Port B has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Figure 9-11 shows the port B pin configuration. Port B pins PB7 / A15 PB6 / A14 PB5 / A13 PB4 / A12 Port B PB3 / A11 PB2 / A10 PB1 / A9 PB0 / A8 Pin functions in modes 1, 4, and 5 A15 (output) A14 (output) A13 (output) A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Pin functions in modes 2 and 6* PB7 (input)/A15 (output) PB6 (input)/A14 (output) PB5 (input)/A13 (output) PB4 (input)/A12 (output) PB3 (input)/A11 (output) PB2 (input)/A10 (output) PB1 (input)/A9 (output) PB0 (input)/A8 (output) Pin functions in modes 3 and 7* PB7 (I/O) PB6 (I/O) PB5 (I/O) PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-11 Port B Pin Functions 363 9.9.2 Register Configuration [H8S/2351 Only] Table 9-15 shows the port B register configuration. Table 9-15 Port B Registers Name Port B data direction register Port B data register Port B register Port B MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PBDDR PBDR PORTB PBPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address * H'FEBA H'FF6A H'FF5A H'FF71 Port B Data Direction Register (PBDDR) [H8S/2351 Only] Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Initial value : R/W : PBDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port B. PBDDR cannot be read; if it is, an undefined value will be read. PBDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 The corresponding port B pins are address outputs irrespective of the value of the PBDDR bits. * Modes 2 and 6 Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. 364 Port B Data Register (PBDR) [H8S/2351 Only] Bit : 7 PB7DR Initial value : R/W : 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port B Register (PORTB) [H8S/2351 Only] Bit : 7 PB7 Initial value : R/W : --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R Note: * Determined by state of pins PB7 to PB0. PORTB is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port B pins (PB 7 to PB0) must always be performed on PBDR. If a port B read is performed while PBDDR bits are set to 1, the PBDR values are read. If a port B read is performed while PBDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTB contents are determined by the pin states, as PBDDR and PBDR are initialized. PORTB retains its prior state after a manual reset, and in software standby mode. 365 Port B MOS Pull-Up Control Register (PBPCR) [H8S/2351 Only] Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis. When a PBDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PBPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 9.9.3 Pin Functions Modes 1, 4, and 5: In modes 1, 4, and 5, port B pins are automatically designated as address outputs. Port B pin functions in modes 1, 4, and 5 are shown in figure 9-12. A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) Figure 9-12 Port B Pin Functions (Modes 1, 4, and 5) 366 Modes 2 and 6 [H8S/2351 Only]: In modes 2 and 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. Port B pin functions in modes 2 and 6 are shown in figure 9-13. When PBDDR = 1 A15 (output) A14 (output) A13 (output) Port B A12 (output) A11 (output) A10 (output) A9 (output) A8 (output) When PBDDR = 0 PB7 (input) PB6 (input) PB5 (input) PB4 (input) PB3 (input) PB2 (input) PB1 (input) PB0 (input) Figure 9-13 Port B Pin Functions (Modes 2 and 6) Modes 3 and 7 [H8S/2351 Only]: In modes 3 and 7, port B pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an output port, while clearing the bit to 0 makes the pin an input port. Port B pin functions in modes 3 and 7 are shown in figure 9-14. PB7 (I/O) PB6 (I/O) PB5 (I/O) Port B PB4 (I/O) PB3 (I/O) PB2 (I/O) PB1 (I/O) PB0 (I/O) Figure 9-14 Port B Pin Functions (Modes 3 and 7) 367 9.9.4 MOS Input Pull-Up Function [H8S/2351 Only] Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-16 summarizes the MOS input pull-up states. Table 9-16 MOS Input Pull-Up States (Port B) Modes 1, 4, 5 2, 3, 6, 7 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode OFF ON/OFF In Other Operations Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PBDDR = 0 and PBPCR = 1; otherwise off. 368 9.10 9.10.1 Port C Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. However, in the H8S/2350, port C pins function only as address outputs. Port C has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 Only). Figure 9-15 shows the port C pin configuration. Port C pins PC7 / A7 PC6 / A6 PC5 / A5 Port C PC4 / A4 PC3 / A3 PC2 / A2 PC1 / A1 PC0 / A0 Pin functions in modes 1, 4, and 5 A7 (output) A6 (output) A5 (output) A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Pin functions in modes 2 and 6* PC7 (input)/ A7 (output) PC6 (input)/ A6 (output) PC5 (input)/ A5 (output) PC4 (input)/ A4 (output) PC3 (input)/ A3 (output) PC2 (input)/ A2 (output) PC1 (input)/ A1 (output) PC0 (input)/ A0 (output) Pin functions in modes 3 and 7* PC7 (I/O) PC6 (I/O) PC5 (I/O) PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-15 Port C Pin Functions 369 9.10.2 Register Configuration [H8S/2351 Only] Table 9-17 shows the port C register configuration. Table 9-17 Port C Registers Name Port C data direction register Port C data register Port C register Port C MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PCDDR PCDR PORTC PCPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address * H'FEBB H'FF6B H'FF5B H'FF72 Port C Data Direction Register (PCDDR) [H8S/2351 Only] Bit Initial value R/W : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port C. PCDDR cannot be read; if it is, an undefined value will be read. PCDDR is initialized to H'00 by a power-on reset and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 The corresponding port C pins are address outputs irrespective of the value of the PCDDR bits. * Modes 2 and 6 Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. 370 Port C Data Register (PCDR) [H8S/2351 Only] Bit : 7 PC7DR Initial value : R/W : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 PC2DR 0 R/W 1 0 R/W 0 0 R/W PC6DR PC5DR PC4DR PC3DR PC1DR PC0DR PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port C Register (PORTC) [H8S/2351 Only] Bit : 7 PC7 Initial value : R/W : --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R Note: * Determined by state of pins PC7 to PC0. PORTC is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port C pins (PC 7 to PC0) must always be performed on PCDR. If a port C read is performed while PCDDR bits are set to 1, the PCDR values are read. If a port C read is performed while PCDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTC contents are determined by the pin states, as PCDDR and PCDR are initialized. PORTC retains its prior state after a manual reset, and in software standby mode. 371 Port C MOS Pull-Up Control Register (PCPCR) [H8S/2351] Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis. When a PCDDR bit is cleared to 0 (input port setting) in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PCPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 9.10.3 Pin Functions Modes 1, 4, and 5: In modes 1, 4, and 5, port C pins are automatically designated as address outputs. Port C pin functions in modes 1, 4, and 5 are shown in figure 9-16. A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) Figure 9-16 Port C Pin Functions (Modes 1, 4, and 5) 372 Modes 2 and 6 [H8S/2351 Only]: In modes 2 and 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Port C pin functions in modes 2 and 6 are shown in figure 9-17. When PCDDR = 1 A7 (output) A6 (output) A5 (output) Port C A4 (output) A3 (output) A2 (output) A1 (output) A0 (output) When PCDDR = 0 PC7 (input) PC6 (input) PC5 (input) PC4 (input) PC3 (input) PC2 (input) PC1 (input) PC0 (input) Figure 9-17 Port C Pin Functions (Modes 2 and 6) Modes 3 and 7 [H8S/2351 Only]: In modes 3 and 7, port C pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port. Port C pin functions in modes 3 and 7 are shown in figure 9-18. PC7 (I/O) PC6 (I/O) PC5 (I/O) Port C PC4 (I/O) PC3 (I/O) PC2 (I/O) PC1 (I/O) PC0 (I/O) Figure 9-18 Port C Pin Functions (Modes 3 and 7) 373 9.10.4 MOS Input Pull-Up Function [H8S/2351 Only] Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 2, 3, 6, and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 2, 3, 6, or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-18 summarizes the MOS input pull-up states. Table 9-18 MOS Input Pull-Up States (Port C) Modes 1, 4, 5 2, 3, 6, 7 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode OFF ON/OFF In Other Operations Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PCDDR = 0 and PCPCR = 1; otherwise off. 374 9.11 9.11.1 Port D Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. However, in the H8S/2350, port D pins function only as data bus pins. Port D has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Figure 9-19 shows the port D pin configuration. Port D pins PD7 / D15 PD6 / D14 PD5 / D13 Port D PD4 / D12 PD3 / D11 PD2 / D10 PD1 / D9 PD0 / D8 Pin functions in modes 1, 2, 4, 5, and 6* D15 (I/O) D14 (I/O) D13 (I/O) D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Pin functions in modes 3 and 7* PD7 (I/O) PD6 (I/O) PD5 (I/O) PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-19 Port D Pin Functions 375 9.11.2 Register Configuration [H8S/2351 Only] Table 9-19 shows the port D register configuration. Table 9-19 Port D Registers Name Port D data direction register Port D data register Port D register Port D MOS pull-up control register Note: * Lower 16 bits of the address. Abbreviation PDDDR PDDR PORTD PDPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address * H'FEBC H'FF6C H'FF5C H'FF73 Port D Data Direction Register (PDDDR) [H8S/2351 Only] Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : R/W : PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port D. PDDDR cannot be read; if it is, an undefined value will be read.. PDDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. * Modes 1, 2, 4, 5, and 6 The input/output direction specification by PDDDR is ignored, and port D is automatically designated for data I/O. * Modes 3 and 7 Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. 376 Port D Data Register (PDDR) [H8S/2351 Only] Bit : 7 PD7DR Initial value : R/W : 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 PD2DR 0 R/W 1 0 R/W 0 0 R/W PD6DR PD5DR PD4DR PD3DR PD1DR PD0DR PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port D Register (PORTD) [H8S/2351 Only] Bit : 7 PD7 Initial value : R/W : --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R Note: * Determined by state of pins PD7 to PD0. PORTD is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port D pins (PD7 to PD 0) must always be performed on PDDR. If a port D read is performed while PDDDR bits are set to 1, the PDDR values are read. If a port D read is performed while PDDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTD contents are determined by the pin states, as PDDDR and PDDR are initialized. PORTD retains its prior state after a manual reset, and in software standby mode. 377 Port D MOS Pull-Up Control Register (PDPCR) [H8S/2351 Only] Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis. When a PDDDR bit is cleared to 0 (input port setting) in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PDPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 9.11.3 Pin Functions Modes 1, 4, and 5 [H8S/2351]; Modes 1, 2, 4, 5, and 6 [H8S/2351]: In modes 1, 2, 4, 5, and 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 9-20. D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Figure 9-20 Port D Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7 [H8S/2351 Only]: In modes 3 and 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis. Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port. 378 Port D pin functions in modes 3 and 7 are shown in figure 9-21. PD7 (I/O) PD6 (I/O) PD5 (I/O) Port D PD4 (I/O) PD3 (I/O) PD2 (I/O) PD1 (I/O) PD0 (I/O) Figure 9-21 Port D Pin Functions (Modes 3 and 7) 9.11.4 MOS Input Pull-Up Function [H8S/2351 Only] Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 3 and 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 3 or 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-20 summarizes the MOS input pull-up states. Table 9-20 MOS Input Pull-Up States (Port D) Modes 1, 2, 4 to 6 3, 7 Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode OFF ON/OFF In Other Operations Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PDDDR = 0 and PDPCR = 1; otherwise off. 379 9.12 9.12.1 Port E Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software (H8S/2351 only). Figure 9-22 shows the port E pin configuration. Port E pins PE7 / D7 PE6 / D6 PE5 / D5 Port E PE4 / D4 PE3 / D3 PE2 / D2 PE1 / D1 PE0 / D0 Pin functions in modes 1, 2, 4, 5, and 6* PE7 (I/O)/ D7 (I/O) PE6 (I/O)/ D6 (I/O) PE5 (I/O)/ D5 (I/O) PE4 (I/O)/ D4 (I/O) PE3 (I/O)/ D3 (I/O) PE2 (I/O)/ D2 (I/O) PE1 (I/O)/ D1 (I/O) PE0 (I/O)/ D0 (I/O) Pin functions in modes 3 and 7* PE7 (I/O) PE6 (I/O) PE5 (I/O) PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-22 Port E Pin Functions 380 9.12.2 Register Configuration Table 9-21 shows the port E register configuration. Table 9-21 Port E Registers Name Port E data direction register Port E data register Port E register Port E MOS pull-up control register* 2 Abbreviation PEDDR PEDR PORTE PEPCR R/W W R/W R R/W Initial Value H'00 H'00 Undefined H'00 Address* 1 H'FEBD H'FF6D H'FF5D H'FF74 Notes: 1. Lower 16 bits of the address. 2. Only applies to the H8S/2351. Port E Data Direction Register (PEDDR) Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : R/W : PEDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port E. PEDDR cannot be read; if it is, an undefined value will be read. PEDDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. * Modes 1, 4, 5 [H8S/2350]; modes 1, 2, 4, 5, and 6 [H8S/2351] When 8-bit bus mode has been selected, port E pins function as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode has been selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. For details of 8-bit and 16-bit bus modes, see section 6, Bus Controller. * Modes 3 and 7 [H8S/2351 only] Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. 381 Port E Data Register (PEDR) Bit : 7 PE7DR Initial value : R/W : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 PE4DR 0 R/W 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W 0 PE0DR 0 R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port E Register (PORTE) Bit : 7 PE7 Initial value : R/W : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R 0 PE0 --* R Note: * Determined by state of pins PE7 to PE0. PORTE is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port E pins (PE7 to PE0) must always be performed on PEDR. If a port E read is performed while PEDDR bits are set to 1, the PEDR values are read. If a port E read is performed while PEDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTE contents are determined by the pin states, as PEDDR and PEDR are initialized. PORTE retains its prior state after a manual reset, and in software standby mode. Port E MOS Pull-Up Control Register (PEPCR) [H8S/2351 Only] Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis. 382 When a PEDDR bit is cleared to 0 (input port setting) when 8-bit bus mode is selected in mode 1, 2, 4, 5, or 6, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for the corresponding pin. PEPCR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. 9.12.3 Pin Functions Modes 1, 4, and 5 [H8S/2350]; Modes 1, 2, 4, 5, and 6 [H8S/2351]: In modes 1, 2, 4, 5, and 6, when 8-bit access is designated and 8-bit bus mode is selected, port E pins are automatically designated as I/O ports. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. When 16-bit bus mode is selected, the input/output direction specification by PEDDR is ignored, and port E is designated for data I/O. Port E pin functions in modes 1, 2, 4, 5, and 6 are shown in figure 9-23. 8-bit bus mode PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) 16-bit bus mode D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Figure 9-23 Port E Pin Functions (Modes 1, 2, 4, 5, and 6) Modes 3 and 7 [H8S/2351 Only]: In modes 3 and 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis. Setting a PEDDR bit to 1 makes the corresponding port E pin an output port, while clearing the bit to 0 makes the pin an input port. 383 Port E pin functions in modes 3 and 7 are shown in figure 9-24. PE7 (I/O) PE6 (I/O) PE5 (I/O) Port E PE4 (I/O) PE3 (I/O) PE2 (I/O) PE1 (I/O) PE0 (I/O) Figure 9-24 Port E Pin Functions (Modes 3 and 7) 9.12.4 MOS Input Pull-Up Function [H8S/2351 Only] Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 1, 2, 4, 5, and 6 when 8-bit bus mode is selected, or in mode 3 or 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 1, 2, 4, 5, or 6 when 8-bit bus mode is selected, or in mode 3 or 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a power-on reset, and in hardware standby mode. The prior state is retained after a manual reset, and in software standby mode. Table 9-22 summarizes the MOS input pull-up states. Table 9-22 MOS Input Pull-Up States (Port E) Modes 3, 7 1, 2, 4 to 6 8-bit bus 16-bit bus OFF Power-On Hardware Reset Standby Mode OFF Manual Software Reset Standby Mode ON/OFF In Other Operations Legend: OFF : MOS input pull-up is always off. ON/OFF : On when PEDDR = 0 and PEPCR = 1; otherwise off. 384 9.13 9.13.1 Port F Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (o) output pin. Figure 9-25 shows the port F pin configuration. Port F pins PF7 /o PF6 /AS PF5 /RD Port F PF4 /HWR PF3 /LWR PF2 /LCAS/ WAIT / BREQO PF1 /BACK PF0 /BREQ Pin functions in modes 1 and 2* PF7 (input) / o (output) AS (output) RD (output) HWR (output) LWR (output) PF2 (I/O)/ WAIT (input) /BREQO (output) PF1 (I/O)/ BACK (output) PF0 (I/O)/ BREQ (input) Pin functions in modes 3 and 7* PF7 (input)/ o (output) PF6 (I/O) PF5 (I/O) PF4 (I/O) PF3 (I/O) PF2 (I/O) PF1 (I/O) PF0 (I/O) Pin functions in modes 4 to 6* PF7 (input) / o (output) AS (output) RD (output) HWR (output) LWR (output) PF2 (I/O)/ LCAS (output) / WAIT (input) / BREQO (output) PF1 (I/O)/ BACK (output) PF0 (I/O)/ BREQ (input) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-25 Port F Pin Functions 385 9.13.2 Register Configuration Table 9-23 shows the port F register configuration. Table 9-23 Port F Registers Name Port F data direction register Port F data register Port F register Abbreviation PFDDR PFDR PORTF R/W W R/W R Initial Value H'80/H'00* 2 H'00 Undefined Address * 1 H'FEBE H'FF6E H'FF5E Notes: 1. Lower 16 bits of the address. 2. Initial value depends on the mode. Port F Data Direction Register (PFDDR) Bit : 7 6 5 4 3 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4, 5, 6 Initial value : R/W : Modes 3 and 7 Initial value : R/W : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W PFDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port F. PFDDR cannot be read; if it is, an undefined value will be read. PFDDR is initialized by a power-on reset, and in hardware standby mode, to H'80 in modes 1, 2, 4, 5, and 6, and to H'00 in modes 3 and 7. It retains its prior state after a manual reset, and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Modes 1, 4, and 5 [H8S/2350]; modes 1, 2, 4, 5, and 6 [H8S/2351] Pin PF7 functions as the o output pin when the corresponding PFDDR bit is set to 1, and as an input port when the bit is cleared to 0. The input/output direction specified by PFDDR is ignored for pins PF6 to PF3, which are automatically designated as bus control outputs (AS, RD, HWR, and LWR). 386 Pins PF2 to PF0 are designated as bus control input/output pins (LCAS, WAIT, BREQO, BACK, BREQ) by means of bus controller settings. At other times, setting a PFDDR bit to 1 makes the corresponding port F pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 3 and 7 [H8S/2351 only] Setting a PFDDR bit to 1 makes the corresponding port F pin PF6 to PF0 an output port, or in the case of pin PF 7, the o output pin. Clearing the bit to 0 makes the pin an input port. Port F Data Register (PFDR) Bit : 7 PF7DR Initial value : R/W : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 PF4DR 0 R/W 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W 0 PF0DR 0 R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port F Register (PORTF) Bit : 7 PF7 Initial value : R/W : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R 0 PF0 --* R Note: * Determined by state of pins PF7 to PF0. PORTF is an 8-bit read-only register that shows the pin states. Writing of output data for the port F pins (PF 7 to PF0) must always be performed on PFDR. If a port F read is performed while PFDDR bits are set to 1, the PFDR values are read. If a port F read is performed while PFDDR bits are cleared to 0, the pin states are read. After a power-on reset and in hardware standby mode, PORTF contents are determined by the pin states, as PFDDR and PFDR are initialized. PORTF retains its prior state after a manual reset, and in software standby mode. 387 9.13.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS, WAIT, BREQO, BREQ, and BACK) and the system clock (o) output pin. The pin functions differ between modes 1, 2, 4, 5, and 6, and modes 3 and 7. Port F pin functions are shown in table 9-24. Table 9-24 Port F Pin Functions Pin PF 7/o Selection Method and Pin Functions The pin function is switched as shown below according to bit PF7DDR. PF7DDR Pin function 0 PF 7 input pin 1 o output pin PF 6/AS The pin function is switched as shown below according to the operating mode and bit PF6DDR. Operating Mode PF6DDR Pin function Modes 1, 2, 4, 5, 6* -- AS output pin 0 PF 6 input pin Modes 3 and 7* 1 PF 6 output pin PF 5/RD The pin function is switched as shown below according to the operating mode and bit PF5DDR. Operating Mode PF5DDR Pin function Modes 1, 2, 4, 5, 6* -- RD output pin 0 PF 5 input pin Modes 3 and 7* 1 PF 5 output pin PF 4/HWR The pin function is switched as shown below according to the operating mode and bit PF4DDR. Operating Mode PF4DDR Pin function Modes 1, 2, 4, 5, 6* -- HWR output pin 0 PF 4 input pin Modes 3 and 7* 1 PF 4 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 388 Table 9-24 Port F Pin Functions (cont) Pin PF 3/LWR Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PF3DDR. Operating Mode PF3DDR Pin function PF 2/LCAS/WAIT/ BREQO Modes 1, 2, 4, 5, 6* -- LWR output pin 0 PF 3 input pin Modes 3 and 7* 1 PF 3 output pin The pin function is switched as shown below according to the combination of the operating mode, and bits RMTS2 to RMTS0, LCASS, BREQOE, WAITE, ABW5 to ABW2, and PF2DDR. Operating Mode LCASS BREQOE WAITE PF2DDR Pin function 0 PF 2 input pin 0 1 PF 2 output pin 0 1 -- Modes 1, 2, 4, 5, 6* 0 1 -- -- 1* -- -- -- 0 PF 2 input pin Modes 3 and 7* -- -- -- 1 PF 2 output pin WAIT BREQO LCAS input output output pin pin pin Note: 1. Only in DRAM space 16-bit access in modes 4 to 6 when RMTS2 to RMTS0 = B'001 to B'011. PF 1/BACK The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF1DDR. Operating Mode BRLE PF1DDR Pin function 0 PF 1 input pin Modes 1, 2, 4, 5, 6* 0 1 PF 1 output pin 1 -- BACK output pin 0 PF 1 input pin Modes 3 and 7* -- 1 PF 1 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 389 Table 9-24 Port F Pin Functions (cont) Pin PF 0/BREQ Selection Method and Pin Functions The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode BRLE PF0DDR Pin function 0 PF 0 input pin Modes 1, 2, 4, 5, 6* 0 1 PF 0 output pin 1 -- BREQ input pin 0 PF 0 input pin Modes 3 and 7* -- 1 PF 0 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 390 9.14 9.14.1 Port G Overview Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). Figure 9-26 shows the port G pin configuration. Port G pins Pin functions in modes 1 and 2* PG4 / CS0 PG3 / CS1 Port G PG2 / CS2 PG1 / CS3 PG0 / CAS PG4 (input)/CS0 (output) PG3 (I/O) PG2 (I/O) PG1 (I/O) PG0 (I/O) Pin functions in modes 3 and 7* Pin functions in modes 4 to 6* PG4 (I/O) PG3 (I/O) PG2 (I/O) PG1 (I/O) PG0 (I/O) PG4 (input)/CS0 (output) PG3 (input)/CS1 (output) PG2 (input)/CS2 (output) PG1 (input)/CS3 (output) PG0 (I/O)/CAS (output) Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure 9-26 Port G Pin Functions 391 9.14.2 Register Configuration Table 9-25 shows the port G register configuration. Table 9-25 Port G Registers Name Port G data direction register Port G data register Port G register Abbreviation PGDDR PGDR PORTG R/W W R/W R Initial Value* 2 H'10/H'00* 3 H'00 Undefined Address* 1 H'FEBF H'FF6F H'FF5F Notes: 1. Lower 16 bits of the address. 2. Value of bits 4 to 0. 3. Initial value depends on the mode. Port G Data Direction Register (PGDDR) Bit : 7 -- Modes 1, 4, 5 Initial value : R/W : Modes 2, 3, 6, 7 Initial value : R/W : Undefined Undefined Undefined -- -- -- 0 W 0 W 0 W 0 W 0 W Undefined Undefined Undefined -- -- -- 1 W 0 W 0 W 0 W 0 W 6 -- 5 -- 4 3 2 1 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR PGDDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port G. PGDDR cannot be read, and bits 7 to 5 are reserved. If PGDDR is read, an undefined value will be read. The PG4DDR bit is initialized by a power-on reset and in hardware standby mode, to 1 in modes 1, 4, and 5, and to 0 in modes 2, 3, 6, and 7. It retains its prior state after a manual reset and in software standby mode. The OPE bit in SBYCR is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. * Mode 1 [H8S/2350]; modes 1 and 2 [H8S/2351] Pin PG 4 functions as a bus control output pin (CS0) when the corresponding PGDDR bit is set to 1, and as an input port when the bit is cleared to 0. For pins PG3 to PG0, setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. 392 * Modes 3 and 7 [H8S/2351 only] Setting a PGDDR bit to 1 makes the corresponding port G pin an output port, while clearing the bit to 0 makes the pin an input port. * Modes 4 and 5 [H8S/2350]; modes 4, 5, and 6 [H8S/2351] Pins PG 4 to PG 1 function as bus control output pins (CS0 to CS3) when the corresponding PGDDR bits are set to 1, and as input ports when the bits are cleared to 0. Pin PG 0 functions as the CAS output pin when DRAM interface is designated. Otherwise, setting the corresponding PGDDR bit to 1 makes the pin an output port, while clearing the bit to 0 makes the pin an input port. For details of the DRAM interfaces, see section 6, Bus Controller. Port G Data Register (PGDR) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Undefined Undefined Undefined PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a power-on reset, and in hardware standby mode. It retains its prior state after a manual reset, and in software standby mode. Port G Register (PORTG) Bit : 7 -- Initial value : R/W : -- 6 -- -- 5 -- -- 4 PG4 --* R 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R 0 PG0 --* R Undefined Undefined Undefined Note: * Determined by state of pins PG4 to PG0. PORTG is an 8-bit read-only register that shows the pin states. It cannot be written to. Writing of output data for the port G pins (PG4 to PG 0) must always be performed on PGDR. Bits 7 to 5 are reserved; they return an undetermined value if read, and cannot be modified. If a port G read is performed while PGDDR bits are set to 1, the PGDR values are read. If a port G read is performed while PGDDR bits are cleared to 0, the pin states are read. 393 After a power-on reset and in hardware standby mode, PORTG contents are determined by the pin states, as PGDDR and PGDR are initialized. PORTG retains its prior state after a manual reset, and in software standby mode. 9.14.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS). The pin functions are different in modes 1 and 2, modes 3 and 7, and modes 4 to 6. Port G pin functions are shown in table 9-26. Table 9-26 Port G Pin Functions Pin PG4/CS0 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PG4DDR. Operating Mode PG4DDR Pin function Modes 1, 2, 4, 5, 6* 0 1 Modes 3 and 7* 0 1 PG4 input pin CS0 output pin PG4 input pin PG4 output pin PG3/CS1 The pin function is switched as shown below according to the operating mode and bit PG3DDR. Operating Mode PG3DDR Pin function Modes 1, 2, 3, 7* 0 1 Modes 4 to 6* 0 1 PG3 input pin PG3 output pin PG3 input pin CS1 output pin PG2/CS2 The pin function is switched as shown below according to the operating mode and bit PG2DDR. Operating Mode PG2DDR Pin function Modes 1, 2, 3, 7* 0 1 Modes 4 to 6* 0 1 PG2 input pin PG2 output pin PG2 input pin CS2 output pin Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 394 Table 9-26 Port G Pin Functions (cont) Pin PG1/CS3 Selection Method and Pin Functions The pin function is switched as shown below according to the operating mode and bit PG1DDR. Operating Mode PG1DDR Pin function Modes 1, 2, 3, 7* 0 1 Modes 4 to 6* 0 1 PG1 input pin PG1 output pin PG1 input pin CS3 output pin PG0/CAS The pin function is switched as shown below according to the combination of the operating mode and bits RMTS2 to RMTS0 and PG0DDR. Operating Mode RMTS2 to RMTS0 PG0DDR Pin function 0 PG0 input pin Modes 1, 2, 3, 7* -- 1 PG0 output pin Modes 4 to 6* B'000, B'100 to B'111 0 PG0 input pin 1 PG0 output pin B'001 to B'011 -- CAS output Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. 395 396 Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The H8S/2350 Series has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.1 Features * Maximum 16-pulse input/output A total of 16 timer general registers (TGRs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register TGRC and TGRD for channels 0 and 3 can also be used as buffer registers * Selection of 8 counter input clocks for each channel * The following operations can be set for each channel: Waveform output at compare match: Selection of 0, 1, or toggle output Input capture function: Selection of rising edge, falling edge, or both edge detection Counter clear operation: Counter clearing possible by compare match or input capture Synchronous operation: Multiple timer counters (TCNT) can be written to simultaneously Simultaneous clearing by compare match and input capture possible Register simultaneous input/output possible by counter synchronous operation PWM mode: Any PWM output duty can be set Maximum of 15-phase PWM output possible by combination with synchronous operation * Buffer operation settable for channels 0 and 3 Input capture register double-buffering possible Automatic rewriting of output compare register possible * Phase counting mode settable independently for each of channels 1, 2, 4, and 5 Two-phase encoder pulse up/down-count possible * Cascaded operation Channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow * Fast access via internal 16-bit bus Fast access is possible via a 16-bit bus interface 397 * 26 interrupt sources For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently * Automatic transfer of register data Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (DTC) or DMA controller (DMAC) activation * Programmable pulse generator (PPG) output trigger can be generated Channel 0 to 3 compare match/input capture signals can be used as PPG output trigger * A/D converter conversion start trigger can be generated Channel 0 to 5 compare match A/input capture A signals can be used as A/D converter conversion start trigger * Module stop mode can be set As the initial setting, TPU operation is halted. Register access is enabled by exiting module stop mode. Table 10-1 lists the functions of the TPU. 398 Table 10-1 TPU Functions Item Count clock Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 o/1 o/4 o/16 o/64 TCLKA TCLKB TCLKC TCLKD TGR0A TGR0B TGR0C TGR0D TIOCA0 TIOCB0 TIOCC0 TIOCD0 TGR compare match or input capture o/1 o/4 o/16 o/64 o/256 TCLKA TCLKB TGR1A TGR1B -- TIOCA1 TIOCB1 o/1 o/4 o/16 o/64 o/1024 TCLKA TCLKB TCLKC TGR2A TGR2B -- TIOCA2 TIOCB2 o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 TCLKA TGR3A TGR3B TGR3C TGR3D TIOCA3 TIOCB3 TIOCC3 TIOCD3 TGR compare match or input capture o/1 o/4 o/16 o/64 o/1024 TCLKA TCLKC TGR4A TGR4B -- TIOCA4 TIOCB4 o/1 o/4 o/16 o/64 o/256 TCLKA TCLKC TCLKD TGR5A TGR5B -- TIOCA5 TIOCB5 General registers General registers/ buffer registers I/O pins Counter clear function TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capture Compare 0 output match 1 output output Toggle output Input capture function Synchronous operation PWM mode Phase counting mode Buffer operation Legend : Possible -- : Not possible -- -- -- -- -- -- 399 Table 10-1 TPU Functions (cont) Item Channel 0 Channel 1 Channel 2 TGR2A compare match or input capture TGR compare match or input capture TGR2A compare match or input capture TGR2A/ TGR2B compare match or input capture 4 sources Channel 3 TGR3A compare match or input capture TGR compare match or input capture TGR3A compare match or input capture Channel 4 TGR4A compare match or input capture TGR compare match or input capture TGR4A compare match or input capture Channel 5 TGR5A compare match or input capture TGR compare match or input capture TGR5A compare match or input capture -- TGR1A DMAC TGR0A compare activation compare match or match or input capture input capture DTC TGR activation compare match or input capture A/D TGR0A converter compare trigger match or input capture PPG trigger TGR0A/ TGR0B compare match or input capture 5 sources * TGR compare match or input capture TGR1A compare match or input capture TGR1A/ TGR1B compare match or input capture 4 sources -- TGR3A/ TGR3B compare match or input capture 5 sources 4 sources Compare * match or input capture 3A Compare * match or input capture 3B Compare * match or * input capture 3C Compare match or input capture 3D Overflow Interrupt sources 4 sources Compare match or input capture 5A Compare match or input capture 5B Overflow Underflow Compare * match or input capture 0A Compare * match or input capture 0B Compare * match or * input capture 0C Compare match or input capture 0D Overflow Compare * match or input capture 1A Compare * match or input capture 1B Overflow * Underflow * Compare * match or input capture 2A Compare * match or input capture 2B Overflow Underflow * Compare * match or input capture 4A Compare * match or input capture 4B Overflow * Underflow * * * * * * * Legend -- : Not possible 400 10.1.2 Block Diagram Figure 10-1 shows a block diagram of the TPU. TIORH TIORL TMDR Channel 3 TSR TGRC TGRD TGRA TGRB TCNT Control logic for channels 3 to 5 Input/output pins Channel 3: TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 Channel 4: TIOCB4 TIOCA5 Channel 5: TIOCB5 Channel 5 TGRA TIOR TMDR Channel 2 TSR Clock input Internal clock: o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 External clock: TCLKA TCLKB TCLKC TCLKD TIER TCR Module data bus TSTR TSYR Bus interface TGRB TCNT Interrupt request signals Channel 3: TGI3A TGI3B TGI3C TGI3D TCI3V Channel 4: TGI4A TGI4B TCI4V TCI4U Channel 5: TGI5A TGI5B TCI5V TCI5U TMDR Channel 4 TSR TIER TCR TGRA TIOR TMDR TSR TIER TCR TGRB TCNT Common Control logic Internal data bus A/D conversion start request signal PPG output trigger signal TGRA TIOR TIER TCR TGRB TCNT Control logic for channels 0 to 2 TIORH TIORL TMDR Input/output pins TIOCA0 Channel 0: TIOCB0 TIOCC0 TIOCD0 TIOCA1 Channel 1: TIOCB1 TIOCA2 Channel 2: TIOCB2 Interrupt request signals Channel 0: TGI0A TGI0B TGI0C TGI0D TCI0V Channel 1: TGI1A TGI1B TCI1V TCI1U Channel 2: TGI2A TGI2B TCI2V TCI2U TMDR Channel 1 TSR TGRA TIOR Channel 0 TSR TIER TCR TGRB TGRC TGRD TGRB TCNT TCNT Figure 10-1 Block Diagram of TPU TIER TCR TGRA 401 10.1.3 Pin Configuration Table 10-2 summarizes the TPU pins. Table 10-2 TPU Pins Channel All Name Clock input A Symbol TCLKA I/O Input Function External clock A input pin (Channel 1 and 5 phase counting mode A phase input) External clock B input pin (Channel 1 and 5 phase counting mode B phase input) External clock C input pin (Channel 2 and 4 phase counting mode A phase input) External clock D input pin (Channel 2 and 4 phase counting mode B phase input) TGR0A input capture input/output compare output/PWM output pin TGR0B input capture input/output compare output/PWM output pin TGR0C input capture input/output compare output/PWM output pin TGR0D input capture input/output compare output/PWM output pin TGR1A input capture input/output compare output/PWM output pin TGR1B input capture input/output compare output/PWM output pin TGR2A input capture input/output compare output/PWM output pin TGR2B input capture input/output compare output/PWM output pin Clock input B TCLKB Input Clock input C TCLKC Input Clock input D TCLKD Input 0 Input capture/out TIOCA0 compare match A0 Input capture/out TIOCB0 compare match B0 Input capture/out TIOCC0 compare match C0 Input capture/out TIOCD0 compare match D0 I/O I/O I/O I/O I/O I/O I/O I/O 1 Input capture/out TIOCA1 compare match A1 Input capture/out TIOCB1 compare match B1 2 Input capture/out TIOCA2 compare match A2 Input capture/out TIOCB2 compare match B2 402 Table 10-2 TPU Pins (cont) Channel 3 Name Symbol I/O I/O I/O I/O I/O I/O I/O I/O I/O Function TGR3A input capture input/output compare output/PWM output pin TGR3B input capture input/output compare output/PWM output pin TGR3C input capture input/output compare output/PWM output pin TGR3D input capture input/output compare output/PWM output pin TGR4A input capture input/output compare output/PWM output pin TGR4B input capture input/output compare output/PWM output pin TGR5A input capture input/output compare output/PWM output pin TGR5B input capture input/output compare output/PWM output pin Input capture/out TIOCA3 compare match A3 Input capture/out TIOCB3 compare match B3 Input capture/out TIOCC3 compare match C3 Input capture/out TIOCD3 compare match D3 4 Input capture/out TIOCA4 compare match A4 Input capture/out TIOCB4 compare match B4 5 Input capture/out TIOCA5 compare match A5 Input capture/out TIOCB5 compare match B5 403 10.1.4 Register Configuration Table 10-3 summarizes the TPU registers. Table 10-3 TPU Registers Channel Name 0 Timer control register 0 Timer mode register 0 Timer I/O control register 0H Timer I/O control register 0L Abbreviation TCR0 TMDR0 TIOR0H TIOR0L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 2 Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Address * 1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD8 H'FFDA H'FFDC H'FFDE H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE8 H'FFEA H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF8 H'FFFA Timer interrupt enable register 0 TIER0 Timer status register 0 Timer counter 0 Timer general register 0A Timer general register 0B Timer general register 0C Timer general register 0D 1 Timer control register 1 Timer mode register 1 Timer I/O control register 1 TSR0 TCNT0 TGR0A TGR0B TGR0C TGR0D TCR1 TMDR1 TIOR1 Timer interrupt enable register 1 TIER1 Timer status register 1 Timer counter 1 Timer general register 1A Timer general register 1B 2 Timer control register 2 Timer mode register 2 Timer I/O control register 2 TSR1 TCNT1 TGR1A TGR1B TCR2 TMDR2 TIOR2 R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W 2 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Timer interrupt enable register 2 TIER2 Timer status register 2 Timer counter 2 Timer general register 2A Timer general register 2B TSR2 TCNT2 TGR2A TGR2B R/(W) * H'C0 R/W R/W R/W H'0000 H'FFFF H'FFFF 404 Table 10-3 TPU Registers (cont) Channel Name 3 Timer control register 3 Timer mode register 3 Timer I/O control register 3H Timer I/O control register 3L Abbreviation TCR3 TMDR3 TIOR3H TIOR3L R/W R/W R/W R/W R/W R/W R/(W)* R/W R/W R/W R/W R/W R/W R/W R/W R/W 2 2 Initial Value H'00 H'C0 H'00 H'00 H'40 H'C0 H'0000 H'FFFF H'FFFF H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Address* 1 H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE88 H'FE8A H'FE8C H'FE8E H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE98 H'FE9A H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA8 H'FEAA H'FFC0 H'FFC1 H'FF3C Timer interrupt enable register 3 TIER3 Timer status register 3 Timer counter 3 Timer general register 3A Timer general register 3B Timer general register 3C Timer general register 3D 4 Timer control register 4 Timer mode register 4 Timer I/O control register 4 TSR3 TCNT3 TGR3A TGR3B TGR3C TGR3D TCR4 TMDR4 TIOR4 Timer interrupt enable register 4 TIER4 Timer status register 4 Timer counter 4 Timer general register 4A Timer general register 4B 5 Timer control register 5 Timer mode register 5 Timer I/O control register 5 TSR4 TCNT4 TGR4A TGR4B TCR5 TMDR5 TIOR5 R/(W) * H'C0 R/W R/W R/W R/W R/W R/W R/W 2 H'0000 H'FFFF H'FFFF H'00 H'C0 H'00 H'40 Timer interrupt enable register 5 TIER5 Timer status register 5 Timer counter 5 Timer general register 5A Timer general register 5B All Timer start register Timer synchro register Module stop control register TSR5 TCNT5 TGR5A TGR5B TSTR TSYR MSTPCR R/(W) * H'C0 R/W R/W R/W R/W R/W R/W H'0000 H'FFFF H'FFFF H'00 H'00 H'3FFF Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 405 10.2 10.2.1 Register Descriptions Timer Control Register (TCR) Channel 0: TCR0 Channel 3: TCR3 Bit : 7 CCLR2 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Initial value : R/W : Channel 1: TCR1 Channel 2: TCR2 Channel 4: TCR4 Channel 5: TCR5 Bit : 7 -- 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 Initial value : R/W : The TCR registers are 8-bit registers that control the TCNT channels. The TPU has six TCR registers, one for each of channels 0 to 5. The TCR registers are initialized to H'00 by a reset, and in hardware standby mode. TCR register settings should be made only when TCNT operation is stopped. 406 Bits 7, 6, 5--Counter Clear 2, 1, and 0 (CCLR2, CCLR1, CCLR0): These bits select the TCNT counter clearing source. Channel 0, 3 Bit 7 CCLR2 0 Bit 6 CCLR1 0 Bit 5 CCLR0 0 1 1 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture * 2 TCNT cleared by TGRD compare match/input capture * 2 TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 1 1 0 1 Channel 1, 2, 4, 5 Bit 6 Bit 7 Reserved* 3 CCLR1 0 0 Bit 5 CCLR0 0 1 Description TCNT clearing disabled (Initial value) TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be modified. 407 Bits 4 and 3--Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. o/4 both edges = o/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. Bit 4 CKEG1 0 Bit 3 CKEG0 0 1 1 -- Description Count at rising edge Count at falling edge Count at both edges (Initial value) Note: Internal clock edge selection is valid when the input clock is o/4 or slower. This setting is ignored if the input clock is o/1, or when overflow/underflow of another channel is selected. Bits 2, 1, and 0--Time Prescaler 2, 1, and 0 (TPSC2 to TPSC0): These bits select the TCNT counter clock. The clock source can be selected independently for each channel. Table 10-4 shows the clock sources that can be set for each channel. Table 10-4 TPU Clock Sources Overflow/ Underflow on Another Internal Clock Channel 0 1 2 3 4 5 o/1 o/4 o/16 o/64 o/256 o/1024 o/4096 External Clock TCLKA TCLKB TCLKC TCLKD Channel Legend : Setting Blank : No setting 408 Channel 0 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input (Initial value) 1 0 1 1 0 0 1 1 0 1 Channel 1 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on o/256 Counts on TCNT2 overflow/underflow (Initial value) 1 0 1 1 0 0 1 1 0 1 Note: This setting is ignored when channel 1 is in phase counting mode. Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Channel 2 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 (Initial value) Note: This setting is ignored when channel 2 is in phase counting mode. 409 Channel 3 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input Internal clock: counts on o/1024 Internal clock: counts on o/256 Internal clock: counts on o/4096 (Initial value) 1 0 1 1 0 0 1 1 0 1 Channel 4 Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 Counts on TCNT5 overflow/underflow (Initial value) 1 0 1 1 0 0 1 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. Bit 2 TPSC2 0 Bit 1 TPSC1 0 Bit 0 TPSC0 0 1 1 0 1 1 0 0 1 1 0 1 Channel 5 Description Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/256 External clock: counts on TCLKD pin input (Initial value) Note: This setting is ignored when channel 5 is in phase counting mode. 410 10.2.2 Timer Mode Register (TMDR) Channel 0: TMDR0 Channel 3: TMDR3 Bit : 7 -- 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Initial value : R/W : Channel 1: TMDR1 Channel 2: TMDR2 Channel 4: TMDR4 Channel 5: TMDR5 Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W Initial value : R/W : The TMDR registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. The TPU has six TMDR registers, one for each channel. The TMDR registers are initialized to H'C0 by a reset, and in hardware standby mode. TMDR register settings should be made only when TCNT operation is stopped. Bits 7 and 6--Reserved: Read-only bits, always read as 1. Bit 5--Buffer Operation B (BFB): Specifies whether TGRB is to operate in the normal way, or TGRB and TGRD are to be used together for buffer operation. When TGRD is used as a buffer register, TGRD input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRD, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 BFB 0 1 Description TGRB operates normally TGRB and TGRD used together for buffer operation 411 (Initial value) Bit 4--Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified. Bit 4 BFA 0 1 Description TGRA operates normally TGRA and TGRC used together for buffer operation (Initial value) Bits 3 to 0--Modes 3 to 0 (MD3 to MD0): These bits are used to set the timer operating mode. Bit 3 MD3* 1 0 Bit 2 MD2* 2 0 Bit 1 MD1 0 Bit 0 MD0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Description Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- (Initial value) *: Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. 412 10.2.3 Timer I/O Control Register (TIOR) Channel 0: TIOR0H Channel 1: TIOR1 Channel 2: TIOR2 Channel 3: TIOR3H Channel 4: TIOR4 Channel 5: TIOR5 Bit : 7 IOB3 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W 1 IOA1 0 R/W 0 IOA0 0 R/W Initial value : R/W : Channel 0: TIOR0L Channel 3: TIOR3L Bit : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W 1 IOC1 0 R/W 0 IOC0 0 R/W Initial value : R/W : Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. The TIOR registers are 8-bit registers that control the TGR registers. The TPU has eight TIOR registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. The TIOR registers are initialized to H'00 by a reset, and in hardware standby mode. Care is required since TIOR is affected by the TMDR setting. The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is cleared to 0 is specified. 413 Bits 7 to 4-- I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD. Channel 0 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0B is Capture input source is input TIOCB0 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count- up/count-down* 1 1/count clock Note: *: Don't care 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 414 Channel 0 Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is Capture input input source is capture TIOCD0 pin register* 2 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0D is Output disabled output Initial output is 0 compare output register* 2 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count-up/count-down* 1 1/count clock *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000 and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 415 Channel 1 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is Capture input source is input TIOCB1 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at generation of Capture input source is TGR0C TGR0C compare match/input compare match/ capture input capture *: Don't care Channel 2 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is Capture input source is input TIOCB2 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 416 Channel 3 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is Capture input source is input TIOCB3 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 source is channel count-up/count-down* 1 4/count clock Note: *: Don't care 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 417 Channel 3 Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR3D is Capture input input source is capture TIOCD3 pin register* 2 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3D is Output disabled output Initial output is 0 compare output register* 2 (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 source is channel count-up/count-down* 1 4/count clock *: Don't care Notes: 1. When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. 2. When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 418 Channel 4 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR4B is Capture input source is input TIOCB4 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR4B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at generation of Capture input source is TGR3C TGR3C compare match/ compare match/ input capture input capture *: Don't care Channel 5 Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is Capture input source is input TIOCB5 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR5B is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 419 Bits 3 to 0-- I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC. Channel 0 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0A is Capture input source is input TIOCA0 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count-up/count-down 1/ count clock *: Don't care 420 Channel 0 Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is Capture input input source is capture TIOCC0 pin register* 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR0C is Output disabled output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT1 source is channel count-up/count-down 1/count clock Note: *: Don't care 1. When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 421 Channel 1 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is Capture input source is input TIOCA1 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR1A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at generation of Capture input source is TGR0A channel 0/TGR0A compare compare match/ match/input capture input capture *: Don't care Channel 2 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2A is Capture input source is input TIOCA2 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR2A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 422 Channel 3 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is Capture input source is input TIOCA3 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock *: Don't care 423 Channel 3 Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3C is Capture input input source is capture TIOCC3 pin register* 1 Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR3C is Output disabled output Initial output is 0 compare output 1 register* (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at TCNT4 source is channel count-up/count-down 4/count clock Note: *: Don't care 1. When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 424 Channel 4 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 1 0 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is Capture input source is input TIOCA4 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges TGR4A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at generation of Capture input source is TGR3A TGR3A compare match/input compare match/ capture input capture *: Don't care Channel 5 Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 Description 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5A is Capture input source is input TIOCA5 pin capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges *: Don't care TGR5A is Output disabled output Initial output is 0 compare output register (Initial value) 0 output at compare match 1 output at compare match Toggle output at compare match 425 10.2.4 Timer Interrupt Enable Register (TIER) Channel 0: TIER0 Channel 3: TIER3 Bit : 7 TTGE 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W Initial value : R/W : Channel 1: TIER1 Channel 2: TIER2 Channel 4: TIER4 Channel 5: TIER5 Bit : 7 TTGE 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W Initial value : R/W : The TIER registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. The TPU has six TIER registers, one for each channel. The TIER registers are initialized to H'40 by a reset, and in hardware standby mode. 426 Bit 7--A/D Conversion Start Request Enable (TTGE): Enables or disables generation of A/D conversion start requests by TGRA input capture/compare match. Bit 7 TTGE 0 1 Description A/D conversion start request generation disabled A/D conversion start request generation enabled (Initial value) Bit 6--Reserved: Read-only bit, always read as 1. Bit 5--Underflow Interrupt Enable (TCIEU): Enables or disables interrupt requests (TCIU) by the TCFU flag when the TCFU flag in TSR is set to 1 in channels 1 and 2. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCIEU 0 1 Description Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled (Initial value) Bit 4--Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV flag when the TCFV flag in TSR is set to 1. Bit 4 TCIEV 0 1 Description Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled (Initial value) Bit 3--TGR Interrupt Enable D (TGIED): Enables or disables interrupt requests (TGID) by the TGFD bit when the TGFD bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGIED 0 1 Description Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled (Initial value) 427 Bit 2--TGR Interrupt Enable C (TGIEC): Enables or disables interrupt requests (TGIC) by the TGFC bit when the TGFC bit in TSR is set to 1 in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGIEC 0 1 Description Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled (Initial value) Bit 1--TGR Interrupt Enable B (TGIEB): Enables or disables interrupt requests (TGIB) by the TGFB bit when the TGFB bit in TSR is set to 1. Bit 1 TGIEB 0 1 Description Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled (Initial value) Bit 0--TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA 0 1 Description Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled (Initial value) 428 10.2.5 Timer Status Register (TSR) Channel 0: TSR0 Channel 3: TSR3 Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Initial value : R/W : Note: * Can only be written with 0 for flag clearing. Channel 1: TSR1 Channel 2: TSR2 Channel 4: TSR4 Channel 5: TSR5 Bit : 7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* Initial value : R/W : Note: * Can only be written with 0 for flag clearing. The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset, and in hardware standby mode. 429 Bit 7--Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified. Bit 7 TCFD 0 1 Description TCNT counts down TCNT counts up (Initial value) Bit 6--Reserved: Read-only bit, always read as 1. Bit 5--Underflow Flag (TCFU): Status flag that indicates that TCNT underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. In channels 0 and 3, bit 5 is reserved. It is always read as 0 and cannot be modified. Bit 5 TCFU 0 1 Description [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting condition] When the TCNT value underflows (changes from H'0000 to H'FFFF) (Initial value) Bit 4--Overflow Flag (TCFV): Status flag that indicates that TCNT overflow has occurred. Bit 4 TCFV 0 Description [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) (Initial value) 430 Bit 3--Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified. Bit 3 TGFD 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] When TCNT = TGRD while TGRD is functioning as output compare register When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register Bit 2--Input Capture/Output Compare Flag C (TGFC): Status flag that indicates the occurrence of TGRC input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 2 is reserved. It is always read as 0 and cannot be modified. Bit 2 TGFC 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] When TCNT = TGRC while TGRC is functioning as output compare register When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 431 Bit 1--Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match. Bit 1 TGFB 0 Description [Clearing conditions] * * 1 * * (Initial value) When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] When TCNT = TGRB while TGRB is functioning as output compare register When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register Bit 0--Input Capture/Output Compare Flag A (TGFA): Status flag that indicates the occurrence of TGRA input capture or compare match. Bit 0 TGFA 0 Description [Clearing conditions] * * * 1 * * (Initial value) When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] When TCNT = TGRA while TGRA is functioning as output compare register When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 432 10.2.6 Timer Counter (TCNT) Channel 0: TCNT0 (up-counter) Channel 1: TCNT1 (up/down-counter*) Channel 2: TCNT2 (up/down-counter*) Channel 3: TCNT3 (up-counter) Channel 4: TCNT4 (up/down-counter*) Channel 5: TCNT5 (up/down-counter*) Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Note : * These counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. In other cases they function as up-counters. The TCNT registers are 16-bit counters. The TPU has six TCNT counters, one for each channel. The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode. The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. 433 10.2.7 Bit Timer General Register (TGR) : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for operation as buffer registers*. The TGR registers are initialized to H'FFFF by a reset, and in hardware standby mode. The TGR registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. Note: * TGR buffer register combinations are TGRA--TGRC and TGRB--TGRD. 434 10.2.8 Bit Timer Start Register (TSTR) : 7 -- 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W Initial value : R/W : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Counter Start 5 to 0 (CST5 to CST0): These bits select operation or stoppage for TCNT. Bit n CSTn 0 1 Description TCNTn count operation is stopped TCNTn performs count operation (Initial value) n = 5 to 0 Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. 435 10.2.9 Bit Timer Synchro Register (TSYR) : 7 -- 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W Initial value : R/W : TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 5 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1. TSYR is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 and 6--Reserved: Should always be written with 0. Bits 5 to 0--Timer Synchro 5 to 0 (SYNC5 to SYNC0): These bits select whether operation is independent of or synchronized with other channels. When synchronous operation is selected, synchronous presetting of multiple channels*1, and synchronous clearing through counter clearing on another channel* 2 are possible. Bit n SYNCn 0 1 Description TCNTn operates independently (TCNT presetting/clearing is unrelated to other channels) (Initial value) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible n = 5 to 0 Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 436 10.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP13 bit in MSTPCR is set to 1, TPU operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 13--Module Stop (MSTP13): Specifies the TPU module stop mode. Bit 13 MSTP13 0 1 Description TPU module stop mode cleared TPU module stop mode set (Initial value) 437 10.3 10.3.1 Interface to Bus Master 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10-2. Internal data bus H Bus master Module data bus L Bus interface TCNTH TCNTL Figure 10-2 16-Bit Register Access Operation [Bus Master TCNT (16 Bits)] 10.3.2 8-Bit Registers Registers other than TCNT and TGR are 8-bit. As the data bus to the CPU is 16 bits wide, these registers can be read and written to in 16-bit units. They can also be read and written to in 8-bit units. 438 Examples of 8-bit register access operation are shown in figures 10-3, 10-4, and 10-5. Internal data bus H Bus master Module data bus L Bus interface TCR Figure 10-3 8-Bit Register Access Operation [Bus Master TCR (Upper 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TMDR Figure 10-4 8-Bit Register Access Operation [Bus Master TMDR (Lower 8 Bits)] Internal data bus H Bus master Module data bus L Bus interface TCR TMDR Figure 10-5 8-Bit Register Access Operation [Bus Master TCR and TMDR (16 Bits)] 439 10.4 10.4.1 Operation Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register. Synchronous Operation: When synchronous operation is designated for a channel, TCNT for that channel performs synchronous presetting. That is, when TCNT for a channel designated for synchronous operation is rewritten, the TCNT counters for the other channels are also rewritten at the same time. Synchronous clearing of the TCNT counters is also possible by setting the timer synchronization bits in TSYR for channels designated for synchronous operation. Buffer Operation * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the relevant channel is transferred to TGR. * When TGR is an input capture register When input capture occurs, the value in TCNT is transfer to TGR and the value previously held in TGR is transferred to the buffer register. Cascaded Operation: The channel 1 counter (TCNT1), channel 2 counter (TCNT2), channel 4 counter (TCNT4), and channel 5 counter (TCNT5) can be connected together to operate as a 32bit counter. PWM Mode: In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM waveform with a duty of between 0% and 100% can be output, according to the setting of each TGR register. Phase Counting Mode: In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. When phase counting mode is set, the corresponding TCLK pin functions as the clock pin, and TCNT performs up- or down-counting. This can be used for two-phase encoder pulse input. 440 10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. * Example of count operation setting procedure Figure 10-6 shows an example of the count operation setting procedure. Operation selection Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. Free-running counter [2] For periodic counter operation, select the TGR to be used as the TCNT clearing source with bits CCLR2 to CCLR0 in TCR. [3] Designate the TGR selected in [2] as an output compare register by means of TIOR. [4] Set the periodic counter cycle in the TGR selected in [2]. Start count operation Periodic counter Select counter clearing source [2] Select output compare register [3] Set period [4] Start count operation [5] Figure 10-6 Example of Counter Operation Setting Procedure 441 * Free-running count operation and periodic count operation Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again from H'0000. Figure 10-7 illustrates free-running counter operation. TCNT value H'FFFF H'0000 Time CST bit TCFV Figure 10-7 Free-Running Counter Operation When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant channel performs periodic count operation. The TGR register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000. If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an interrupt. After a compare match, TCNT starts counting up again from H'0000. 442 Figure 10-8 illustrates periodic counter operation. Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC/DMAC activation TGF Figure 10-8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. * Example of setting procedure for waveform output by compare match Figure 10-9 shows an example of the setting procedure for waveform output by compare match [1] Select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of TIOR. The set initial value is output at the TIOC pin until the first compare match occurs. [2] Set the timing for compare match generation in TGR. Set output timing [2] Output selection Select waveform output mode [1] [3] Set the CST bit in TSTR to 1 to start the count operation. Start count operation [3] Figure 10-9 Example Of Setting Procedure For Waveform Output By Compare Match 443 * Examples of waveform output operation Figure 10-10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB H'0000 No change TIOCA TIOCB No change No change No change 1 output 0 output Time Figure 10-10 Example of 0 Output/1 Output Operation Figure 10-11 shows an example of toggle output. In this example TCNT has been designated as a periodic counter (with counter clearing performed by compare match B), and settings have been made so that output is toggled by both compare match A and compare match B. TCNT value Counter cleared by TGRB compare match H'FFFF TGRB TGRA H'0000 Time Toggle output Toggle output TIOCB TIOCA Figure 10-11 Example of Toggle Output Operation 444 Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel's counter input clock or compare match signal as the input capture source. Note: When another channel's counter input clock is used as the input capture input for channels 0 and 3, o/1 should not be selected as the counter input clock used for input capture input. Input capture will not be generated if o/1 is selected. * Example of input capture operation setting procedure Figure 10-12 shows an example of the input capture operation setting procedure. Input selection [1] Designate TGR as an input capture register by means of TIOR, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [1] Select input capture input [2] Set the CST bit in TSTR to 1 to start the count operation. Start count [2] Figure 10-12 Example of Input Capture Operation Setting Procedure 445 * Example of input capture operation Figure 10-13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT. TCNT value H'0180 H'0160 Counter cleared by TIOCB input (falling edge) H'0010 H'0005 H'0000 Time TIOCA TGRA H'0005 H'0160 H'0010 TIOCB TGRB H'0180 Figure 10-13 Example of Input Capture Operation 446 10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation. Example of Synchronous Operation Setting Procedure: Figure 10-14 shows an example of the synchronous operation setting procedure. Synchronous operation selection Set synchronous operation [1] Synchronous presetting Synchronous clearing Set TCNT [2] Clearing sourcegeneration channel? Yes Select counter clearing source Start count No [3] [5] Set synchronous counter clearing Start count [4] [5] [1] [2] [3] [4] [5] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation. When the TCNT counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other TCNT counters. Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc. Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source. Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation. Figure 10-14 Example of Synchronous Operation Setting Procedure 447 Example of Synchronous Operation: Figure 10-15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A. At this time, synchronous presetting, and synchronous clearing by TGR0B compare match, is performed for channel 0 to 2 TCNT counters, and the data set in TGR0B is used as the PWM cycle. For details of PWM modes, see section 10.4.6, PWM Modes. Synchronous clearing by TGR0B compare match TCNT0 to TCNT2 values TGR0B TGR1B TGR0A TGR2B TGR1A TGR2A H'0000 Time TIOC0A TIOC1A TIOC2A Figure 10-15 Example of Synchronous Operation 448 10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10-5 shows the register combinations used in buffer operation. Table 10-5 Register Combinations in Buffer Operation Channel 0 Timer General Register TGR0A TGR0B 3 TGR3A TGR3B Buffer Register TGR0C TGR0D TGR3C TGR3D * When TGR is an output compare register When a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. This operation is illustrated in figure 10-16. Compare match signal Buffer register Timer general register Comparator TCNT Figure 10-16 Compare Match Buffer Operation 449 * When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10-17. Input capture signal Timer general register Buffer register TCNT Figure 10-17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10-18 shows an example of the buffer operation setting procedure. Buffer operation [1] Designate TGR as an input capture register or output compare register by means of TIOR. [1] Select TGR function [2] Designate TGR for buffer operation with bits BFA and BFB in TMDR. [3] Set the CST bit in TSTR to 1 to start the count operation. Set buffer operation [2] Start count [3] Figure 10-18 Example of Buffer Operation Setting Procedure 450 Examples of Buffer Operation * When TGR is an output compare register Figure 10-19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B. As buffer operation has been set, when compare match A occurs the output changes and the value in buffer register TGRC is simultaneously transferred to timer general register TGRA. This operation is repeated each time compare match A occurs. For details of PWM modes, see section 10.4.6, PWM Modes. TCNT value TGR0B H'0200 TGR0A H'0000 TGR0C H'0200 Transfer TGR0A H'0200 H'0450 H'0450 H'0520 Time H'0520 H'0450 TIOCA Figure 10-19 Example of Buffer Operation (1) 451 * When TGR is an input capture register Figure 10-20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge. As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC. TCNT value H'0F07 H'09FB H'0532 H'0000 Time TIOCA TGRA H'0532 H'0F07 H'09FB TGRC H'0532 H'0F07 Figure 10-20 Example of Buffer Operation (2) 452 10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10-6 shows the register combinations used in cascaded operation. Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. Table 10-6 Cascaded Combinations Combination Channels 1 and 2 Channels 4 and 5 Upper 16 Bits TCNT1 TCNT4 Lower 16 Bits TCNT2 TCNT5 Example of Cascaded Operation Setting Procedure: Figure 10-21 shows an example of the setting procedure for cascaded operation. Cascaded operation [1] Set bits TPSC2 to TPSC0 in the channel 1 (channel 4) TCR to B'111 to select TCNT2 (TCNT5) overflow/underflow counting. [1] Set cascading [2] Set the CST bit in TSTR for the upper and lower channel to 1 to start the count operation. Start count [2] Figure 10-21 Cascaded Operation Setting Procedure 453 Examples of Cascaded Operation: Figure 10-22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A. TCNT1 clock TCNT1 TCNT2 clock TCNT2 TIOCA1, TIOCA2 TGR1A H'03A2 H'FFFF H'0000 H'0001 H'03A1 H'03A2 TGR2A H'0000 Figure 10-22 Example of Cascaded Operation (1) Figure 10-23 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, and phase counting mode has been designated for channel 2. TCNT1 is incremented by TCNT2 overflow and decremented by TCNT2 underflow. TCLKA TCLKB TCNT2 FFFD FFFE FFFF 0000 0001 0002 0001 0000 FFFF TCNT1 0000 0001 0000 Figure 10-23 Example of Cascaded Operation (2) 454 10.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register. All channels can be designated for PWM mode independently. Synchronous operation is also possible. There are two PWM modes, as described below. * PWM mode 1 PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and TGRC with TGRD. The output specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR is output from the TIOCA and TIOCC pins at compare matches A and C, and the output specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR is output at compare matches B and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired TGRs are identical, the output value does not change when a compare match occurs. In PWM mode 1, a maximum 8-phase PWM output is possible. * PWM mode 2 PWM output is generated using one TGR as the cycle register and the others as duty registers. The output specified in TIOR is performed by means of compare matches. Upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in TIOR. If the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with synchronous operation. The correspondence between PWM output pins and registers is shown in table 10-7. 455 Table 10-7 PWM Output Registers and Output Pins Output Pins Channel 0 Registers TGR0A TGR0B TGR0C TGR0D 1 TGR1A TGR1B 2 TGR2A TGR2B 3 TGR3A TGR3B TGR3C TGR3D 4 TGR4A TGR4B 5 TGR5A TGR5B TIOCA5 TIOCA4 TIOCC3 TIOCA3 TIOCA2 TIOCA1 TIOCC0 PWM Mode 1 TIOCA0 PWM Mode 2 TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 TIOCB1 TIOCA2 TIOCB2 TIOCA3 TIOCB3 TIOCC3 TIOCD3 TIOCA4 TIOCB4 TIOCA5 TIOCB5 Note: In PWM mode 2, PWM output is not possible for the TGR register in which the period is set. 456 Example of PWM Mode Setting Procedure: Figure 10-24 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source. Select counter clearing source [2] Select waveform output level [3] [3] Use TIOR to designate the TGR as an output compare register, and select the initial value and output value. [4] Set the cycle in the TGR selected in [2], and set the duty in the other the TGR. [5] Select the PWM mode with bits MD3 to MD0 in TMDR. Set TGR [4] Set PWM mode [5] [6] Set the CST bit in TSTR to 1 to start the count operation. Start count [6] Figure 10-24 Example of PWM Mode Setting Procedure Examples of PWM Mode Operation: Figure 10-25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the values set in TGRB registers as the duty. 457 TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 10-25 Example of PWM Mode Operation (1) Figure 10-26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the cycle, and the values set in the other TGRs as the duty. Counter cleared by TGR1B compare match TCNT value TGR1B TGR1A TGR0D TGR0C TGR0B TGR0A H'0000 Time TIOCA0 TIOCB0 TIOCC0 TIOCD0 TIOCA1 Figure 10-26 Example of PWM Mode Operation (2) 458 Figure 10-27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode. TCNT value TGRA TGRB rewritten TGRB H'0000 0% duty TGRB rewritten TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty TGRB rewritten Time TIOCA Output does not change when cycle register and duty register compare matches occur simultaneously TCNT value TGRB rewritten TGRA TGRB rewritten TGRB H'0000 100% duty 0% duty TGRB rewritten Time TIOCA Figure 10-27 Example of PWM Mode Operation (3) 459 10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used. When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow occurs while TCNT is counting down, the TCFU flag is set. The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of whether TCNT is counting up or down. Table 10-8 shows the correspondence between external clock pins and channels. Table 10-8 Phase Counting Mode Clock Input Pins External Clock Pins Channels When channel 1 or 5 is set to phase counting mode When channel 2 or 4 is set to phase counting mode A-Phase TCLKA TCLKC B-Phase TCLKB TCLKD Example of Phase Counting Mode Setting Procedure: Figure 10-28 shows an example of the phase counting mode setting procedure. [1] Select phase counting mode with bits MD3 to MD0 in TMDR. [2] Set the CST bit in TSTR to 1 to start the count operation. Phase counting mode Select phase counting mode [1] Start count [2] Figure 10-28 Example of Phase Counting Mode Setting Procedure 460 Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. * Phase counting mode 1 Figure 10-29 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-29 Example of Phase Counting Mode 1 Operation Table 10-9 Up/Down-Count Conditions in Phase Counting Mode 1 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Down-count TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count 461 * Phase counting mode 2 Figure 10-30 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the TCNT up/down-count conditions. TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-30 Example of Phase Counting Mode 2 Operation Table 10-10 Up/Down-Count Conditions in Phase Counting Mode 2 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Don't care Don't care Don't care Down-count 462 * Phase counting mode 3 Figure 10-31 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10-31 Example of Phase Counting Mode 3 Operation Table 10-11 Up/Down-Count Conditions in Phase Counting Mode 3 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Don't care Don't care Don't care Up-count Down-count Don't care Don't care Don't care 463 * Phase counting mode 4 Figure 10-32 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10-32 Example of Phase Counting Mode 4 Operation Table 10-12 Up/Down-Count Conditions in Phase Counting Mode 4 TCLKA (Channels 1 and 5) TCLKC (Channels 2 and 4) High level Low level Low level High level High level Low level High level Low level Legend : Rising edge : Falling edge Don't care Down-count Don't care TCLKB (Channels 1 and 5) TCLKD (Channels 2 and 4) Operation Up-count 464 Phase Counting Mode Application Example: Figure 10-33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB. Channel 0 operates with TCNT counter clearing by TGR0C compare match; TGR0A and TGR0C are used for the compare match function, and are set with the speed control period and position control period. TGR0B is used for input capture, with TGR0B and TGR0D operating in buffer mode. The channel 1 counter input clock is designated as the TGR0B input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. TGR1A and TGR1B for channel 1 are designated for input capture, channel 0 TGR0A and TGR0C compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. This procedure enables accurate position/speed detection to be achieved. 465 Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) - TGR0C (position control period) + - TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10-33 Phase Counting Mode Application Example 466 10.5 10.5.1 Interrupts Interrupt Sources and Priorities There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The interrupt request is cleared by clearing the status flag to 0. Relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. For details, see section 5, Interrupt Controller. Table 10-13 lists the TPU interrupt sources. 467 Table 10-13 TPU Interrupts Channel 0 Interrupt Source Description TGI0A TGI0B TGI0C TGI0D TCI0V 1 TGI1A TGI1B TCI1V TCI1U 2 TGI2A TGI2B TCI2V TCI2U 3 TGI3A TGI3B TGI3C TGI3D TCI3V 4 TGI4A TGI4B TCI4V TCI4U 5 TGI5A TGI5B TCI5V TCI5U DMAC Activation DTC Activation Possible Priority High TGR0A input capture/compare match Possible TGR0B input capture/compare match Not possible Possible TGR0C input capture/compare match Not possible Possible TGR0D input capture/compare match Not possible Possible TCNT0 overflow Not possible Not possible Possible TGR1A input capture/compare match Possible TGR1B input capture/compare match Not possible Possible TCNT1 overflow TCNT1 underflow Not possible Not possible Not possible Not possible Possible TGR2A input capture/compare match Possible TGR2B input capture/compare match Not possible Possible TCNT2 overflow TCNT2 underflow Not possible Not possible Not possible Not possible Possible TGR3A input capture/compare match Possible TGR3B input capture/compare match Not possible Possible TGR3C input capture/compare match Not possible Possible TGR3D input capture/compare match Not possible Possible TCNT3 overflow Not possible Not possible Possible TGR4A input capture/compare match Possible TGR4B input capture/compare match Not possible Possible TCNT4 overflow TCNT4 underflow Not possible Not possible Not possible Not possible Possible TGR5A input capture/compare match Possible TGR5B input capture/compare match Not possible Possible TCNT5 overflow TCNT5 underflow Not possible Not possible Not possible Not possible Low Note: This table shows the initial state immediately after a reset. The relative channel priorities can be changed by the interrupt controller. 468 Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for each channel. Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one each for channels 1, 2, 4, and 5. 10.5.2 DTC/DMAC Activation DTC Activation: The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For details, see section 8, Data Transfer Controller. A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. DMAC Activation: The DMAC can be activated by the TGRA input capture/compare match interrupt for a channel. For details, see section 7, DMA Controller. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as DMAC activation sources, one for each channel. 10.5.3 A/D Converter Activation The A/D converter can be activated by the TGRA input capture/compare match for a channel. If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a TGRA input capture/compare match on a particular channel, a request to start A/D conversion is sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is started. In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 469 10.6 10.6.1 Operation Timing Input/Output Timing TCNT Count Timing: Figure 10-34 shows TCNT count timing in internal clock operation, and figure 10-35 shows TCNT count timing in external clock operation. o Internal clock Falling edge Rising edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10-34 Count Timing in Internal Clock Operation o External clock Falling edge Rising edge Falling edge TCNT input clock TCNT N-1 N N+1 N+2 Figure 10-35 Count Timing in External Clock Operation 470 Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10-36 shows output compare output timing. o TCNT input clock TCNT N N+1 TGR N Compare match signal TIOC pin Figure 10-36 Output Compare Output Timing Input Capture Signal Timing: Figure 10-37 shows input capture signal timing. o Input capture input Input capture signal TCNT N N+1 N+2 TGR N N+2 Figure 10-37 Input Capture Input Signal Timing 471 Timing for Counter Clearing by Compare Match/Input Capture: Figure 10-38 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-39 shows the timing when counter clearing by input capture occurrence is specified. o Compare match signal Counter clear signal N H'0000 TCNT TGR N Figure 10-38 Counter Clear Timing (Compare Match) o Input capture signal Counter clear signal N H'0000 TCNT TGR N Figure 10-39 Counter Clear Timing (Input Capture) 472 Buffer Operation Timing: Figures 10-40 and 10-41 show the timing in buffer operation. o TCNT n n+1 Compare match signal TGRA, TGRB TGRC, TGRD n N N Figure 10-40 Buffer Operation Timing (Compare Match) o Input capture signal TCNT TGRA, TGRB TGRC, TGRD N N+1 n N N+1 n N Figure 10-41 Buffer Operation Timing (Input Capture) 473 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10-42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. o TCNT input clock TCNT N N+1 TGR N Compare match signal TGF flag TGI interrupt Figure 10-42 TGI Interrupt Timing (Compare Match) 474 TGF Flag Setting Timing in Case of Input Capture: Figure 10-43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. o Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10-43 TGI Interrupt Timing (Input Capture) 475 TCFV Flag/TCFU Flag Setting Timing: Figure 10-44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10-45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. o TCNT input clock TCNT (overflow) Overflow signal TCFV flag H'FFFF H'0000 TCIV interrupt Figure 10-44 TCIV Interrupt Setting Timing o TCNT input clock TCNT (underflow) Underflow signal H'0000 H'FFFF TCFU flag TCIU interrupt Figure 10-45 TCIU Interrupt Setting Timing 476 Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC is activated, the flag is cleared automatically. Figure 10-46 shows the timing for status flag clearing by the CPU, and figure 10-47 shows the timing for status flag clearing by the DTC or DMAC. TSR write cycle T1 T2 o Address TSR address Write signal Status flag Interrupt request signal Figure 10-46 Timing for Status Flag Clearing by CPU DTC/DMAC read cycle T1 o T2 DTC/DMAC write cycle T1 T2 Address Source address Destination address Status flag Interrupt request signal Figure 10-47 Timing for Status Flag Clearing by DTC/DMAC Activation 477 10.7 Usage Notes Note that the kinds of operation and contention described below occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. Figure 10-48 shows the input clock conditions in phase counting mode. Overlap TCLKA (TCLKC) TCLKB (TCLKD) Phase Phase differdifference Overlap ence Pulse width Pulse width Pulse width Pulse width Notes: Phase difference and overlap : 1.5 states or more : 2.5 states or more Pulse width Figure 10-48 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode Caution on Period Setting: When counter clearing by compare match is set, TCNT is cleared in the final state in which it matches the TGR value (the point at which the count value matched by TCNT is updated). Consequently, the actual counter frequency is given by the following formula: f= Where o (N + 1) f : Counter frequency o : Operating frequency N : TGR set value 478 Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10-49 shows the timing in this case. TCNT write cycle T1 T2 o Address TCNT address Write signal Counter clear signal TCNT N H'0000 Figure 10-49 Contention between TCNT Write and Clear Operations 479 Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10-50 shows the timing in this case. TCNT write cycle T1 T2 o Address TCNT address Write signal TCNT input clock N TCNT write data M TCNT Figure 10-50 Contention between TCNT Write and Increment Operations 480 Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10-51 shows the timing in this case. TGR write cycle T1 T2 o Address TGR address Write signal Compare match signal TCNT N N+1 Inhibited TGR N TGR write data M Figure 10-51 Contention between TGR Write and Compare Match 481 Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10-52 shows the timing in this case. TGR write cycle T1 T2 o Address Buffer register address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10-52 Contention between Buffer Register Write and Compare Match 482 Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10-53 shows the timing in this case. TGR read cycle T1 T2 o Address TGR address Read signal Input capture signal TGR X M Internal data bus M Figure 10-53 Contention between TGR Read and Input Capture 483 Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10-54 shows the timing in this case. TGR write cycle T1 T2 o Address TGR address Write signal Input capture signal TCNT M TGR M Figure 10-54 Contention between TGR Write and Input Capture 484 Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10-55 shows the timing in this case. Buffer register write cycle T1 T2 o Address Buffer register address Write signal Input capture signal TCNT N TGR Buffer register M N M Figure 10-55 Contention between Buffer Register Write and Input Capture 485 Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10-56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. o TCNT input clock TCNT Counter clear signal TGF Disabled TCFV H'FFFF H'0000 Figure 10-56 Contention between Overflow and Counter Clearing 486 Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set . Figure 10-57 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T1 T2 o Address TCNT address Write signal TCNT write data H'FFFF M TCNT TCFV flag Figure 10-57 Contention between TCNT Write and Overflow Multiplexing of I/O Pins: In the H8S/2350 Series, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not be performed from a multiplexed pin. Interrupts and Module Stop Mode: If module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. 487 488 Section 11 Programmable Pulse Generator (PPG) 11.1 Overview The H8S/2350 Series has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently. 11.1.1 Features PPG features are listed below. * 16-bit output data Maximum 16-bit data can be output, and output can be enabled on a bit-by-bit basis * Four output groups Output trigger signals can be selected in 4-bit groups to provide up to four different 4-bit outputs * Selectable output trigger signals Output trigger signals can be selected for each group from the compare match signals of four TPU channels * Non-overlap mode A non-overlap margin can be provided between pulse outputs * Can operate together with the data transfer controller (DTC) and DMA controller (DMAC) The compare match signals selected as output trigger signals can activate the DTC or DMAC for sequential output of data without CPU intervention * Settable inverted output Inverted data can be output for each group * Module stop mode can be set As the initial setting, PPG operation is halted. Register access is enabled by exiting module stop mode 489 11.1.2 Block Diagram Figure 11-1 shows a block diagram of the PPG. Compare match signals NDERH Control logic PMR NDERL PCR PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 PO7 PO6 PO5 PO4 PO3 PO2 PO1 PO0 Pulse output pins, group 3 PODRH Pulse output pins, group 2 Pulse output pins, group 1 PODRL Pulse output pins, group 0 NDRL NDRH Internal data bus Legend PMR PCR NDERH NDERL NDRH NDRL PODRH PODRL : PPG output mode register : PPG output control register : Next data enable register H : Next data enable register L : Next data register H : Next data register L : Output data register H : Output data register L Figure 11-1 Block Diagram of PPG 490 11.1.3 Pin Configuration Table 11-1 summarizes the PPG pins. Table 11-1 PPG Pins Name Pulse output 0 Pulse output 1 Pulse output 2 Pulse output 3 Pulse output 4 Pulse output 5 Pulse output 6 Pulse output 7 Pulse output 8 Pulse output 9 Pulse output 10 Pulse output 11 Pulse output 12 Pulse output 13 Pulse output 14 Pulse output 15 Symbol PO0 PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PO13 PO14 PO15 I/O Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Output Group 3 pulse output Group 2 pulse output Group 1 pulse output Function Group 0 pulse output 491 11.1.4 Registers Table 11-2 summarizes the PPG registers. Table 11-2 PPG Registers Name PPG output control register PPG output mode register Next data enable register H Next data enable register L Output data register H Output data register L Next data register H Next data register L Port 1 data direction register Port 2 data direction register Module stop control register Abbreviation PCR PMR NDERH NDERL PODRH PODRL NDRH NDRL P1DDR P2DDR MSTPCR R/W R/W R/W R/W R/W R/(W)* R/(W)* R/W R/W W W R/W 2 2 Initial Value H'FF H'F0 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3FFF Address* 1 H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B H'FF4C* 3 H'FF4E H'FF4D* 3 H'FF4F H'FEB0 H'FEB1 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bits used for pulse output cannot be written to. 3. When the same output trigger is selected for pulse output groups 2 and 3 by the PCR setting, the NDRH address is H'FF4C. When the output triggers are different, the NDRH address is H'FF4E for group 2 and H'FF4C for group 3. Similarly, when the same output trigger is selected for pulse output groups 0 and 1 by the PCR setting, the NDRL address is H'FF4D. When the output triggers are different, the NDRL address is H'FF4F for group 0 and H'FF4D for group 1. 492 11.2 11.2.1 NDERH Register Descriptions Next Data Enable Registers H and L (NDERH, NDERL) Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : R/W : NDERL Bit : 7 NDER7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W NDER6 NDER5 NDER4 NDER3 NDER1 NDER0 Initial value : R/W : NDERH and NDERL are 8-bit readable/writable registers that enable or disable pulse output on a bit-by-bit basis. If a bit is enabled for pulse output by NDERH or NDERL, the NDR value is automatically transferred to the corresponding PODR bit when the TPU compare match event specified by PCR occurs, updating the output value. If pulse output is disabled, the bit value is not transferred from NDR to PODR and the output value does not change. NDERH and NDERL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. NDERH Bits 7 to 0--Next Data Enable 15 to 8 (NDER15 to NDER8): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER15 to NDER8 0 1 Description Pulse outputs PO15 to PO8 are disabled (NDR15 to NDR8 are not transferred to POD15 to POD8) (Initial value) Pulse outputs PO15 to PO8 are enabled (NDR15 to NDR8 are transferred to POD15 to POD8) 493 NDERL Bits 7 to 0--Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 0 1 Description Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not transferred to POD7 to POD0) (Initial value) Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to POD7 to POD0) 11.2.2 Output Data Registers H and L (PODRH, PODRL) PODRH Bit : 7 POD15 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* Initial value : R/W : PODRL Bit : 7 POD7 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* Initial value : R/W : Note: * A bit that has been set for pulse output by NDER is read-only. PODRH and PODRL are 8-bit readable/writable registers that store output data for use in pulse output. 494 11.2.3 Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. For details see section 11.2.4, Notes on NDR Access. NDRH and NDRL are each initialized to H'00 by a reset and in hardware standby mode. They are not initialized in software standby mode. 11.2.4 Notes on NDR Access The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers. Same Trigger for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by the same compare match event, the NDRH address is H'FF4C. The upper 4 bits belong to group 3 and the lower 4 bits to group 2. Address H'FF4E consists entirely of reserved bits that cannot be modified and are always read as 1. Address H'FF4C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Address H'FF4E Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- If pulse output groups 0 and 1 are triggered by the same compare match event, the NDRL address is H'FF4D. The upper 4 bits belong to group 1 and the lower 4 bits to group 0. Address H'FF4F consists entirely of reserved bits that cannot be modified and are always read as 1. 495 Address H'FF4D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Address H'FF4F Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of the upper 4 bits in NDRH (group 3) is H'FF4C and the address of the lower 4 bits (group 2) is H'FF4E. Bits 3 to 0 of address H'FF4C and bits 7 to 4 of address H'FF4E are reserved bits that cannot be modified and are always read as 1. Address H'FF4C Bit : 7 NDR15 Initial value : R/W : 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Address H'FF4E Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W If pulse output groups 0 and 1 are triggered by different compare match event, the address of the upper 4 bits in NDRL (group 1) is H'FF4D and the address of the lower 4 bits (group 0) is H'FF4F. Bits 3 to 0 of address H'FF4D and bits 7 to 4 of address H'FF4F are reserved bits that cannot be modified and are always read as 1. 496 Address H'FF4D Bit : 7 NDR7 Initial value : R/W : 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Address H'FF4F Bit : 7 -- Initial value : R/W : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W 11.2.5 Bit PPG Output Control Register (PCR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : R/W : PCR is an 8-bit readable/writable register that selects output trigger signals for PPG outputs on a group-by-group basis. PCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 7 and 6--Group 3 Compare Match Select 1 and 0 (G3CMS1, G3CMS0): These bits select the compare match that triggers pulse output group 3 (pins PO15 to PO12). Description Bit 7 G3CMS1 0 Bit 6 G3CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 3 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) 497 Bits 5 and 4--Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8). Description Bit 5 G2CMS1 0 Bit 4 G2CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 2 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Bits 3 and 2--Group 1 Compare Match Select 1 and 0 (G1CMS1, G1CMS0): These bits select the compare match that triggers pulse output group 1 (pins PO7 to PO4). Description Bit 3 G1CMS1 0 Bit 2 G1CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) Bits 1 and 0--Group 0 Compare Match Select 1 and 0 (G0CMS1, G0CMS0): These bits select the compare match that triggers pulse output group 0 (pins PO3 to PO0). Description Bit 1 G0CMS1 0 Bit 0 G0CMS0 0 1 1 0 1 Output Trigger for Pulse Output Group 0 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 (Initial value) 498 11.2.6 Bit PPG Output Mode Register (PMR) : 7 G3INV 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 G0INV 1 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W G3NOV G2NOV G1NOV G0NOV Initial value : R/W : PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group. The output trigger period of a non-overlapping operation PPG output waveform is set in TGRB and the non-overlap margin is set in TGRA. The output values change at compare match A and B. For details, see section 11.3.4, Non-Overlapping Pulse Output. PMR is initialized to H'F0 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Group 3 Inversion (G3INV): Selects direct output or inverted output for pulse output group 3 (pins PO15 to PO12). Bit 7 G3INV 0 1 Description Inverted output for pulse output group 3 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 3 (high-level output at pin for a 1 in PODRH) (Initial value) Bit 6--Group 2 Inversion (G2INV): Selects direct output or inverted output for pulse output group 2 (pins PO11 to PO8). Bit 6 G2INV 0 1 Description Inverted output for pulse output group 2 (low-level output at pin for a 1 in PODRH) Direct output for pulse output group 2 (high-level output at pin for a 1 in PODRH) (Initial value) 499 Bit 5--Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). Bit 5 G1INV 0 1 Description Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 4--Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output group 0 (pins PO3 to PO0). Bit 4 G0INV 0 1 Description Inverted output for pulse output group 0 (low-level output at pin for a 1 in PODRL) Direct output for pulse output group 0 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 3--Group 3 Non-Overlap (G3NOV): Selects normal or non-overlapping operation for pulse output group 3 (pins PO15 to PO12). Bit 3 G3NOV 0 1 Description Normal operation in pulse output group 3 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 3 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Bit 2--Group 2 Non-Overlap (G2NOV): Selects normal or non-overlapping operation for pulse output group 2 (pins PO11 to PO8). Bit 2 G2NOV 0 1 Description Normal operation in pulse output group 2 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 2 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 500 Bit 1--Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4). Bit 1 G1NOV 0 1 Description Normal operation in pulse output group 1 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 1 (independent 1 and 0 output at compare match A or B in the selected TPU channel) Bit 0--Group 0 Non-Overlap (G0NOV): Selects normal or non-overlapping operation for pulse output group 0 (pins PO3 to PO0). Bit 0 G0NOV 0 1 Description Normal operation in pulse output group 0 (output values updated at compare match A in the selected TPU channel) (Initial value) Non-overlapping operation in pulse output group 0 (independent 1 and 0 output at compare match A or B in the selected TPU channel) 501 11.2.7 Bit Port 1 Data Direction Register (P1DDR) : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : R/W : P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. Port 1 is multiplexed with pins PO15 to PO8. Bits corresponding to pins used for PPG output must be set to 1. For further information about P1DDR, see section 9.2, Port 1. 11.2.8 Bit Port 2 Data Direction Register (P2DDR) : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W 2 0 W 1 0 W 0 0 W P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : R/W : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1. For further information about P2DDR, see section 9.3, Port 2. 502 11.2.9 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP11 bit in MSTPCR is set to 1, PPG operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 11--Module Stop (MSTP11): Specifies the PPG module stop mode. Bit 11 MSTP11 0 1 Description PPG module stop mode cleared PPG module stop mode set (Initial value) 503 11.3 11.3.1 Operation Overview PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11-2 illustrates the PPG output operation and table 11-3 summarizes the PPG operating conditions. DDR Q NDER Q Output trigger signal C Q PODR D Pulse output pin Normal output/inverted output Q NDR D Internal data bus Figure 11-2 PPG Output Operation Table 11-3 PPG Operating Conditions NDER 0 DDR 0 1 1 0 1 Pin Function Generic input port Generic output port Generic input port (but the PODR bit is a read-only bit, and when compare match occurs, the NDR bit value is transferred to the PODR bit) PPG pulse output Sequential output of data of up to 16 bits is possible by writing new output data to NDR before the next compare match. For details of non-overlapping operation, see section 11.3.4, NonOverlapping Pulse Output. 504 11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11-3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. o TCNT N N+1 TGRA N Compare match A signal NDRH n PODRH m n PO8 to PO15 m n Figure 11-3 Timing of Transfer and Output of NDR Contents (Example) 505 11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11-4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions Set TGRA value TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Port and PPG setup Select output trigger Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [10] [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA an output compare register (with output disabled) [2] Set the PPG output trigger period [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the output trigger in PCR. [8] Set the next pulse output values in NDR. [9] Set the CST bit in TSTR to 1 to start the TCNT counter. [10] At each TGIA interrupt, set the next output values in NDR. [9] No Figure 11-4 Setup Procedure for Normal Pulse Output (Example) 506 Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11-5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value TGRA TCNT Compare match H'0000 NDRH 80 C0 40 60 20 30 10 18 08 88 80 C0 40 Time PODRH 00 80 C0 40 60 20 30 10 18 08 88 80 C0 PO15 PO14 PO13 PO12 PO11 Figure 11-5 Normal Pulse Output Example (Five-Phase Pulse Output) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA is an output compare register and the counter will be cleared by compare match A. Set the trigger period in TGRA and set the TGIEA bit in TIER to 1 to enable the compare match A (TGIA) interrupt. [2] Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Write output data H'80 in NDRH. [3] The timer counter in the TPU channel starts. When compare match A occurs, the NDRH contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the next output data (H'C0) in NDRH. [4] Five-phase overlapping pulse output (one or two phases active at a time) can be obtained subsequently by writing H'40, H'60, H'20, H'30. H'10, H'18, H'08, H'88... at successive TGIA interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. 507 11.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11-6 shows a sample procedure for setting up non-overlapping pulse output. Non-overlapping PPG output Select TGR functions Set TGR values TPU setup Set counting operation Select interrupt request Set initial output data Enable pulse output Select output trigger Set non-overlapping groups Set next pulse output data TPU setup Start counter Compare match? Yes Set next pulse output data [11] [3] [4] [5] [6] [7] [8] [1] [2] [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled) [2] Set the pulse output trigger period in TGRB and the non-overlap margin in TGRA. [3] Select the counter clock source with bits TPSC2 to TPSC0 in TCR. Select the counter clear source with bits CCLR1 and CCLR0. [4] Enable the TGIA interrupt in TIER. The DTC or DMAC can also be set up to transfer data to NDR. [5] Set the initial output values in PODR. [6] Set the DDR and NDER bits for the pins to be used for pulse output to 1. [7] Select the TPU compare match event to be used as the pulse output trigger in PCR. [8] In PMR, select the groups that will operate in non-overlap mode. [9] Set the next pulse output values in NDR. [10] Set the CST bit in TSTR to 1 to start the TCNT counter. [11] At each TGIA interrupt, set the next output values in NDR. PPG setup [9] [10] No Figure 11-6 Setup Procedure for Non-Overlapping Pulse Output (Example) 508 Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11-7 shows an example in which pulse output is used for fourphase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRH 00 95 05 65 41 59 50 56 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-7 Non-Overlapping Pulse Output Example (Four-Phase Complementary) 509 [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt. [2] Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0 bits in PCR to select compare match in the TPU channel set up in the previous step to be the output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output. Write output data H'95 in NDRH. [3] The timer counter in the TPU channel starts. When a compare match with TGRB occurs, outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0 to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt handling routine writes the next output data (H'65) in NDRH. [4] Four-phase complementary non-overlapping pulse output can be obtained subsequently by writing H'59, H'56, H'95... at successive TGIA interrupts. If the DTC or DMAC is set for activation by this interrupt, pulse output can be obtained without imposing a load on the CPU. 510 11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11-8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11-7. TCNT value TGRB TCNT TGRA H'0000 NDRH 95 65 59 56 95 65 Time PODRL 00 95 05 65 41 59 50 56 14 95 05 65 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11-8 Inverted Pulse Output (Example) 511 11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11-9 shows the timing of this output. o TIOC pin Input capture signal NDR N PODR M N PO M N Figure 11-9 Pulse Output Triggered by Input Capture (Example) 512 11.4 Usage Notes Operation of Pulse Output Pins: Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by another peripheral function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur. Note on Non-Overlapping Output: During non-overlapping operation, the transfer of NDR bit values to PODR bits takes place as follows. * NDR bits are always transferred to PODR bits at compare match A. * At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred if their value is 1. Figure 11-10 illustrates the non-overlapping pulse output operation. DDR NDER Q Compare match A Compare match B Pulse output pin C Q PODR D Q NDR D Internal data bus Normal output/inverted output Figure 11-10 Non-Overlapping Pulse Output 513 Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC. Note, however, that the next data must be written before the next compare match B occurs. Figure 11-11 shows the timing of this operation. Compare match A Compare match B Write to NDR NDR Write to NDR PODR 0 output 0/1 output Write to NDR Do not write here to NDR here 0 output 0/1 output Write to NDR Do not write here to NDR here Figure 11-11 Non-Overlapping Operation and NDR Write Timing 514 Section 12 Watchdog Timer 12.1 Overview The H8S/2350 Series has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF) if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the H8S/2350 Series. When this watchdog function is not needed, the WDT can be used as an interval timer. In interval timer operation, an interval timer interrupt is generated each time the counter overflows. 12.1.1 Features WDT features are listed below. * Switchable between watchdog timer mode and interval timer mode * WDTOVF output when in watchdog timer mode If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not the entire H8S/2350 Series is reset at the same time. This internal reset can be a power-on reset or a manual reset. * Interrupt generation when in interval timer mode If the counter overflows, the WDT generates an interval timer interrupt. * Choice of eight counter clock sources. 515 12.1.2 Block Diagram Figure 12-1 shows a block diagram of the WDT. Overflow WOVI (interrupt request signal) Interrupt control Clock Clock select WDTOVF Internal reset signal* Reset control o/2 o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Internal clock sources Internal bus RSTCSR TCNT TSCR Module bus Bus interface WDT Legend : Timer control/status register TCSR : Timer counter TCNT RSTCSR : Reset control/status register Note: * The type of internal reset signal depends on a register setting. Either power-on reset or manual reset can be selected. Figure 12-1 Block Diagram of WDT 516 12.1.3 Pin Configuration Table 12-1 describes the WDT output pin. Table 12-1 WDT Pin Name Watchdog timer overflow Symbol WDTOVF I/O Output Function Outputs counter overflow signal in watchdog timer mode 12.1.4 Register Configuration The WDT has three registers, as summarized in table 12-2. These registers control clock selection, WDT mode switching, and the reset signal. Table 12-2 WDT Registers Address* 1 Name Timer control/status register Timer counter Reset control/status register Abbreviation TCSR TCNT RSTCSR R/W R/(W)* R/W R/(W)* 3 3 Initial Value H'18 H'00 H'1F Write*2 H'FFBC H'FFBC H'FFBE Read H'FFBC H'FFBD H'FFBF Notes: 1. Lower 16 bits of the address. 2. For details of write operations, see section 12.2.4, Notes on Register Access. 3. Only a write of 0 is permitted to bit 7, to clear the flag. 517 12.2 12.2.1 Bit Register Descriptions Timer Counter (TCNT) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value : R/W : TCNT is an 8-bit readable/writable* up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR. When the count overflows (changes from H'FF to H'00), either the watchdog timer overflow signal (WDTOVF) or an interval timer interrupt (WOVI) is generated, depending on the mode selected by the WT/IT bit in TCSR. TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared to 0. It is not initialized in software standby mode. Note: * TCNT is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. 12.2.2 Bit Timer Control/Status Register (TCSR) : 7 OVF 0 R/(W)* 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : Note: * Can only be written with 0 for flag clearing. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode. It is not initialized in software standby mode. Note: * TCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. 518 Bit 7--Overflow Flag (OVF): Indicates that TCNT has overflowed from H'FF to H'00, when in interval timer mode. This flag cannot be set during watchdog timer operation. Bit 7 OVF 0 Description [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF 1 [Setting condition] Set when TCNT overflows (changes from H'FF to H'00) in interval timer mode (Initial value) Bit 6--Timer Mode Select (WT/IT): Selects whether the WDT is used as a watchdog timer or interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request (WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates the WDTOVF signal when TCNT overflows. Bit 6 WT/IT 0 1 Description Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) Watchdog timer: Generates the WDTOVF signal when TCNT overflows Note: * For details of the case where TCNT overflows in watchdog timer mode, see section 12.2.3, Reset Control/Status Register (RSTCSR). Bit 5--Timer Enable (TME): Selects whether TCNT runs or is halted. Bit 5 TME 0 1 Description TCNT is initialized to H'00 and halted TCNT counts (Initial value) Bits 4 and 3--Reserved: Read-only bits, always read as 1. 519 Bits 2 to 0: Clock Select 2 to 0 (CKS2 to CKS0): These bits select one of eight internal clock sources, obtained by dividing the system clock (o), for input to TCNT. Description Bit 2 CKS2 0 Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 1 0 0 1 1 0 1 Clock o/2 (initial value) o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Overflow Period (when o = 20 MHz)* 25.6 s 819.2 s 1.6 ms 6.6 ms 26.2 ms 104.9 ms 419.4 ms 1.68 s Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. 12.2.3 Bit Reset Control/Status Register (RSTCSR) : 7 WOVF 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value: R/W : Note: * Can only be written with 0 for flag clearing. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin, but not by the WDT internal reset signal caused by overflows. Note: * RSTCSR is write-protected by a password to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. 520 Bit 7--Watchdog Overflow Flag (WOVF): Indicates that TCNT has overflowed (changed from H'FF to H'00) during watchdog timer operation. This bit is not set in interval timer mode. Bit 7 WOVF 0 Description [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF 1 [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation (Initial value) Bit 6--Reset Enable (RSTE): Specifies whether or not a reset signal is generated in the H8S/2350 Series if TCNT overflows during watchdog timer operation. Bit 6 RSTE 0 1 Description Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows (Initial value) Note: * The modules within the H8S/2350 Series are not reset, but TCNT and TCSR within the WDT are reset. Bit 5--Reset Select (RSTS): Selects the type of internal reset generated if TCNT overflows during watchdog timer operation. For details of the types of resets, see section 4, Exception Handling. Bit 5 RSTS 0 1 Description Power-on reset Manual reset (Initial value) Bits 4 to 0--Reserved: Read-only bits, always read as 1. 521 12.2.4 Notes on Register Access The watchdog timer's TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction. They cannot be written to with byte instructions. Figure 12-2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the same write address. For a write to TCNT, the upper byte of the written word must contain H'5A and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written word must contain H'A5 and the lower byte must contain the write data. This transfers the write data from the lower byte to TCNT or TCSR. TCNT write 15 Address: H'FFBC H'5A 87 Write data 0 TCSR write 15 Address: H'FFBC H'A5 87 Write data 0 Figure 12-2 Format of Data Written to TCNT and TCSR 522 Writing to RSTCSR: RSTCSR must be written to by word transfer instruction to address H'FFBE. It cannot be written to with byte instructions. Figure 12-3 shows the format of data written to RSTCSR. The method of writing 0 to the WOVF bit differs from that for writing to the RSTE and RSTS bits. To write 0 to the WOVF bit, the write data must have H'A5 in the upper byte and H'00 in the lower byte. This clears the WOVF bit to 0, but has no effect on the RSTE and RSTS bits. To write to the RSTE and RSTS bits, the upper byte must contain H'5A and the lower byte must contain the write data. This writes the values in bits 6 and 5 of the lower byte into the RSTE and RSTS bits, but has no effect on the WOVF bit. Writing 0 to WOVF bit 15 Address: H'FFBE H'A5 87 H'00 0 Writing to RSTE and RSTS bits 15 Address: H'FFBE H'5A 87 Write data 0 Figure 12-3 Format of Data Written to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. 523 12.3 12.3.1 Operation Watchdog Timer Operation To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1. Software must prevent TCNT overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs. This ensures that TCNT does not overflow while the system is operating normally. If TCNT overflows without being rewritten because of a system crash or other error, the WDTOVF signal is output. This is shown in figure 12-4. This WDTOVF signal can be used to reset the system. The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0. If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets the H8S/2350 Series internally is generated at the same time as the WDTOVF signal. This reset can be selected as a power-on reset or a manual reset, depending on the setting of the RSTS bit in RSTCSR. The internal reset signal is output for 518 states. If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. TCNT count Overflow H'FF H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF and internal reset are generated WT/IT=1 TME=1 H'00 written to TCNT Time WDTOVF signal 132 states*2 Internal reset signal*1 518 states Legend WT/IT : Timer mode select bit TME : Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. Figure 12-4 Watchdog Timer Operation 524 12.3.2 Interval Timer Operation To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 12-5. This function can be used to generate interrupt requests at regular intervals. TCNT count H'FF Overflow Overflow Overflow Overflow H'00 WT/IT=0 TME=1 WOVI WOVI WOVI WOVI Time Legend WOVI: Interval timer interrupt request generation Figure 12-5 Interval Timer Operation 12.3.3 Timing of Setting Overflow Flag (OVF) The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 12-6. 525 o TCNT H'FF H'00 o1 Overflow signal (internal signal) o1 OVF o1 Figure 12-6 Timing of Setting of OVF 12.3.4 Timing of Setting of Watchdog Timer Overflow Flag (WOVF) The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire H8S/2350 Series chip. Figure 12-7 shows the timing in this case. o TCNT H'FF H'00 Overflow signal (internal signal) WOVF WDTOVF signal Internal reset signal 132 states 518 states Figure 12-7 Timing of Setting of WOVF 526 12.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 12.5 12.5.1 Usage Notes Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 12-8 shows this operation. TCNT write cycle T1 T2 o Address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12-8 Contention between TCNT Write and Increment 12.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 527 12.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before switching the mode. 12.5.4 System Reset by WDTOVF Signal If the WDTOVF output signal is input to the RES pin of the H8S/2350 Series, the H8S/2350 Series will not be initialized correctly. Make sure that the WDTOVF signal is not input logically to the RES pin. To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 12-9. H8S/2350 Series Reset input RES Reset signal to entire system WDTOVF Figure 12-9 Circuit for System Reset by WDTOVF Signal (Example) 12.5.5 Internal Reset in Watchdog Timer Mode The H8S/2350 Series is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TSCR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF falg, therefore, read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag. 528 Section 13 Serial Communication Interface (SCI) 13.1 Overview The H8S/2350 Series is equipped with a two-channel serial communication interface (SCI). All two channels have the same functions. The SCI can handle both asynchronous and clocked synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 13.1.1 Features SCI features are listed below. * Choice of asynchronous or clocked synchronous serial communication mode Asynchronous mode Serial data communication executed using asynchronous system in which synchronization is achieved character by character Serial data communication can be carried out with standard asynchronous communication chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter (ACIA) A multiprocessor communication function is provided that enables serial data communication with a number of processors Choice of 12 serial data transfer formats Data length : 7 or 8 bits Stop bit length : 1 or 2 bits Parity : Even, odd, or none Multiprocessor bit : 1 or 0 Receive error detection : Parity, overrun, and framing errors Break detection : Break can be detected by reading the RxD pin level directly in case of a framing error Clocked Synchronous mode Serial data communication synchronized with a clock Serial data communication can be carried out with other chips that have a synchronous communication function One serial data transfer format Data length : 8 bits Receive error detection : Overrun errors detected 529 * Full-duplex communication capability The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data * On-chip baud rate generator allows any bit rate to be selected * Choice of serial clock source: internal clock from baud rate generator or external clock from SCK pin * Four interrupt sources Four interrupt sources -- transmit-data-empty, transmit-end, receive-data-full, and receive error -- that can issue requests independently The transmit-data-empty interrupt and receive data full interrupts can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer * Choice of LSB-first or MSB-first transfer Can be selected regardless of the communication mode* (except in the case of asynchronous mode bit data) * Module stop mode can be set As the initial setting, SCI operation is halted. Register access is enabled by exiting module stop mode. Note: * Descriptions in this section refer to LSB-first transfer. 530 13.1.2 Block Diagram Figure 13-1 shows a block diagram of the SCI. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR o Baud rate generator o/4 o/16 o/64 Clock TxD Parity generation Parity check SCK External clock TEI TXI RXI ERI Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR : Smart Card mode register : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register : Bit rate register Figure 13-1 Block Diagram of SCI 531 13.1.3 Pin Configuration Table 13-1 shows the serial pins for each SCI channel. Table 13-1 SCI Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output 532 13.1.4 Register Configuration The SCI has the internal registers shown in table 13-2. These registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. Table 13-2 SCI Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF3C Smart card mode register 0 SCMR0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 Smart card mode register 1 SCMR1 All Module stop control register MSTPCR Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 533 13.2 13.2.1 Bit R/W Register Descriptions Receive Shift Register (RSR) : : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 13.2.2 Bit Receive Data Register (RDR) : 7 0 R 6 0 R 5 0 R 4 0 R 3 0 R 2 0 R 1 0 R 0 0 R Initial value : R/W : RDR is a register that stores received serial data. When the SCI has received one byte of serial data, it transfers the received serial data from RSR to RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous receive operations to be performed. RDR is a read-only register, and cannot be written to by the CPU. RDR is initialized to H'00 by a reset, and in standby mode or module stop mode. 534 13.2.3 Bit R/W Transmit Shift Register (TSR) : : 7 -- 6 -- 5 -- 4 -- 3 -- 2 -- 1 -- 0 -- TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not performed if the TDRE bit in SSR is set to 1. TSR cannot be directly read or written to by the CPU. 13.2.4 Bit Transmit Data Register (TDR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : TDR is an 8-bit register that stores data for serial transmission. When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and starts serial transmission. Continuous serial transmission can be carried out by writing the next transmit data to TDR during serial transmission of the data in TSR. TDR can be read or written to by the CPU at all times. TDR is initialized to H'FF by a reset, and in standby mode or module stop mode. 535 13.2.5 Bit Serial Mode Register (SMR) : 7 C/A 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W Initial value : R/W : SMR is an 8-bit register used to set the SCI's serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7--Communication Mode (C/A): Selects asynchronous mode or clocked synchronous mode as the SCI operating mode. Bit 7 C/A 0 1 Description Asynchronous mode Clocked synchronous mode (Initial value) Bit 6--Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In clocked synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting. Bit 6 CHR 0 1 Description 8-bit data 7-bit data* (Initial value) Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and it is not possible to choose between LSB-first or MSB-first transfer. 536 Bit 5--Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In clocked synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting. Bit 5 PE 0 1 Description Parity bit addition and checking disabled Parity bit addition and checking enabled* (Initial value) Note:* When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to transmit data before transmission. In reception, the parity bit is checked for the parity (even or odd) specified by the O/E bit. Bit 4--Parity Mode (O/E): Selects either even or odd parity for use in parity addition and checking. The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. The O/E bit setting is invalid in clocked synchronous mode, and when parity addition and checking is disabled in asynchronous mode. Bit 4 O/E 0 1 Description Even parity* 1 Odd parity* 2 (Initial value) Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. When odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. In reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd. 537 Bit 3--Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode. The STOP bits setting is only valid in asynchronous mode. If clocked synchronous mode is set the STOP bit setting is invalid since stop bits are not added. Bit 3 STOP 0 1 Description 1 stop bit: In transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 2 stop bits: In transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. Bit 2--Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. For details of the multiprocessor communication function, see section 13.3.3, Multiprocessor Communication Function. Bit 2 MP 0 1 Description Multiprocessor function disabled Multiprocessor format selected (Initial value) Bits 1 and 0--Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the baud rate generator. The clock source can be selected from o, o/4, o/16, and o/64, according to the setting of bits CKS1 and CKS0. For the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, Bit Rate Register. Bit 1 CKS1 0 Bit 0 CKS0 0 1 1 0 1 Description o clock o/4 clock o/16 clock o/64 clock (Initial value) 538 13.2.6 Bit Serial Control Register (SCR) : 7 TIE 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times. SCR is initialized to H'00 by a reset, and in standby mode or module stop mode. Bit 7--Transmit Interrupt Enable (TIE): Enables or disables transmit data empty interrupt (TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE flag in SSR is set to 1. Bit 7 TIE 0 1 Description Transmit data empty interrupt (TXI) requests disabled* Transmit data empty interrupt (TXI) requests enabled (Initial value) Note:* TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag, then clearing it to 0, or clearing the TIE bit to 0. Bit 6--Receive Interrupt Enable (RIE): Enables or disables receive data full interrupt (RXI) request and receive error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1. Bit 6 RIE 0 1 Description Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled* (Initial value) Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Note:* RXI and ERI interrupt request cancellation can be performed by reading 1 from the RDRF flag, or the FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0. 539 Bit 5--Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI. Bit 5 TE 0 1 Description Transmission disabled* 1 Transmission enabled* 2 (Initial value) Notes: 1. The TDRE flag in SSR is fixed at 1. 2. In this state, serial transmission is started when transmit data is written to TDR and the TDRE flag in SSR is cleared to 0. SMR setting must be performed to decide the transfer format before setting the TE bit to 1. Bit 4--Receive Enable (RE): Enables or disables the start of serial reception by the SCI. Bit 4 RE 0 1 Description Reception disabled* 1 Reception enabled* 2 (Initial value) Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which retain their states. 2. Serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. SMR setting must be performed to decide the transfer format before setting the RE bit to 1. 540 Bit 3--Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in clocked synchronous mode or when the MP bit is cleared to 0. Bit 3 MPIE 0 Description Multiprocessor interrupts disabled (normal reception performed) [Clearing conditions] * * 1 When the MPIE bit is cleared to 0 When MPB= 1 data is received (Initial value) Multiprocessor interrupts enabled* Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received. Note: * When receive data including MPB = 0 is received, receive data transfer from RSR to RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR , is not performed. When receive data including MPB = 1 is received, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag setting is enabled. Bit 2--Transmit End Interrupt Enable (TEIE): Enables or disables transmit end interrupt (TEI) request generation when there is no valid transmit data in TDR in MSB data transmission. Bit 2 TEIE 0 1 Description Transmit end interrupt (TEI) request disabled* Transmit end interrupt (TEI) request enabled* (Initial value) Note: * TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0. 541 Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. The combination of the CKE1 and CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or the serial clock input pin. The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in asynchronous mode. The CKE0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (CKE1 = 1). Note that the SCI's operating mode must be decided using SMR before setting the CKE1 and CKE0 bits. For details of clock source selection, see table 13-9 in section 13-3, Operation. Bit 1 CKE1 0 Bit 0 CKE0 0 Description Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode 1 0 Asynchronous mode Clocked synchronous mode 1 Asynchronous mode Clocked synchronous mode Internal clock/SCK pin functions as I/O port* 1 Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output* 2 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input* 3 External clock/SCK pin functions as serial clock input Notes: 1. Initial value 2. Outputs a clock of the same frequency as the bit rate. 3. Inputs a clock with a frequency 16 times the bit rate. 542 13.2.7 Bit Serial Status Register (SSR) : 7 TDRE 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : Note: Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified. SSR is initialized to H'84 by a reset, and in standby mode or module stop mode. Bit 7--Transmit Data Register Empty (TDRE): Indicates that data has been transferred from TDR to TSR and the next serial data can be written to TDR. Bit 7 TDRE 0 Description [Clearing conditions] * * 1 * * When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) When the TE bit in SCR is 0 When data is transferred from TDR to TSR and data can be written to TDR [Setting conditions] Bit 6--Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR. Bit 6 RDRF 0 Description [Clearing conditions] (Initial value) * When 0 is written to RDRF after reading RDRF = 1 * When the DMAC or DTC is activated by an RXI interrupt and read data from RDR 1 [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR Note: RDR and the RDRF flag are not affected and retain their previous values when an error is detected during reception or when the RE bit in SCR is cleared to 0. If reception of the next data is completed while the RDRF flag is still set to 1, an overrun error will occur and the receive data will be lost. 543 Bit 5--Overrun Error (ORER): Indicates that an overrun error occurred during reception, causing abnormal termination. Bit 5 ORER 0 Description [Clearing condition] When 0 is written to ORER after reading ORER = 1 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. The receive data prior to the overrun error is retained in RDR, and the data received subsequently is lost. Also, subsequent serial reception cannot be continued while the ORER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 Bit 4--Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER 0 Description [Clearing condition] When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. If a framing error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the FER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. (Initial value)*1 544 Bit 3--Parity Error (PER): Indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. Bit 3 PER 0 1 Description [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR* 2 (Initial value)*1 Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is cleared to 0. 2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not set. Also, subsequent serial reception cannot be continued while the PER flag is set to 1. In clocked synchronous mode, serial transmission cannot be continued, either. Bit 2--Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified. Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) When the TE bit in SCR is 0 When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Setting conditions] Bit 1--Multiprocessor Bit (MPB): When reception is performed using multiprocessor format in asynchronous mode, MPB stores the multiprocessor bit in the receive data. MPB is a read-only bit, and cannot be modified. Bit 1 MPB 0 1 Description [Clearing condition] When data with a 0 multiprocessor bit is received (Initial value)* [Setting condition] When data with a 1 multiprocessor bit is received Note: * Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor format. 545 Bit 0--Multiprocessor Bit Transfer (MPBT): When transmission is performed using multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to the transmit data. The MPBT bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. Bit 0 MPBT 0 1 Description Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted (Initial value) 13.2.8 Bit Bit Rate Register (BRR) : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W Initial value : R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset, and in standby mode or module stop mode. As baud rate generator control is performed independently for each channel, different values can be set for each channel. Table 13-3 shows sample BRR settings in asynchronous mode, and table 13-4 shows sample BRR settings in clocked synchronous mode. 546 Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) o = 2 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 -- -- 0.00 -- o = 2.097152 MHz Error (%) o = 2.4576 MHz Error (%) o = 3 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 -2.34 -2.34 -2.34 0.00 -- n 1 1 0 0 0 0 0 0 0 0 0 N 141 103 207 103 51 25 12 6 2 1 1 n 1 1 0 0 0 0 0 0 0 0 0 N 148 108 217 108 54 26 13 6 2 1 1 n N 174 127 255 127 63 31 15 7 3 1 1 n N 212 155 77 155 77 38 19 9 4 2 -- -0.04 1 0.21 0.21 0.21 1 0 0 -0.26 1 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 1 1 0 0 0 0 0 0 0 -- -0.70 0 1.14 0 -2.48 0 -2.48 0 -- -- -- 0 0 0 o = 3.6864 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -- 0.00 o = 4 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -- 0.00 -- o = 4.9152 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 5 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 1.73 0.00 1.73 n 2 1 1 0 0 0 0 0 0 -- 0 N 64 191 95 191 95 47 23 11 5 -- 2 n 2 1 1 0 0 0 0 0 0 0 0 N 70 207 103 207 103 51 25 12 6 3 2 n 2 1 1 0 0 0 0 0 0 0 0 N 86 255 127 255 127 63 31 15 7 4 3 n 2 2 1 1 0 0 0 0 0 N 88 64 129 64 129 64 32 15 7 4 3 -1.70 0 0.00 0 547 Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) o = 6 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 6.144 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 o = 7.3728 MHz Error (%) o = 8 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -- n 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 38 19 9 5 4 n N 108 79 159 79 159 79 39 19 9 5 4 n 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 n N 141 103 207 103 207 103 51 25 12 7 6 -0.44 2 0.16 0.16 0.16 0.16 0.16 0.16 2 1 1 0 0 0 -0.07 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 1 1 0 0 0 0 0 0 0 -2.34 0 -2.34 0 0.00 0 -2.34 0 o = 9.8304 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 10 MHz Error (%) o = 12 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 o = 12.288 MHz Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 n N 177 129 64 129 64 129 64 32 15 9 7 n N 212 155 77 155 77 155 77 38 19 11 9 n 2 2 2 1 1 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 -0.26 2 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2 2 1 1 0 0 0 0 -0.25 2 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -1.36 0 1.73 0.00 1.73 0 0 0 -2.34 0 0.00 0 -1.70 0 0.00 0 -2.34 0 548 Table 13-3 BRR Settings for Various Bit Rates (Asynchronous Mode) (cont) o = 14 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 14.7456 MHz Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 16 MHz Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 o = 17.2032 MHz Error (%) 0.48 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 1.20 0.00 n 2 2 2 1 1 0 0 0 0 0 0 N 248 181 90 181 90 181 90 45 22 13 10 n N 64 191 95 191 95 191 95 47 23 14 11 n 3 2 2 1 1 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 n 3 2 2 1 1 0 0 0 0 0 0 N 75 223 111 223 111 223 111 55 27 16 13 -0.17 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -0.93 0 -0.93 0 0.00 -- 0 0 -1.70 0 0.00 0 o = 18 MHz Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 Error (%) o = 19.6608 MHz Error (%) 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 o = 20 MHz Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 n 3 2 2 1 1 0 0 0 0 0 0 N 79 233 116 233 116 233 116 58 28 17 14 n N 86 255 127 255 127 255 127 63 31 19 15 n 3 3 2 2 1 1 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 -0.12 3 0.16 0.16 0.16 0.16 0.16 0.16 2 2 1 1 0 0 -0.69 0 1.02 0.00 0 0 -1.70 0 0.00 0 -2.34 0 549 Table 13-4 BRR Settings for Various Bit Rates (Clocked Synchronous Mode) Bit Rate (bit/s) 110 250 500 1k 2.5 k 5k 10 k 25 k 50 k 100 k 250 k 500 k 1M 2.5 M 5M n 3 2 1 1 0 0 0 0 0 0 0 0 o = 2 MHz N 70 124 249 124 199 99 49 19 9 4 1 0* n -- 2 2 1 1 0 0 0 0 0 0 0 0 o = 4 MHz N -- 249 124 249 99 199 99 39 19 9 3 1 0* 3 2 2 1 1 0 0 0 0 0 0 0 -- 124 249 124 199 99 199 79 39 19 7 3 1 -- -- -- -- 1 1 0 0 0 0 0 0 -- 0 -- -- -- 249 124 249 99 49 24 9 4 -- 0* 3 3 2 2 1 1 0 0 0 0 0 0 -- -- 249 124 249 99 199 99 159 79 39 15 7 3 -- -- -- -- 2 1 1 0 0 0 0 0 0 0 0 -- -- 124 249 124 199 99 49 19 9 4 1 0* n o = 8 MHz N n o = 10 MHz N n o = 16 MHz N n o = 20 MHz N Note: As far as possible, the setting should be made so that the error is no more than 1%. Legend Blank : Cannot be set. -- : Can be set, but there will be a degree of error. * : Continuous transfer is not possible. 550 The BRR setting is found from the following formulas. Asynchronous mode: N= o 64 x 2 2n-1 xB x 10 6 - 1 Clocked synchronous mode: N= o 8x2 2n-1 xB x 10 6 - 1 Where B: N: o: n: Bit rate (bit/s) BRR setting for baud rate generator (0 N 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.) SMR Setting n 0 1 2 3 Clock o o/4 o/16 o/64 CKS1 0 0 1 1 CKS0 0 1 0 1 The bit rate error in asynchronous mode is found from the following formula: Error (%) = { o x 106 (N + 1) x B x 64 x 22n-1 - 1} x 100 551 Table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 13-6 and 13-7 show the maximum bit rates with external clock input. Table 13-5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) o (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 Maximum Bit Rate (bit/s) 62500 65536 76800 93750 115200 125000 153600 156250 187500 192000 230400 250000 307200 312500 375000 384000 437500 460800 500000 537600 562500 614400 625000 n 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 552 Table 13-6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) o (MHz) 2 2.097152 2.4576 3 3.6864 4 4.9152 5 6 6.144 7.3728 8 9.8304 10 12 12.288 14 14.7456 16 17.2032 18 19.6608 20 External Input Clock (MHz) 0.5000 0.5243 0.6144 0.7500 0.9216 1.0000 1.2288 1.2500 1.5000 1.5360 1.8432 2.0000 2.4576 2.5000 3.0000 3.0720 3.5000 3.6864 4.0000 4.3008 4.5000 4.9152 5.0000 Maximum Bit Rate (bit/s) 31250 32768 38400 46875 57600 62500 76800 78125 93750 96000 115200 125000 153600 156250 187500 192000 218750 230400 250000 268800 281250 307200 312500 553 Table 13-7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode) o (MHz) 2 4 6 8 10 12 14 16 18 20 External Input Clock (MHz) 0.3333 0.6667 1.0000 1.3333 1.6667 2.0000 2.3333 2.6667 3.0000 3.3333 Maximum Bit Rate (bit/s) 333333.3 666666.7 1000000.0 1333333.3 1666666.7 2000000.0 2333333.3 2666666.7 3000000.0 3333333.3 554 13.2.9 Bit Smart Card Mode Register (SCMR) : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : SCMR selects LSB-first or MSB-first by means of bit SDIR. Except in the case of asynchronous mode 7-bit data, LSB-first or MSB-first can be selected regardless of the serial communication mode. The descriptions in this chapter refer to LSB-first transfer. For details of the other bits in SCMR, see 14.2.1, Smart Card Mode Register (SCMR). SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2--Smart Card Data Invert (SINV): When the smart card interface operates as a normal SCI, 0 should be written in this bit. Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): When the smart card interface operates as a normal SCI, 0 should be written in this bit. 555 13.2.10 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the corresponding bit of bits MSTP6 and MSTP5 is set to 1, SCI operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 6--Module Stop (MSTP6): Specifies the SCI channel 1 module stop mode. Bit 6 MSTP6 0 1 Description SCI channel 1 module stop mode cleared SCI channel 1 module stop mode set (Initial value) Bit 5--Module Stop (MSTP5): Specifies the SCI channel 0 module stop mode. Bit 5 MSTP5 0 1 Description SCI channel 0 module stop mode cleared SCI channel 0 module stop mode set (Initial value) 556 13.3 13.3.1 Operation Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or clocked synchronous mode and the transmission format is made using SMR as shown in table 13-8. The SCI clock is determined by a combination of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR, as shown in table 13-9. Asynchronous Mode * Data length: Choice of 7 or 8 bits * Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) * Detection of framing, parity, and overrun errors, and breaks, during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output When external clock is selected: A clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) Clocked Synchronous Mode * Transfer format: Fixed 8-bit data * Detection of overrun errors during reception * Choice of internal or external clock as SCI clock source When internal clock is selected: The SCI operates on the baud rate generator clock and a serial clock is output off-chip When external clock is selected: The on-chip baud rate generator is not used, and the SCI operates on the input serial clock 557 Table 13-8 SMR Settings and Serial Transfer Format Selection SMR Settings Bit 7 C/A 0 Bit 6 CHR 0 Bit 2 MP 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 0 1 -- -- 1 -- -- 1 -- -- -- 0 1 0 1 -- Clocked 8-bit data synchronous mode No Asynchronous mode (multiprocessor format) 8-bit data Yes No Yes 7-bit data No Mode Asynchronous mode Yes Data Length 8-bit data SCI Transfer Format Multi Processor Bit No Parity Bit No Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 7-bit data 1 bit 2 bits None Table 13-9 SMR and SCR Settings and SCI Clock Source Selection SMR Bit 7 C/A 0 SCR Setting Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 1 0 0 1 1 0 1 Clocked synchronous mode Internal Mode Asynchronous mode Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use SCK pin Outputs clock with same frequency as bit rate External Inputs clock with frequency of 16 times the bit rate Outputs serial clock External Inputs serial clock 558 13.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-2 shows the general format for asynchronous serial communication. In asynchronous serial communication, the transmission line is usually held in the mark state (high level). The SCI monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level). In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. Idle state (mark state) 1 Serial data 0 Start bit 1 bit LSB D0 D1 D2 D3 D4 D5 D6 MSB D7 0/1 Parity bit 1 bit, or none 1 1 1 Stop bit Transmit/receive data 7 or 8 bits 1 or 2 bits One unit of transfer data (character or frame) Figure 13-2 Data Format in Asynchronous Communication (Example with 8-Bit Data, Parity, Two Stop Bits) Data Transfer Format: Table 13-10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. 559 Table 13-10 Serial Transfer Formats (Asynchronous Mode) SMR Settings CHR 0 0 0 0 1 1 1 1 0 0 1 1 PE 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 0 1 0 1 0 1 0 1 0 1 0 1 1 S Serial Transfer Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP 11 12 8-bit data 8-bit data 8-bit data 8-bit data 7-bit data 7-bit data 7-bit data 7-bit data 8-bit data 8-bit data 7-bit data 7-bit data STOP S STOP STOP S P STOP S P STOP STOP S S STOP STOP S P STOP S P STOP STOP S MPB STOP S MPB STOP STOP S MPB STOP S MPB STOP STOP Legend S : Start bit STOP : Stop bit P : Parity bit MPB : Multiprocessor bit 560 Clock: Either an internal clock generated by the on-chip baud rate generator or an external clock input at the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used. When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3. 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 13-3 Relation between Output Clock and Transfer Data Phase (Asynchronous Mode) Data Transfer Operations: * SCI initialization (asynchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain. 561 Figure 13-4 shows a sample SCI initialization flowchart. Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made. [2] Set the data transfer format in SMR and SCMR. [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [4] Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits Figure 13-4 Sample SCI Initialization Flowchart 562 * Serial data transmission (asynchronous mode) Figure 13-5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] Read TDRE flag in SSR [2] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set DDR for the port corresponding to the TxD pin to 1, clear DR to 0, then clear the TE bit in SCR to 0. No TDRE=1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes Clear DR to 0 and set DDR to 1 [4] Clear TE bit in SCR to 0 Figure 13-5 Sample Serial Transmission Flowchart 563 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Parity bit or multiprocessor bit: One parity bit (even or odd parity), or one multiprocessor bit is output. A format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the "mark state" is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. 564 Figure 13-6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and request generated TDRE flag cleared to 0 in TXI interrupt service routine TXI interrupt request generated TEI interrupt request generated 1 frame Figure 13-6 Example of Operation in Transmission in Asynchronous Mode (Example with 8-Bit Data, Parity, One Stop Bit) 565 * Serial data reception (asynchronous mode) Figure 13-7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Initialization Start reception [1] [2] [3] Receive error processing and break detection: Read ORER, PER, and If a receive error occurs, read the [2] FER flags in SSR ORER, PER, and FER flags in SSR to identify the error. After performing the appropriate error Yes processing, ensure that the PERFERORER= 1 ORER, PER, and FER flags are [3] all cleared to 0. Reception cannot No Error processing be resumed if any of these flags (Continued on next page) are set to 1. In the case of a framing error, a break can be detected by reading the value of [4] Read RDRF flag in SSR the input port corresponding to the RxD pin. No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] SCI status check and receive data read : Read SSR and check that RDRF = 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] No All data received? Yes Clear RE bit in SCR to 0 [5] Serial reception continuation procedure: To continue serial reception, before the stop bit for the current frame is received, read the RDRF flag, read RDR, and clear the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by an RXI interrupt and the RDR value is read. Figure 13-7 Sample Serial Reception Data Flowchart 566 [3] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes No Break? Yes Framing error processing Clear RE bit in SCR to 0 No PER= 1 Yes Parity error processing Clear ORER, PER, and FER flags in SSR to 0 Figure 13-7 Sample Serial Reception Data Flowchart (cont) 567 In serial reception, the SCI operates as described below. [1] The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks. [a] Parity check: The SCI checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the O/E bit in SMR. [b] Stop bit check: The SCI checks whether the stop bit is 1. If there are two stop bits, only the first is checked. [c] Status check: The SCI checks whether the RDRF flag is 0, indicating that the receive data can be transferred from RSR to RDR. If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error* is detected in the error check, the operation is as shown in table 13-11. Note: * Subsequent receive operations cannot be performed when a receive error has occurred. Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a receive error interrupt (ERI) request is generated. 568 Table 13-11 Receive Errors and Conditions for Occurrence Receive Error Overrun error Abbreviation ORER Occurrence Condition Data Transfer When the next data reception is Receive data is not completed while the RDRF flag transferred from RSR to RDR. in SSR is set to 1 When the stop bit is 0 Receive data is transferred from RSR to RDR. Framing error Parity error FER PER When the received data differs Receive data is transferred from the parity (even or odd) set from RSR to RDR. in SMR Figure 13-8 shows an example of the operation for reception in asynchronous mode. Start bit 0 D0 D1 Data D7 Parity Stop Start bit bit bit 0/1 1 0 D0 D1 Data D7 Parity Stop bit bit 0/1 0 1 1 Idle state (mark state) RDRF FER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ERI interrupt request generated by framing error 1 frame Figure 13-8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity, One Stop Bit) 569 13.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing transmission lines. When multiprocessor communication is carried out, each receiving station is addressed by a unique ID code. The serial communication cycle consists of two component cycles: an ID transmission cycle which specifies the receiving station , and a data transmission cycle. The multiprocessor bit is used to differentiate between the ID transmission cycle and the data transmission cycle. The transmitting station first sends the ID of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added. The receiving station skips the data until data with a 1 multiprocessor bit is sent. When data with a 1 multiprocessor bit is received, the receiving station compares that data with its own ID. The station whose ID matches then receives the data sent next. Stations whose ID does not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this way, data communication is carried out among a number of processors. Figure 13-9 shows an example of inter-processor communication using the multiprocessor format. Data Transfer Format: There are four data transfer formats. When the multiprocessor format is specified, the parity bit specification is invalid. For details, see table 13-10. Clock: See the section on asynchronous mode. 570 Transmitting station Serial transmission line Receiving station A (ID= 01) Serial data Receiving station B (ID= 02) Receiving station C (ID= 03) Receiving station D (ID= 04) H'01 (MPB= 1) ID transmission cycle= receiving station specification H'AA (MPB= 0) Data transmission cycle= Data transmission to receiving station specified by ID Legend MPB: Multiprocessor bit Figure 13-9 Example of Inter-Processor Communication Using Multiprocessor Format (Transmission of Data H'AA to Receiving Station A) Data Transfer Operations: * Multiprocessor serial data transmission Figure 13-10 shows a sample flowchart for multiprocessor serial data transmission. The following procedure should be used for multiprocessor serial data transmission. 571 Initialization Start transmission [1] [1] SCI initialization: Read TDRE flag in SSR [2] The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR. Set the MPBT bit in SSR to 0 or 1. Finally, clear the TDRE flag to 0. No TDRE= 1 Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No TEND= 1 Yes No Break output? Yes [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is [3] possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request, and data is written to TDR. [4] Break output at the end of serial transmission: To output a break in serial transmission, set the port DDR to [4] 1, clear DR to 0, then clear the TE bit in SCR to 0. Clear DR to 0 and set DDR to 1 Clear TE bit in SCR to 0 Figure 13-10 Sample Multiprocessor Serial Transmission Flowchart 572 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. The serial transmit data is sent from the TxD pin in the following order. [a] Start bit: One 0-bit is output. [b] Transmit data: 8-bit or 7-bit data is output in LSB-first order. [c] Multiprocessor bit One multiprocessor bit (MPBT value) is output. [d] Stop bit(s): One or two 1-bits (stop bits) are output. [e] Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] The SCI checks the TDRE flag at the timing for sending the stop bit. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and then serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this time, a transmission end interrupt (TEI) request is generated. 573 Figure 13-11 shows an example of SCI operation for transmission using the multiprocessor format. Multiprocessor Stop bit bit D7 0/1 1 1 Start bit 0 D0 D1 Data Start bit 0 D0 D1 Data D7 Multiproces- Stop 1 sor bit bit 0/1 1 Idle state (mark state) TDRE TEND TXI interrupt request generated Data written to TDR and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 13-11 Example of SCI Operation in Transmission (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) * Multiprocessor serial data reception Figure 13-12 shows a sample flowchart for multiprocessor serial reception. The following procedure should be used for multiprocessor serial data reception. 574 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] ID reception cycle: Set the MPIE bit in SCR to 1. [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station's ID. If the data is not this station's ID, set the MPIE bit to 1 again, and clear the RDRF flag to 0. If the data is this station's ID, clear the RDRF flag to 0. [4] SCI status check and data reception: Read SSR and check that the RDRF flag is set to 1, then read the data in RDR. [5] Receive error processing and break detection: If a receive error occurs, read the ORER and FER flags in SSR to identify the error. After performing the appropriate error processing, ensure that the ORER and FER flags are both cleared to 0. Reception cannot be resumed if either of these flags is set to 1. In the case of a framing error, a break can be detected by reading the RxD pin value. Read MPIE bit in SCR Read ORER and FER flags in SSR [2] Yes FERORER= 1 No Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR No This station's ID? Yes Read ORER and FER flags in SSR Yes FERORER= 1 No Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR No All data received? Yes Clear RE bit in SCR to 0 [5] Error processing (Continued on next page) Figure 13-12 Sample Multiprocessor Serial Reception Flowchart 575 [5] Error processing No ORER= 1 Yes Overrun error processing No FER= 1 Yes Yes Break? No Framing error processing Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 13-12 Sample Multiprocessor Serial Reception Flowchart (cont) Figure 13-13 shows an example of SCI operation for multiprocessor format reception. 576 1 Start bit 0 D0 D1 Data (ID1) MPB D7 1 Stop bit 1 Start bit 0 D0 D1 Data (Data1) MPB D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID1 If not this station's ID, RXI interrupt request is not generated, and RDR MPIE bit is set to 1 retains its state again (a) Data does not match station's ID 1 Start bit 0 D0 D1 Data (ID2) MPB D7 1 Stop bit 1 Start bit 0 D0 Data (Data2) MPB D1 D7 0 Stop bit 1 1 Idle state (mark state) MPIE RDRF RDR value ID1 MPIE = 0 RXI interrupt request (multiprocessor interrupt) generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine ID2 Matches this station's ID, so reception continues, and data is received in RXI interrupt service routine Data2 MPIE bit set to 1 again (b) Data matches station's ID Figure 13-13 Example of SCI Operation in Reception (Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit) 577 13.3.4 Operation in Clocked Synchronous Mode In clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. Both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. Figure 13-14 shows the general format for clocked synchronous serial communication. One unit of transfer data (character or frame) * Serial clock LSB Serial data Don't care Note: * High except in continuous transfer Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Figure 13-14 Data Format in Synchronous Communication In clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. Data confirmation is guaranteed at the rising edge of the serial clock. In clocked serial communication, one character consists of data output starting with the LSB and ending with the MSB. After the MSB is output, the transmission line holds the MSB state. In clocked synchronous mode, the SCI receives data in synchronization with the rising edge of the serial clock. Data Transfer Format: A fixed 8-bit data format is used. No parity or multiprocessor bits are added. Clock: Either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 13-9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. When only receive operations are performed, however, the 578 serial clock is output until an overrun error occurs or the RE bit is cleared to 0. If you want to perform receive operations in units of one character, you should select an external clock as the clock source. Data Transfer Operations: * SCI initialization (clocked synchronous mode) Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then initialize the SCI as described below. When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. Figure 13-15 shows a sample SCI initialization flowchart. Start initialization Clear TE and RE bits in SCR to 0 [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR Set value in BRR Wait [3] Write a value corresponding to the bit rate to BRR. Not necessary if an external clock is used. [4] Wait at least one bit interval, then set the TE bit or RE bit in SCR to 1. Also set the RIE, TIE, TEIE, and MPIE bits. Setting the TE and RE bits enables the TxD and RxD pins to be used. [2] [3] No 1-bit interval elapsed? Yes Set TE and RE bits in SCR to 1, and set RIE, TIE, TEIE, and MPIE bits [4] Figure 13-15 Sample SCI Initialization Flowchart 579 * Serial data transmission (clocked synchronous mode) Figure 13-16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization Start transmission [1] [1] SCI initialization: The TxD pin is automatically designated as the transmit data output pin. [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. [3] Serial transmission continuation procedure: To continue serial transmission, be sure to read 1 from the TDRE flag to confirm that writing is possible, then write data to TDR, and then clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Read TDRE flag in SSR [2] No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 No All data transmitted? Yes [3] Read TEND flag in SSR No TEND= 1 Yes Clear TE bit in SCR to 0 Figure 13-16 Sample Serial Transmission Flowchart 580 In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated. When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an external clock has been specified, data is output synchronized with the input clock. The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with the MSB (bit 7). [3] The SCI checks the TDRE flag at the timing for sending the MSB (bit 7). If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission of the next frame is started. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the TxD pin maintains its state. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request is generated. [4] After completion of serial transmission, the SCK pin is fixed. Figure 13-17 shows an example of SCI operation in transmission. 581 Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt Data written to TDR request generated and TDRE flag cleared to 0 in TXI interrupt service routine 1 frame TXI interrupt request generated TEI interrupt request generated Figure 13-17 Example of SCI Operation in Transmission * Serial data reception (clocked synchronous mode) Figure 13-18 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. When changing the operating mode from asynchronous to clocked synchronous, be sure to check that the ORER, PER, and FER flags are all cleared to 0. The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive operations will be possible. 582 Initialization Start reception [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. Read ORER flag in SSR Yes ORER= 1 No [2] [3] Error processing (Continued below) [2] [3] Receive error processing: If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. [5] Serial reception continuation procedure: To continue serial reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. The RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. Read RDRF flag in SSR [4] No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit in SCR to 0 Error processing Overrun error processing Clear ORER flag in SSR to 0 Figure 13-18 Sample Serial Reception Flowchart 583 In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a receive error is detected in the error check, the operation is as shown in table 13-11. Neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive data full interrupt (RXI) request is generated. Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive error interrupt (ERI) request is generated. Figure 13-19 shows an example of SCI operation in reception. Serial clock Serial data RDRF ORER RXI interrupt request generated RDR data read and RDRF flag cleared to 0 in RXI interrupt service routine 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 Figure 13-19 Example of SCI Operation in Reception * Simultaneous serial data transmission and reception (clocked synchronous mode) Figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations. The following procedure should be used for simultaneous serial data transmit and receive operations. 584 Initialization Start transmission/reception [1] [1] SCI initialization: The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Read TDRE flag in SSR No TDRE= 1 Yes Write transmit data to TDR and clear TDRE flag in SSR to 0 [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0. Transition of the TDRE flag from 0 to 1 can also be identified by a TXI interrupt. [3] Receive error processing: Read ORER flag in SSR Yes [3] Error processing ORER= 1 No If a receive error occurs, read the ORER flag in SSR , and after performing the appropriate error processing, clear the ORER flag to 0. Transmission/reception cannot be resumed if the ORER flag is set to 1. [4] SCI status check and receive data read: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and clear the RDRF flag to 0. Transition of the RDRF flag from 0 to 1 can also be identified by an RXI interrupt. Read RDRF flag in SSR No RDRF= 1 Yes Read receive data in RDR, and clear RDRF flag in SSR to 0 [4] [5] Serial transmission/reception continuation procedure: To continue serial transmission/ reception, before the MSB (bit 7) of the current frame is received, finish reading the RDRF flag, reading RDR, and clearing the RDRF flag to 0. Also, before the MSB (bit 7) of the current frame is transmitted, read 1 from the TDRE flag to confirm that writing is possible. Then write data to TDR and clear the TDRE flag to 0. Checking and clearing of the TDRE flag is automatic when the DMAC or DTC is activated by a transmit data empty interrupt (TXI) request and data is written to TDR. Also, the RDRF flag is cleared automatically when the DMAC or DTC is activated by a receive data full interrupt (RXI) request and the RDR value is read. No All data received? Yes [5] Clear TE and RE bits in SCR to 0 Figure 13-20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations 585 13.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 13-12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR. Each kind of interrupt request is sent to the interrupt controller independently. When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DMAC or DTC to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. The DMAC and DTC cannot be activated by a TEI interrupt request. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER, PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt can activate the DMAC or DTC to perform data transfer. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. The DMAC and DTC cannot be activated by an ERI interrupt request. 586 Table 13-12 SCI Interrupt Sources Channel 0 Interrupt Source Description ERI RXI TXI TEI 1 ERI RXI TXI TEI Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) Interrupt due to receive error (ORER, FER, or PER) Interrupt due to receive data full state (RDRF) Interrupt due to transmit data empty state (TDRE) Interrupt due to transmission end (TEND) DTC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible DMAC Activation Not possible Possible Possible Not possible Not possible Possible Possible Not possible Priority* High Low Note: * This table shows the initial state immediately after a reset. Relative priorities among channels can be changed by means of the interrupt controller. A TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a TXI interrupt are requested simultaneously, the TXI interrupt may have priority for acceptance, with the result that the TDRE and TEND flags are cleared. Note that the TEI interrupt will not be accepted in this case. 587 13.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1 before writing transmit data to TDR. Operation when Multiple Receive Errors Occur Simultaneously If a number of receive errors occur at the same time, the state of the status flags in SSR is as shown in table 13-13. If there is an overrun error, data is not transferred from RSR to RDR, and the receive data is lost. Table 13-13 State of SSR Status Flags and Transfer of Receive Data SSR Status Flags RDRF 1 0 0 1 1 0 1 Notes: ORER 1 0 0 1 1 0 1 FER 0 1 0 1 0 1 1 PER 0 0 1 0 1 1 1 X X X Receive Data Transfer RSR to RDR X Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error : Receive data is transferred from RSR to RDR. X: Receive data is not transferred from RSR to RDR. 588 Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again. Sending a Break (Asynchronous Mode Only): The TxD pin has a dual function as an I/O port whose direction (input or output) is determined by DR and DDR. This can be used to send a break. Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1). Consequently, DDR and DR for the port corresponding to the TxD pin are first set to 1. To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0. When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin. Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only): Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0. Receive Data Sampling Timing and Reception Margin in Asynchronous Mode: In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the basic clock. This is illustrated in figure 13-21. 589 16 clocks 8 clocks 0 Internal basic clock 7 15 0 7 15 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 13-21 Receive Data Sampling Timing in Asynchronous Mode Thus the reception margin in asynchronous mode is given by formula (1) below. M = | (0.5 - 1 2N ) - (L - 0.5) F - | D - 0.5 | N ... Formula (1) Where M N D L F : Reception margin (%) : Ratio of bit rate to clock (N = 16) : Clock duty (D = 0 to 1.0) : Frame length (L = 9 to 12) : Absolute value of clock rate deviation (1 + F) | x 100% Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. When D = 0.5 and F = 0, M = (0.5 - 1 2 x 16 ) x 100% = 46.875% ... Formula (2) However, this is only the computed value, and a margin of 20% to 30% should be allowed in system design. 590 Restrictions on Use of DMAC or DTC * When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 o clock cycles after TDR is updated by the DMAC or DTC. Misoperation may occur if the transmit clock is input within 4 o clocks after TDR is updated. (Figure 13-22) * When RDR is read by the DMAC or DTC, be sure to set the activation source to the relevant SCI reception end interrupt (RXI). SCK t TDRE LSB Serial data D0 D1 D2 D3 D4 D5 D6 D7 Note: When operating on an external clock, set t >4 clocks. Figure 13-22 Example of Clocked Synchronous Transmission by DTC 591 592 Section 14 Smart Card Interface 14.1 Overview SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as a serial communication interface extension function. Switching between the normal serial communication interface and the Smart Card interface is carried out by means of a register setting. 14.1.1 Features Features of the Smart Card interface supported by the H8S/2357 are as follows. * Asynchronous mode Data length: 8 bits Parity bit generation and checking Transmission of error signal (parity error) in receive mode Error signal detection and automatic data retransmission in transmit mode Direct convention and inverse convention both supported * On-chip baud rate generator allows any bit rate to be selected * Three interrupt sources Three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently The transmit data empty interrupt and receive data full interrupt can activate the DMA controller (DMAC) or data transfer controller (DTC) to execute data transfer 593 14.1.2 Block Diagram Figure 14-1 shows a block diagram of the Smart Card interface. Bus interface Module data bus Internal data bus RDR TDR RxD RSR TSR SCMR SSR SCR SMR Transmission/ reception control BRR o Baud rate generator o/4 o/16 o/64 Clock TxD Parity generation Parity check SCK TXI RXI ERI : Smart Card mode register : Receive shift register : Receive data register : Transmit shift register : Transmit data register : Serial mode register : Serial control register : Serial status register : Bit rate register Legend SCMR RSR RDR TSR TDR SMR SCR SSR BRR Figure 14-1 Block Diagram of Smart Card Interface 594 14.1.3 Pin Configuration Table 14-1 shows the Smart Card interface pin configuration. Table 14-1 Smart Card Interface Pins Channel 0 Pin Name Serial clock pin 0 Receive data pin 0 Transmit data pin 0 1 Serial clock pin 1 Receive data pin 1 Transmit data pin 1 Symbol SCK0 RxD0 TxD0 SCK1 RxD1 TxD1 I/O I/O Input Output I/O Input Output Function SCI0 clock input/output SCI0 receive data input SCI0 transmit data output SCI1 clock input/output SCI1 receive data input SCI1 transmit data output 595 14.1.4 Register Configuration Table 14-2 shows the registers used by the Smart Card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface. Table 14-2 Smart Card Interface Registers Channel 0 Name Serial mode register 0 Bit rate register 0 Serial control register 0 Transmit data register 0 Serial status register 0 Receive data register 0 Smart card mode register 0 1 Serial mode register 1 Bit rate register 1 Serial control register 1 Transmit data register 1 Serial status register 1 Receive data register 1 Smart card mode register 1 All Module stop control register Abbreviation SMR0 BRR0 SCR0 TDR0 SSR0 RDR0 SCMR0 SMR1 BRR1 SCR1 TDR1 SSR1 RDR1 SCMR1 MSTPCR R/W R/W R/W R/W R/W R/(W)* R R/W R/W R/W R/W R/W R/(W)* R R/W R/W 2 2 Initial Value H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'00 H'FF H'00 H'FF H'84 H'00 H'F2 H'3FFF Address* 1 H'FF78 H'FF79 H'FF7A H'FF7B H'FF7C H'FF7D H'FF7E H'FF80 H'FF81 H'FF82 H'FF83 H'FF84 H'FF85 H'FF86 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Can only be written with 0 for flag clearing. 596 14.2 Register Descriptions Registers added with the Smart Card interface and bits for which the function changes are described here. 14.2.1 Bit Smart Card Mode Register (SCMR) : 7 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W 2 SINV 0 R/W 1 -- 1 -- 0 SMIF 0 R/W Initial value : R/W : 1 -- SCMR is an 8-bit readable/writable register that selects the Smart Card interface function. SCMR is initialized to H'F2 by a reset, and in standby mode or module stop mode. Bits 7 to 4--Reserved: Read-only bits, always read as 1. Bit 3--Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. Bit 3 SDIR 0 Description TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first (Initial value) Bit 2--Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 14.3.4, Register Settings. Bit 2 SINV 0 Description TDR contents are transmitted as they are Receive data is stored as it is in RDR 1 TDR contents are inverted before being transmitted Receive data is stored in inverted form in RDR (Initial value) 597 Bit 1--Reserved: Read-only bit, always read as 1. Bit 0--Smart Card Interface Mode Select (SMIF): Enables or disables the Smart Card interface function. Bit 0 SMIF 0 1 Description Smart Card interface function is disabled Smart Card interface function is enabled (Initial value) 14.2.2 Bit Serial Status Register (SSR) : 7 TDRE 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R 1 MPB 0 R 0 MPBT 0 R/W Initial value : R/W : 1 R/(W)* Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in Smart Card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different. Bits 7 to 5--Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). Bit 4--Error Signal Status (ERS): In Smart Card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. Framing errors are not detected in Smart Card interface mode. Bit 4 ERS 0 Description [Clearing condition] * * 1 Upon reset, and in standby mode or module stop mode When 0 is written to ERS after reading ERS = 1 (Initial value) [Setting condition] When the low level of the error signal is sampled Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its previous state. 598 Bits 3 to 0--Operate in the same way as for the normal SCI. For details, see section 13.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below. Bit 2 TEND 0 Description [Clearing conditions] * * 1 * * * * When 0 is written to TDRE after reading TDRE = 1 When the DMAC or DTC is activated by a TXI interrupt and write data to TDR (Initial value) [Setting conditions] Upon reset, and in standby mode or module stop mode When the TE bit in SCR is 0 and the ERS bit is also 0 When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when GM = 0 When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when GM = 1 Note: etu: Elementary Time Unit (time for transfer of 1 bit) 14.2.3 Bit Serial Mode Register (SMR) : 7 GM 6 CHR 0 0 R/W 5 PE 0 1 R/W 4 O/E 0 O/E R/W 3 STOP 0 1 R/W 2 MP 0 0 R/W 1 CKS1 0 CKS1 R/W 0 CKS0 0 CKS0 R/W Initial value : Set value* : R/W : 0 GM R/W Note: * When the smart card interface is used, be sure to make the 0 or 1 setting shown for bits 6, 5, 3, and 2. The function of bit 7 of SMR changes in smart card interface mode. Bit 7--GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used. In GSM mode, this bit is set to 1, the timing of setting of the TEND flag that indicates transmission completion is advanced and clock output control mode addition is performed. The contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (SCR). 599 Bit 7 GM 0 Description Normal smart card interface mode operation * * TEND flag generation 12.5 etu after beginning of start bit Clock output ON/OFF control only (Initial value) 1 GSM mode smart card interface mode operation * * TEND flag generation 11.0 etu after beginning of start bit High/low fixing control possible in addition to clock output ON/OFF control (set by SCR) Note: etu: Elementary time unit (time for transfer of 1 bit) Bits 6 to 0--Operate in the same way as for the normal SCI. For details, see section 13.2.5, Serial Mode Register (SMR). 14.2.4 Bit Serial Control Register (SCR) : 7 TIE 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W 1 CKE1 0 R/W 0 CKE0 0 R/W Initial value : R/W : 0 R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2--Operate in the same way as for the normal SCI. For details, see section 13.2.6, Serial Control Register (SCR). Bits 1 and 0--Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock source and enable or disable clock output from the SCK pin. In smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. 600 SCMR SMIF 0 1 1 1 1 1 1 SMR C/A, GM See the SCI 0 0 1 1 1 1 0 0 0 0 1 1 SCR Setting CKE1 CKE0 SCK Pin Function 0 1 0 1 0 1 Operates as port I/O pin Outputs clock as SCK output pin Operates as SCK output pin, with output fixed low Outputs clock as SCK output pin Operates as SCK output pin, with output fixed high Outputs clock as SCK output pin 14.3 14.3.1 Operation Overview The main functions of the Smart Card interface are as follows. * * * * * One frame consists of 8-bit data plus a parity bit. In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of one bit) is left between the end of the parity bit and the start of the next frame. If a parity error is detected during reception, a low error signal level is output for one etu period, 10.5 etu after the start bit. If the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. Only asynchronous communication is supported; there is no clocked synchronous communication function. 601 14.3.2 Pin Connections Figure 14-2 shows a schematic diagram of Smart Card interface related pin connections. In communication with an IC card, since both transmission and reception are carried out on a single data transmission line, the TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be pulled up to the VCC power supply with a resistor. When the clock generated on the Smart Card interface is used by an IC card, the SCK pin output is input to the CLK pin of the IC card. No connection is needed if the IC card uses an internal clock. LSI port output is used as the reset signal. Other pins must normally be connected to the power supply or ground. VCC TxD I/O RxD SCK Rx (port) H8S/2350 Connected equipment Data line Clock line Reset line CLK RST IC card Figure 14-2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. 602 14.3.3 Data Format Figure 14-3 shows the Smart Card interface data format. In reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted. When there is no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output When a parity error occurs Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Legend Ds D0 to D7 Dp DE Receiving station output : Start bit : Data bits : Parity bit : Error signal Figure 14-3 Smart Card Interface Data Format 603 The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the Smart Card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor. [4] The receiving station carries out a parity check. If there is no parity error and the data is received normally, the receiving station waits for reception of the next data. If a parity error occurs, however, the receiving station outputs an error signal (DE, low-level) to request retransmission of the data. After outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. The signal line is pulled high again by a pull-up resistor. [5] If the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. If it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. 604 14.3.4 Register Settings Table 14-3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 14-3 Smart Card Interface Register Settings Bit Register SMR BRR SCR TDR SSR RDR SCMR Bit 7 GM BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1* TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF Notes: -- : Unused bit. *: The CKE1 bit must be cleared to 0 when the GM bit in SMR is cleared to 0. SMR Setting: The GM bit is cleared to 0 in normal smart card interface mode, and set to 1 in GSM mode. The O/E bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. Bits CKS1 and CKS0 select the clock source of the on-chip baud rate generator. See section 14.3.5, Clock. BRR Setting: BRR is used to set the bit rate. See section 14.3.5, Clock, for the method of calculating the value to be set. SCR Setting: The function of the TIE, RIE, TE, and RE bits is the same as for the normal SCI. For details, see section 13, Serial Communication Interface. Bits CKE1 and CKE0 specify the clock output. When the GM bit in SMR is cleared to 0, set these bits to B'00 if a clock is not to be output, or to B'01 if a clock is to be output. When the GM bit in SMR is set to 1, clock output is performed. The clock output can also be fixed high or low. 605 Smart Card Mode Register (SCMR) Setting: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 in the case of the Smart Card interface. Examples of register settings and the waveform of the start character are shown below for the two types of IC card (direct convention and inverse convention). * Direct convention (SDIR = SINV = O/E = 0) (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State With the direct convention type, the logic 1 level corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order. The start character data above is H'3B. The parity bit is 1 since even parity is stipulated for the Smart Card. * Inverse convention (SDIR = SINV = O/E = 1) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. The parity bit is 0, corresponding to state Z, since even parity is stipulated for the Smart Card. With the H8S/2357, inversion specified by the SINV bit applies only to the data bits, D7 to D0. For parity bit inversion, the O/E bit in SMR is set to odd parity mode (the same applies to both transmission and reception). 606 14.3.5 Clock Only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1 and CKS0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 14-5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, a clock with a frequency of 372 times the bit rate is output from the SCK pin. B= o 1488 x 2 2n-1 x (N + 1) x 10 6 Where: N = Value set in BRR (0 N 255) B = Bit rate (bit/s) o = Operating frequency (MHz) n = See table 14-4 Table 14-4 Correspondence between n and CKS1, CKS0 n 0 1 2 3 1 CKS1 0 CKS0 0 1 0 1 Table 14-5 Examples of Bit Rate B (bit/s) for Various BRR Settings (When n = 0) o (MHz) N 0 1 2 10.00 13441 6720 4480 10.714 14400 7200 4800 13.00 17473 8737 5824 14.285 19200 9600 6400 16.00 21505 10753 7168 18.00 24194 12097 8065 20.00 26882 13441 8961 Note: Bit rates are rounded to the nearest whole number. 607 The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 N 255, and the smaller error is specified. N= o 1488 x 2 2n-1 xB x 10 6 - 1 Table 14-6 Examples of BRR Settings for Bit Rate B (bit/s) (When n = 0) o (MHz) 7.1424 bit/s 9600 N Error 0 0.00 10.00 N Error 1 30 10.7136 13.00 14.2848 16.00 N Error 1 18.00 N Error 20.00 N Error 6.60 N Error N Error N Error 1 25 1 8.99 1 0.00 12.01 2 15.99 2 Table 14-7 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode) o (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 Maximum Bit Rate (bit/s) 9600 13441 14400 17473 19200 21505 24194 26882 N 0 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 0 The bit rate error is given by the following formula: Error (%) = ( o 1488 x 2 2n-1 x B x (N + 1) x 106 - 1) x 100 608 14.3.6 Data Transfer Operations Initialization: Before transmitting and receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the O/E bit and CKS1 and CKS0 bits in SMR. Clear the C/A, CHR, and MP bits to 0, and set the STOP and PE bits to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR. When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins, and are placed in the high-impedance state. [5] Set the value corresponding to the bit rate in BRR. [6] Set the CKE0 bit in SCR. Clear the TIE, RIE, TE, RE, MPIE, TEIE and CKE1 bits to 0. If the CKE0 bit is set to 1, the clock is output from the SCK pin. [7] Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE bit and RE bit at the same time, except for self-diagnosis. 609 Serial Data Transmission: As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ERS error flag in SSR is cleared to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the TEND flag in SSR is set to 1. [4] Write the transmit data to TDR, clear the TDRE flag to 0, and perform the transmit operation. The TEND flag is cleared to 0. [5] When transmitting data continuously, go back to step [2]. [6] To end transmission, clear the TE bit to 0. With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If transmission ends and the TEND flag is set to 1 while the TIE bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (TXI) request will be generated. If an error occurs in transmission and the ERS flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (ERI) request will be generated. The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND flag set timing is shown in figure 14-6. If the DMAC or DTC is activated by a TXI request, the number of bytes set in the DMAC or DTC can be transmitted automatically, including automatic retransmission. For details, see Interrupt Operations and Data Transfer Operation by DMAC or DTC below. 610 Start Initialization Start transmission ERS=0? Yes No Error processing No TEND=1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS=0? Yes Error processing No TEND=1? Yes Clear TE bit to 0 End Figure 14-4 Example of Transmission Processing Flow 611 TDR (1) Data write (2) Transfer from TDR to TSR (3) Serial data output Data 1 Data 1 Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmission) of the next transfer data to be transmitted has been completed. Figure 14-5 Relation Between Transmit Operation and Internal Registers I/O data TXI (TEND interrupt) When GM = 0 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Guard time 12.5etu When GM = 1 11.0etu Legend Ds D0 to D7 Dp DE : Start bit : Data bits : Parity bit : Error signal Figure 14-6 TEND Flag Generation Timing in Transmission Operation 612 Serial Data Reception: Data reception in Smart Card mode uses the same processing procedure as for the normal SCI. Figure 14-7 shows an example of the transmission processing flow. [1] Perform Smart Card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0. If either is set, perform the appropriate receive error processing, then clear both the ORER and the PER flag to 0. [3] Repeat steps [2] and [3] until it can be confirmed that the RDRF flag is set to 1. [4] Read the receive data from RDR. [5] When receiving data continuously, clear the RDRF flag to 0 and go back to step [2]. [6] To end reception, clear the RE bit to 0. Start Initialization Start reception ORER = 0 and PER = 0 Yes No Error processing No RDRF=1? Yes Read RDR and clear RDRF flag in SSR to 0 No All data received? Yes Clear RE bit to 0 Figure 14-7 Example of Reception Processing Flow 613 With the above processing, interrupt servicing or data transfer by the DMAC or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transfer error interrupt (ERI) request will be generated. If the DMAC or DTC is activated by an RXI request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the DMAC or DTC are transferred. For details, see Interrupt Operation and Data Transfer Operation by DMAC or DTC below. If a parity error occurs during reception and the PER is set to 1, the received data is still transferred to RDR, and therefore this data can be read. Mode Switching Operation: When switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing RE bit to 0 and setting TE bit to 1. The RDRF flag or the PER and ORER flags can be used to check that the receive operation has been completed. When switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing TE bit to 0 and setting RE bit to 1. The TEND flag can be used to check that the transmit operation has been completed. Fixing Clock Output Level: When the GSM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width. Figure 14-8 shows the timing for fixing the clock output level. In this example, GSM is set to 1, CKE1 is cleared to 0, and the CKE0 bit is controlled. Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 14-8 Timing for Fixing Clock Output Level Interrupt Operation: There are three interrupt sources in smart card interface mode: transmit data empty interrupt (TXI) requests, transfer error interrupt (ERI) requests, and receive data full interrupt (RXI) requests. The transmit end interrupt (TEI) request is not used in this mode. 614 When the TEND flag in SSR is set to 1, a TXI interrupt request is generated. When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When any of flags ORER, PER, and ERS in SSR is set to 1, an ERI interrupt request is generated. The relationship between the operating states and interrupt sources is shown in table 14-8. Table 14-8 Smart Card Mode Operating States and Interrupt Sources Operating State Transmit Mode Normal operation Error Receive Mode Normal operation Error Flag TEND ERS RDRF PER, ORER Enable Bit TIE RIE RIE RIE Interrupt DMAC Source Activation TXI ERI RXI ERI Possible DTC Activation Possible Not possible Not possible Possible Possible Not possible Not possible Data Transfer Operation by DMAC or DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0 when data transfer is performed by the DMAC or DTC. In the event of an error, the SCI retransmits the same data automatically. The TEND flag remains cleared to 0 during this time, and the DMAC is not activated. Thus, the number of bytes specified by the SCI and DMAC are transmitted automatically even in retransmission following an error. However, the ERS flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will be cleared. When performing transfer using the DMAC or DTC, it is essential to set and enable the DMAC or DTC before carrying out SCI setting. For details of the DMAC and DTC setting procedures, see section 7, DMA Controller (DMAC), and section 8, Data Transfer Controller (DTC). In a receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If the RXI request is designated beforehand as a DMAC or DTC activation source, the DMAC or DTC will be activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared to 0 automatically when data transfer is performed by the DMAC or DTC. If an error occurs, an error flag is set but the RDRF flag is not. Consequently, the DMAC or DTC is not activated, but instead, an ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared. 615 14.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. * When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode. [2] Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive operation. At the same time, set the CKE1 bit to the value for the fixed output state in software standby mode. [3] Write 0 to the CKE0 bit in SCR to halt the clock. [4] Wait for one serial clock period. During this interval, clock output is fixed at the specified level, with the duty preserved. [5] Write H'00 to SMR and SCMR. [6] Make the transition to the software standby state. * When returning to smart card interface mode from software standby mode [7] Exit the software standby state. [8] Set the CKE1 bit in SCR to the value for the fixed output state (current SCK pin state) when software standby mode is initiated. [9] Set smart card interface mode and output the clock. Signal generation is started with the normal duty. Software standby Normal operation Normal operation [1] [2] [3] [4] [5] [6] [7] [8] [9] Figure 14-9 Clock Halt and Restart Procedure 616 Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 14.4 Usage Notes The following points should be noted when using the SCI as a Smart Card interface. Receive Data Sampling Timing and Reception Margin in Smart Card Interface Mode: In Smart Card Interface mode, the SCI operates on a basic clock with a frequency of 372 times the transfer rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs internal synchronization. Receive data is latched internally at the rising edge of the 186th pulse of the basic clock. This is illustrated in figure 14-10. 372 clocks 186 clocks 0 185 371 0 185 371 0 Internal basic clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14-10 Receive Data Sampling Timing in Smart Card Mode 617 Thus the reception margin in asynchronous mode is given by the following formula. M = (0.5 - 1 2N ) - (L - 0.5) F - D - 0.5 N (1 + F) x 100% Where M: Reception margin (%) N: Ratio of bit rate to clock (N = 372) D: Clock duty (D = 0 to 1.0) L: Frame length (L = 10) F: Absolute value of clock frequency deviation Assuming values of F = 0 and D = 0.5 in the above formula, the reception margin formula is as follows. When D = 0.5 and F = 0, M = (0.5 - 1/2 x 372) x 100% = 49.866% Retransfer Operations: Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. * Retransfer operation when SCI is in receive mode Figure 14-11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [2] The RDRF bit in SSR is not set for a frame in which an error has occurred. [3] If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1. [4] If no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the RDRF flag in SSR is automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is generated. If DMAC or DTC data transfer by an RXI source is enabled, the contents of RDR can be read automatically. When the RDR data is read by the DMAC or DTC, the RDRF flag is automatically cleared to 0. [5] When a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission. 618 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF [2] PER [1] Retransferred frame Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 [4] [3] Figure 14-11 Retransfer Operation in SCI Receive Mode * Retransfer operation when SCI is in transmit mode Figure 14-12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled. [7] The TEND bit in SSR is not set for a frame for which an error signal indicating an abnormality is received. [8] If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set. [9] If an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt request is generated. If data transfer by the DMAC or DTC by means of the TXI source is enabled, the next data can be written to TDR automatically. When data is written to TDR by the DMAC or DTC, the TDRE bit is automatically cleared to 0. Transfer frame n+1 (DE) Ds D0 D1 D2 D3 D4 nth transfer frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE TDRE Transfer to TSR from TDR TEND [7] FER/ERS [6] Retransferred frame Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transfer to TSR from TDR Transfer to TSR from TDR [9] [8] Figure 14-12 Retransfer Operation in SCI Transmit Mode 619 620 Section 15 A/D Converter 15.1 Overview The H8S/2350 Series incorporates a successive approximation type 10-bit A/D converter that allows up to eight analog input channels to be selected. 15.1.1 Features A/D converter features are listed below * 10-bit resolution * Eight input channels * Settable analog conversion voltage range Conversion of analog voltages with the reference voltage pin (Vref ) as the analog reference voltage * High-speed conversion Minimum conversion time: 6.7 s per channel (at 20 MHz operation) * Choice of single mode or scan mode Single mode: Single-channel A/D conversion Scan mode: Continuous A/D conversion on 1 to 4 channels * Four data registers Conversion results are held in a 16-bit data register for each channel * Sample and hold function * Three kinds of conversion start Choice of software or timer conversion start trigger (TPU), or ADTRG pin * A/D conversion end interrupt generation A/D conversion end interrupt (ADI) request can be generated at the end of A/D conversion * Module stop mode can be set As the initial setting, A/D converter operation is halted. Register access is enabled by exiting module stop mode. 621 15.1.2 Block Diagram Figure 15-1 shows a block diagram of the A/D converter. Module data bus Bus interface A D D R A A D D R B A D D R C A D D R D A D C S R A D C R + Multiplexer - Comparator Sample-andhold circuit Control circuit Internal data bus AVCC Vref AVSS 10-bit D/A AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 Successive approximations register o/8 o/16 ADI interrupt ADTRG Conversion start trigger from TPU ADCR : A/D control register ADCSR : A/D control/status register ADDRA : A/D data register A ADDRB : A/D data register B ADDRC : A/D data register C ADDRD : A/D data register D Figure 15-1 Block Diagram of A/D Converter 622 15.1.3 Pin Configuration Table 15-1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 15-1 A/D Converter Pins Pin Name Analog power supply pin Analog ground pin Reference voltage pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 Analog input pin 4 Analog input pin 5 Analog input pin 6 Analog input pin 7 Symbol AVCC AVSS Vref AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 I/O Input Input Input Input Input Input Input Input Input Input Input Input External trigger input for starting A/D conversion Group 1 analog inputs Function Analog block power supply Analog block ground and A/D conversion reference voltage A/D conversion reference voltage Group 0 analog inputs A/D external trigger input pin ADTRG 623 15.1.4 Register Configuration Table 15-2 summarizes the registers of the A/D converter. Table 15-2 A/D Converter Registers Name A/D data register AH A/D data register AL A/D data register BH A/D data register BL A/D data register CH A/D data register CL A/D data register DH A/D data register DL A/D control/status register A/D control register Module stop control register Abbreviation ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR MSTPCR R/W R R R R R R R R R/(W)* R/W R/W 2 Initial Value H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'00 H'3F H'3FFF Address* 1 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FF3C Notes: 1. Lower 16 bits of the address. 2. Bit 7 can only be written with 0 for flag clearing. 624 15.2 15.2.1 Bit Register Descriptions A/D Data Registers A to D (ADDRA to ADDRD) : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : R/W : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion. The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. Bits 5 to 0 are always read as 0. The correspondence between the analog input channels and ADDR registers is shown in table 153. ADDR can always be read by the CPU. The upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section 15.3, Interface to Bus Master. The ADDR registers are initialized to H'0000 by a reset, and in standby mode or module stop mode. Table 15-3 Analog Input Channels and Corresponding ADDR Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 625 15.2.2 Bit A/D Control/Status Register (ADCSR) : 7 ADF 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W 3 CKS 0 R/W 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Initial value : R/W : Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation. ADCSR is initialized to H'00 by a reset, and in hardware standby mode or module stop mode. Bit 7--A/D End Flag (ADF): Status flag that indicates the end of A/D conversion. Bit 7 ADF 0 Description [Clearing conditions] * * 1 When 0 is written to the ADF flag after reading ADF = 1 When the DTC is activated by an ADI interrupt and ADDR is read (Initial value) [Setting conditions] * * Single mode: When A/D conversion ends Scan mode: When A/D conversion ends on all specified channels Bit 6--A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests at the end of A/D conversion. Bit 6 ADIE 0 1 Description A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled (Initial value) 626 Bit 5--A/D Start (ADST): Selects starting or stopping on A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST 0 1 Description * * * A/D conversion stopped (Initial value) Single mode: A/D conversion is started. Cleared to 0 automatically when conversion on the specified channel ends Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. Bit 4--Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating mode. See section 15.4, Operation, for single mode and scan mode operation. Only set the SCAN bit while conversion is stopped (ADST = 0). Bit 4 SCAN 0 1 Description Single mode Scan mode (Initial value) Bit 3--Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time while conversion is stopped (ADST = 0). Bit 3 CKS 0 1 Description Conversion time = 266 states (max.) Conversion time = 134 states (max.) (Initial value) Bits 2 to 0--Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select the analog input channels. Only set the input channel while conversion is stopped (ADST = 0). 627 Group Selection CH2 0 Channel Selection CH1 0 CH0 0 1 1 0 1 Single Mode AN0 (Initial value) AN1 AN2 AN3 AN4 AN5 AN6 AN7 Description Scan Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 1 0 0 1 1 0 1 15.2.3 Bit A/D Control Register (ADCR) : 7 TRGS1 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : R/W : ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D conversion operations. ADCR is initialized to H'3F by a reset, and in standby mode or module stop mode. Bits 7 and 6--Timer Trigger Select 1 and 0 (TRGS1, TRGS0): Select enabling or disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0 while conversion is stopped (ADST = 0). Bit 7 TRGS1 0 Bit 6 TRGS0 0 1 1 0 1 Description A/D conversion start by software is enabled (Initial value) A/D conversion start by TPU conversion start trigger is enabled -- A/D conversion start by external trigger pin (ADTRG) is enabled Bits 5 to 0--Reserved: These bits are reserved; they are always read as 1 and cannot be modified. 628 15.2.4 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 9--Module Stop (MSTP9): Specifies the A/D converter module stop mode. Bit 9 MSTP9 0 1 Description A/D converter module stop mode cleared A/D converter module stop mode set (Initial value) 629 15.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the CPU. When reading ADDR. always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. Figure 15-2 shows the data flow for ADDR access. Upper byte read Bus master (H'AA) Bus interface Module data bus TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Lower byte read Bus master (H'40) Module data bus Bus interface TEMP (H'40) ADDRnH (H'AA) ADDRnL (H'40) (n = A to D) Figure 15-2 ADDR Access Operation (Reading H'AA40) 630 15.4 Operation The A/D converter operates by successive approximation with 10-bit resolution. It has two operating modes: single mode and scan mode. 15.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1, according to the software or external trigger input. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when conversion ends. On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 15-3 shows a timing diagram for this example. [1] Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = 0, CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). [2] When A/D conversion is completed, the result is transferred to ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. [3] Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. [4] The A/D interrupt handling routine starts. [5] The routine reads ADCSR, then writes 0 to the ADF flag. [6] The routine reads and processes the connection result (ADDRB). [7] Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1, A/D conversion starts again and steps [2] to [7] are repeated. 631 Set* ADIE ADST ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Idle Idle Idle Idle A/D conversion 1 A/D conversion starts Set* Clear* Set* Clear* Idle A/D conversion 2 Idle ADDRA ADDRB ADDRC ADDRD Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 Note: * Vertical arrows ( ) indicate instructions executed by software. Figure 15-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) 632 15.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by a software, timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR registers corresponding to the channels. When the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the operating mode or input channel is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 15-4 shows a timing diagram for this example. [1] Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1) [2] When A/D conversion of the first channel (AN0) is completed, the result is transferred to ADDRA. Next, conversion of the second channel (AN1) starts automatically. [3] Conversion proceeds in the same way through the third channel (AN2). [4] When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends. [5] Steps [2] to [4] are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). 633 Continuous A/D conversion execution Set*1 ADST ADF A/D conversion time State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) State of channel 3 (AN3) Transfer ADDRA ADDRB ADDRC ADDRD Notes: 1. Vertical arrows ( ) indicate instructions executed by software. 2. Data currently being converted is ignored. A/D conversion result 1 A/D conversion result 4 A/D conversion result 2 A/D conversion result 3 Idle Idle Idle A/D conversion 1 Clear*1 Clear*1 Idle A/D conversion 2 A/D conversion 4 Idle A/D conversion 5 *2 Idle A/D conversion 3 Idle Idle Idle Figure 15-4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 634 15.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 15-5 shows the A/D conversion timing. Table 15-4 indicates the A/D conversion time. As indicated in figure 15-5, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 15-4. In scan mode, the values given in table 15-4 apply to the first conversion time. In the second and subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states when CKS = 1. (1) o Address bus (2) Write signal Input sampling timing ADF tD t SPL t CONV Legend (1) : (2) : : tD tSPL : tCONV : ADCSR write cycle ADCSR address A/D conversion start delay Input sampling time A/D conversion time Figure 15-5 A/D Conversion Timing 635 Table 15-4 A/D Conversion Time (Single Mode) CKS = 0 Item A/D conversion start delay Input sampling time A/D conversion time Symbol tD t SPL t CONV Min 10 -- 259 Typ -- 63 -- Max 17 -- 266 Min 6 -- 131 CKS = 1 Typ -- 31 -- Max 9 -- 134 Note: Values in the table are the number of states. 15.4.4 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan modes, are the same as if the ADST bit has been set to 1 by software. Figure 15-6 shows the timing. o ADTRG Internal trigger signal ADST A/D conversion Figure 15-6 External Trigger Input Timing 636 15.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC can be activated by an ADI interrupt. Having the converted data read by the DTC or DMAC in response to an ADI interrupt enables continuous conversion to be achieved without imposing a load on software. The A/D converter interrupt source is shown in table 15-5. Table 15-5 A/D Converter Interrupt Source Interrupt Source ADI Description Interrupt due to end of conversion DTC or DMAC Activation Possible 15.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins: (1) Analog input voltage range The voltage applied to analog input pins AN0 to AN7 during A/D conversion should be in the range AVSS ANn Vref. (2) Relation between AV CC, AVSS and V CC, VSS As the relationship between AVCC, AVSS and V CC, VSS, set AVSS = VSS . If the A/D converter is not used, the AVCC and AVSS pins must on no account be left open. (3) Vref input range The analog reference voltage input at the V ref pin set in the range Vref AVCC. If conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. Notes on Board Design: In board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D conversion values. 637 Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), analog reference power supply (Vref ), and analog power supply (AVCC) by the analog ground (AVSS ). Also, the analog ground (AVSS) should be connected at one point to a stable digital ground (VSS) on the board. Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) and analog reference power supply (Vref) should be connected between AVCC and AVSS as shown in figure 157. Also, the bypass capacitors connected to AVCC and Vref and the filter capacitor connected to AN0 to AN7 must be connected to AVSS . If a filter capacitor is connected as shown in figure 15-7, the input currents at the analog input pins (AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin ), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref Rin* 2 *1 *1 0.1 F 100 AN0 to AN7 AVSS Notes: Values are reference values. 1. 10 F 0.01 F 2. Rin: Input impedance Figure 15-7 Example of Analog Input Protection Circuit 638 Table 15-6 Analog Pin Specifications Item Analog input capacitance Permissible signal source impedance Min -- -- Max 20 10* Unit pF k Note: * When V CC = 4.0 V to 5.5 V and o 12 MHz 10 k AN0 to AN7 To A/D converter 20 pF Note: Values are reference values. Figure 15-8 Analog Input Pin Equivalent Circuit A/D Conversion Precision Definitions: H8S/2350 Series A/D conversion precision definitions are given below. * Resolution The number of A/D converter digital output codes * Offset error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from the minimum voltage value B'0000000000 (H'000) to B'0000000001 (H'001) (see figure 15-10). * Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see figure 15-10). * Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 15-9). * Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage. Does not include the offset error, full-scale error, or quantization error. * Absolute precision The deviation between the digital value and the analog input value. Includes the offset error, full-scale error, quantization error, and nonlinearity error. 639 Digital output 111 110 101 100 011 010 001 000 Ideal A/D conversion characteristic Quantization error 1 2 1024 1024 1022 1023 1024 1024 FS Analog input voltage Figure 15-9 A/D Conversion Precision Definitions (1) 640 Digital output Full-scale error Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 15-10 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: H8S/2350 Series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 10 k or less. This specification is provided to enable the A/D converter's sample-and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 10 k, charging may be insufficient and it may not be possible to guarantee the A/D conversion precision. However, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k, and the signal source impedance is ignored. However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mV/s or greater). When converting a high-speed analog signal, a low-impedance buffer should be inserted. 641 Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. H8/2350 Series Sensor output impedance to 10 k Sensor input Low-pass filter C to 0.1 F Cin = 15 pF A/D converter equivalent circuit 10 k 20 pF Note: Values are reference values. Figure 15-11 Example of Analog Input Circuit 642 Section 16 D/A Converter 16.1 Overview The H8S/2350 Series includes a two-channel D/A converter. 16.1.1 Features D/A converter features are listed below * * * * * * 8-bit resolution Two output channels Maximum conversion time of 10 s (with 20 pF load) Output voltage of 0 V to Vref D/A output hold function in software standby mode Module stop mode can be set As the initial setting, D/A converter operation is halted. Register access is enabled by exiting module stop mode. 643 16.1.2 Block Diagram Figure 16-1 shows a block diagram of the D/A converter. Module data bus Bus interface DACR Internal data bus Vref AVCC DADR0 8-bit DA1 D/A DA0 AVSS DADR1 Control circuit Figure 16-1 Block Diagram of D/A Converter 644 16.1.3 Pin Configuration Table 16-1 summarizes the input and output pins of the D/A converter. Table 16-1 Pin Configuration Pin Name Analog power pin Analog ground pin Analog output pin 0 Analog output pin 1 Reference voltage pin Symbol AVCC AVSS DA0 DA1 Vref I/O Input Input Output Output Input Function Analog power source Analog ground and reference voltage Channel 0 analog output Channel 1 analog output Analog reference voltage 16.1.4 Register Configuration Table 16-2 summarizes the registers of the D/A converter. Table 16-2 D/A Converter Registers Name D/A data register 0 D/A data register 1 D/A control register Module stop control register Abbreviation DADR0 DADR1 DACR MSTPCR R/W R/W R/W R/W R/W Initial Value H'00 H'00 H'1F H'3FFF Address* H'FFA4 H'FFA5 H'FFA6 H'FF3C Note:* Lower 16 bits of the address. 645 16.2 16.2.1 Bit Register Descriptions D/A Data Registers 0 and 1 (DADR0, DADR1) : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Initial value: R/W : DADR0 and DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 16.2.2 Bit D/A Control Register (DACR) : 7 DAOE1 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value: R/W : DACR is an 8-bit readable/writable register that controls the operation of the D/A converter. DACR is initialized to H'1F by a reset and in hardware standby mode. Bit 7--D/A Output Enable 1 (DAOE1): Controls D/A conversion and analog output for channel 1. Bit 7 DAOE1 0 1 Description Analog output DA1 is disabled Channel 1 D/A conversion is enabled; analog output DA1 is enabled (Initial value) 646 Bit 6--D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output for channel 0. Bit 6 DAOE0 0 1 Description Analog output DA0 is disabled Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value) Bit 5--D/A Enable (DAE): The DAOE0 and DAOE1 bits both control D/A conversion. When the DAE bit is cleared to 0, the channel 0 and 1 D/A conversions are controlled independently. When the DAE bit is set to 1, the channel 0 and 1 D/A conversions are controlled together. Output of resultant conversions is always controlled independently by the DAOE0 and DAOE1 bits. Bit 7 DAOE1 0 Bit 6 DAOE0 0 1 Bit 5 DAE * 0 1 1 0 0 1 1 * Description Channel 0 and 1 D/A conversions disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled Channel 0 and 1 D/A conversions enabled Channel 0 and 1 D/A conversions enabled *: Don't care If the H8S/2350 Series enters software standby mode when D/A conversion is enabled, the D/A output is held and the analog power current is the same as during D/A conversion. When it is necessary to reduce the analog power current in software standby mode, clear both the DAOE0 and DAOE1 bits to 0 to disable D/A output. Bits 4 to 0--Reserved: Read-only bits, always read as 1. 647 16.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. When the MSTP10 bit in MSTPCR is set to 1, D/A converter operation stops at the end of the bus cycle and a transition is made to module stop mode. Registers cannot be read or written to in module stop mode. For details, see section 20.5, Module Stop Mode. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 10--Module Stop (MSTP10): Specifies the D/A converter module stop mode. Bit 10 MSTP10 0 1 Description D/A converter module stop mode cleared D/A converter module stop mode set (Initial value) 648 16.3 Operation The D/A converter includes D/A conversion circuits for two channels, each of which can operate independently. D/A conversion is performed continuously while enabled by DACR. If either DADR0 or DADR1 is written to, the new data is immediately converted. The conversion result is output by setting the corresponding DAOE0 or DAOE1 bit to 1. The operation example described in this section concerns D/A conversion on channel 0. Figure 162 shows the timing of this operation. [1] Write the conversion data to DADR0. [2] Set the DAOE0 bit in DACR to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents 256 The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted. The new conversion result is output after the conversion time has elapsed. [4] If the DAOE0 bit is cleared to 0, the DA0 pin becomes an input pin. x Vref 649 DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle o Address DADR0 Conversion data 1 Conversion data 2 DAOE0 DA0 High-impedance state tDCONV Legend tDCONV: D/A conversion time Conversion result 1 tDCONV Conversion result 2 Figure 16-2 Example of D/A Converter Operation 650 Section 17 RAM 17.1 Overview The H8S/2350 Series has 2 kbytes of on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer. The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the system control register (SYSCR). 17.1.1 Block Diagram Figure 17-1 shows a block diagram of the on-chip RAM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'FFF400 H'FFF402 H'FFF404 H'FFF401 H'FFF403 H'FFF405 H'FFFBFE H'FFFBFF Figure 17-1 Block Diagram of RAM 651 17.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 17-1 shows the address and initial value of SYSCR. Table 17-1 RAM Register Name System control register Abbreviation SYSCR R/W R/W Initial Value H'01 Address* H'FF39 Note: * Lower 16 bits of the address. 17.2 17.2.1 Bit Register Descriptions System Control Register (SYSCR) : 7 -- 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W Initial value : R/W : The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in SYSCR, see section 3.2.2, System Control Register (SYSCR). Bit 0--RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode. Bit 0 RAME 0 1 Description On-chip RAM is disabled On-chip RAM is enabled (Initial value) 652 17.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFF400 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start at an even address. 17.4 Usage Note DTC register information can be located in addresses H'FFF800 to H'FFFBFF. When the DTC is used, the RAME bit must not be cleared to 0. 653 654 Section 18 ROM (H8S/2351 Only) 18.1 Overview The H8S/2351 has 64 kbytes of on-chip ROM (mask ROM). The ROM is connected to the H8S/2000 CPU by a 16-bit data bus. The CPU accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. The on-chip ROM is enabled or disabled by setting the mode pins (MD2, MD1, and MD0) and bit EAE in BCRL. 18.1.1 Block Diagram Figure 18-1 shows a block diagram of the on-chip ROM. Internal data bus (upper 8 bits) Internal data bus (lower 8 bits) H'000000 H'000002 H'000004 H'000001 H'000003 H'000004 H'00FFFE H'00FFFF Figure 18-1 Block Diagram of ROM (H8S/2351) 655 18.2 Operation The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data can be accessed in one state. Even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. Word data must start at an even address. The on-chip ROM is enabled and disabled by setting the mode pins (MD 2, MD1, and MD0). These settings are shown in table 18-1. In normal mode, a maximum of 56 kbytes of ROM can be used. Table 18-1 Operating Modes and ROM Area Mode Pin Operating Mode Mode 1 Normal expanded mode with on-chip ROM disabled Mode 2 Normal expanded mode with on-chip ROM enabled Mode 3 Normal single-chip mode Mode 4 Advanced expanded mode with on-chip ROM disabled Mode 5 Advanced expanded mode with on-chip ROM disabled Mode 6 Advanced expanded mode with on-chip ROM enabled Mode 7 Advanced single-chip mode 1 1 0 MD2 0 MD1 0 1 MD0 1 0 1 0 1 0 1 Enabled Disabled On-Chip ROM Disabled Enabled (56 kbytes) 656 Section 19 Clock Pulse Generator 19.1 Overview The H8S/2350 Series has a built-in clock pulse generator (CPG) that generates the system clock (o), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit. 19.1.1 Block Diagram Figure 19-1 shows a block diagram of the clock pulse generator. SCKCR SCK2 to SCK0 Mediumspeed divider EXTAL Oscillator XTAL Duty adjustment circuit o/2 to o/32 Bus master clock selection circuit System clock to o pin Internal clock to supporting modules Bus master clock to CPU, DTC, and DMAC Figure 19-1 Block Diagram of Clock Pulse Generator 657 19.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 19-1 shows the register configuration. Table 19-1 Clock Pulse Generator Register Name System clock control register Abbreviation SCKCR R/W R/W Initial Value H'00 Address* H'FF3A Note:* Lower 16 bits of the address. 658 19.2 19.2.1 Bit Register Descriptions System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value: R/W : SCKCR is an 8-bit readable/writable register that performs o clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): Controls o output. Description Bit 7 PSTOP 0 1 Normal Operation o output (initial value) Fixed high Sleep Mode o output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bit 6--Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3--Reserved: Read-only bits, always read as 0. Bits 2 to 0--System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 659 19.3 Oscillator Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 19.3.1 Connecting a Crystal Resonator Circuit Configuration: A crystal resonator can be connected as shown in the example in figure 19-2. Select the damping resistance Rd according to table 19-2. An AT-cut parallel-resonance crystal should be used. CL1 EXTAL XTAL Rd CL2 CL1 = CL2 = 10 to 22pF Figure 19-2 Connection of Crystal Resonator (Example) Table 19-2 Damping Resistance Value Frequency (MHz) Rd () 2 1k 4 500 8 200 12 0 16 0 20 0 Crystal Resonator: Figure 19-3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 19-3 and the same resonance frequency as the system clock (o). CL L XTAL Rs EXTAL AT-cut parallel-resonance type C0 Figure 19-3 Crystal Resonator Equivalent Circuit 660 Table 19-3 Crystal Resonator Parameters Frequency (MHz) RS max () C0 max (pF) 2 500 7 4 120 7 8 80 7 12 60 7 16 50 7 20 40 7 Note on Board Design: When a crystal resonator is connected, the following points should be noted: Other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. See figure 19-4. When designing the board, place the crystal resonator and its load capacitors as close as possible to the XTAL and EXTAL pins. Avoid CL2 Signal A Signal B H8S/2350 Series XTAL EXTAL CL1 Figure 19-4 Example of Incorrect Board Design 661 19.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 19-5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL XTAL Open External clock input (a) XTAL pin left open EXTAL XTAL External clock input (b) Complementary clock input at XTAL pin Figure 19-5 External Clock Input (Examples) External Clock: The external clock signal should have the same frequency as the system clock (o). Table 19-4 and figure 19-6 show the input conditions for the external clock. 662 Table 19-4 External Clock Input Conditions VCC = 2.7 V to 5.5 V Item External clock input low pulse width External clock input high pulse width External clock rise time External clock fall time Clock low pulse width level Clock high pulse width level Symbol t EXL t EXH t EXr t EXf t CL Min 40 40 -- -- 0.4 80 t CH 0.4 80 Max -- -- 10 10 0.6 -- 0.6 -- VCC = 5.0 V 10% Min 20 20 -- -- 0.4 80 0.4 80 Max -- -- 5 5 0.6 -- 0.6 -- Unit ns ns ns ns t cyc ns t cyc ns o 5 MHz o < 5 MHz o 5 MHz o < 5 MHz Figure 21-4 Test Conditions Figure 19-6 tEXH tEXL EXTAL VCC x 0.5 tEXr tEXf Figure 19-6 External Clock Input Timing 663 19.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (o). 19.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate o/2, o/4, o/8, o/16, and o/32. 19.6 Bus Master Clock Selection Circuit The bus master clock selection circuit selects the system clock (o) or one of the medium-speed clocks (o/2, o/4, or o/8, o/16, and o/32) to be supplied to the bus master, according to the settings of the SCK2 to SCK0 bits in SCKCR. 664 Section 20 Power-Down Modes 20.1 Overview In addition to the normal program execution state, the H8S/2350 Series has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The H8S/2350 Series operating modes are as follows: (1) High-speed mode (2) Medium-speed mode (3) Sleep mode (4) Module stop mode (5) Software standby mode (6) Hardware standby mode Of these, (2) to (6) are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a CPU and bus master mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the CPU). A combination of these modes can be set. After a reset, the H8S/2350 Series is in high-speed mode. Table 20-1 shows the conditions for transition to the various modes, the status of the CPU, on-chip supporting modules, etc., and the method of clearing each mode. 665 Table 20-1 Operating Modes Operating Mode High speed mode Transition Condition Control register Clearing Condition CPU Oscillator Functions Functions High speed Registers Functions High speed Modules Registers Functions I/O Ports High speed High speed MediumControl speed mode register Sleep mode Instruction Module stop Control mode register Software standby mode Hardware standby mode Instruction External interrupt Interrupt Medium Functions speed Halted Retained High/ Functions medium speed *1 High speed Halted Functions Retained/ reset *2 Retained/ reset *2 Reset Functions Functions High speed Retained High/ Functions medium speed Halted Retained Halted Halted Retained Pin Halted Halted Undefined Halted High impedance Notes: 1. The bus master operates on the medium-speed clock, and other on-chip supporting modules on the high-speed clock. 2. The SCI and A/D converter are reset, and other on-chip supporting modules retain their state. 20.1.1 Register Configuration Power-down modes are controlled by the SBYCR, SCKCR, and MSTPCR registers. Table 20-2 summarizes these registers. Table 20-2 Power-Down Mode Registers Name Standby control register System clock control register Module stop control register H Module stop control register L Abbreviation SBYCR SCKCR MSTPCRH MSTPCRL R/W R/W R/W R/W R/W Initial Value H'08 H'00 H'3F H'FF Address* H'FF38 H'FF3A H'FF3C H'FF3D Note: * Lower 16 bits of the address. 666 20.2 20.2.1 Bit Register Descriptions Standby Control Register (SBYCR) : 7 SSBY 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- 0 -- 0 R/W Initial value : R/W : SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--Software Standby (SSBY): Specifies a transition to software standby mode. Remains set to 1 when software standby mode is released by an external interrupt, and a transition is made to normal operation. The SSBY bit should be cleared by writing 0 to it. Bit 7 SSBY 0 1 Description Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction (Initial value) Bits 6 to 4--Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU waits for the clock to stabilize when software standby mode is cleared by an external interrupt. With crystal oscillation, refer to table 20-4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). With an external clock, any selection can be made. Bit 6 STS2 0 Bit 5 STS1 0 Bit 4 STS0 0 1 1 0 1 1 0 0 1 1 0 1 Description Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states 667 (Initial value) Bit 3--Output Port Enable (OPE): Specifies whether the output of the address bus and bus control signals (CS0 to CS7, AS, RD, HWR, LWR, CAS) is retained or set to the high-impedance state in software standby mode. Bit 3 OPE 0 1 Description In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state (Initial value) Bits 2 and 1--Reserved: Read-only bits, always read as 0. Bit 0--Reserved: This bit can be read or written to, but only 0 should be written. 20.2.2 Bit System Clock Control Register (SCKCR) : 7 PSTOP 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- 2 SCK2 0 R/W 1 SCK1 0 R/W 0 SCK0 0 R/W Initial value : R/W : SCKCR is an 8-bit readable/writable register that performs o clock output control and mediumspeed mode control. SCKCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode. Bit 7--o Clock Output Disable (PSTOP): Controls o output. Description Bit 7 PSTOP 0 1 Normal Operating Mode o output (initial value) Fixed high Sleep Mode o output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance Bits 6--Reserved: This bit can be read or written to, but only 0 should be written. Bits 5 to 3--Reserved: Read-only bits, always read as 0. 668 Bits 2 to 0--System Clock Select (SCK2 to SCK0): These bits select the clock for the bus master. Bit 2 SCK2 0 Bit 1 SCK1 0 Bit 0 SCK0 0 1 1 0 1 1 0 0 1 1 -- Description Bus master in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- (Initial value) 20.2.3 Module Stop Control Register (MSTPCR) MSTPCRH MSTPCRL 10 1 9 1 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Bit : 15 0 14 0 13 1 12 1 11 1 Initial value : R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode. Bits 15 to 0--Module Stop (MSTP 15 to MSTP 0): These bits specify module stop mode. See table 20-3 for the method of selecting on-chip supporting modules. Bits 15 to 0 MSTP15 to MSTP0 0 1 Description Module stop mode cleared Module stop mode set 669 20.3 Medium-Speed Mode When the SCK2 to SCK0 bits in SCKCR are set to 1, the operating mode changes to mediumspeed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on the operating clock (o/2, o/4, o/8, o/16, or o/32) specified by the SCK2 to SCK0 bits. The bus masters other than the CPU (the DMAC and DTC) also operate in medium-speed mode. On-chip supporting modules other than the bus masters always operate on the high-speed clock (o). In medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. For example, if o/4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal I/O registers in 8 states. Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored. If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer. When the STBY pin is driven low, a transition is made to hardware standby mode. Figure 20-1 shows the timing for transition to and clearance of medium-speed mode. Medium-speed mode o, supporting module clock Bus master clock Internal address bus SCKCR SCKCR Internal write signal Figure 20-1 Medium-Speed Mode Transition and Clearance Timing 670 20.4 Sleep Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters sleep mode. In sleep mode, CPU operation stops but the contents of the CPU's internal registers are retained. Other supporting modules do not stop. Sleep mode is cleared by a reset or any interrupt, and the CPU returns to the normal program execution state via the exception handling state. Sleep mode is not cleared if interrupts are disabled, or if interrupts other than NMI are masked by the CPU. When the STBY pin is driven low, a transition is made to hardware standby mode. 20.5 20.5.1 Module Stop Mode Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 20-3 shows MSTP bits and the corresponding on-chip supporting modules. When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module starts operating at the end of the bus cycle. In module stop mode, the internal states of modules other than the SCI and A/D converter are retained. After reset clearance, all modules other than DMAC and DTC are in module stop mode. When an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. Do not make a transition to sleep mode with MSTPCR set to H'FFFF, as this will halt operation of the bus controller. 671 Table 20-3 MSTP Bits and Corresponding On-Chip Supporting Modules Register MSTPCRH Bit MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 Module DMA controller (DMAC) Data transfer controller (DTC) 16-bit timer pulse unit (TPU) -- Programmable pulse generator (PPG) D/A converter A/D converter -- -- Serial communication interface (SCI) channel 1 Serial communication interface (SCI) channel 0 -- -- -- -- -- Note: Bits 12, 8, 7, and 4 to 0 can be read or written to, but do not affect operation. 20.5.2 Usage Notes DMAC/DTC Module Stop: Depending on the operating status of the DMAC or DTC, the MSTP15 and MSTP14 bits may not be set to 1. Setting of the DMAC or DTC module stop mode should be carried out only when the respective module is not activated. For details, refer to section 7, DMA Controller, and section 8, Data Transfer Controller. On-Chip Supporting Module Interrupt: Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU interrupt source or the DMAC or DTC activation source. Interrupts should therefore be disabled before entering module stop mode. Writing to MSTPCR: MSTPCR should only be written to by the CPU. 672 20.6 20.6.1 Software Standby Mode Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU's internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained. Whether the address bus and bus control signals are placed in the high-impedance state or retain the output state can be specified by the OPE bit in SBYCR. In this mode the oscillator stops, and therefore power dissipation is significantly reduced. 20.6.2 Clearing Software Standby Mode Software standby mode is cleared by an external interrupt (NMI pin, or pins IRQ0 to IRQ2), or by means of the RES pin or STBY pin. * Clearing with an interrupt When an NMI or IRQ0 to IRQ2 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR, stable clocks are supplied to the entire H8S/2350 Series chip, software standby mode is cleared, and interrupt exception handling is started. When clearing software standby mode with an IRQ0 to IRQ2 interrupt, set the corresponding enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ2 is generated. Software standby mode cannot be cleared if the interrupt has been masked on the CPU side or has been designated as a DTC activation source. * Clearing with the RES pin When the RES pin is driven low, clock oscillation is started. At the same time as clock oscillation starts, clocks are supplied to the entire H8S/2350 Series chip. Note that the RES pin must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception handling. * Clearing with the STBY pin When the STBY pin is driven low, a transition is made to hardware standby mode. 673 20.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 20-4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 20-4 Oscillation Stabilization Time Settings STS2 STS1 STS0 Standby Time 0 0 0 1 1 0 1 1 0 0 1 1 0 1 8192 states 16384 states 32768 states 65536 states 131072 states 262144 states Reserved 16 states 20 16 12 10 8 6 4 2 MHz MHz MHz MHz MHz MHz MHz MHz Unit 0.41 0.51 0.68 0.8 0.82 1.0 1.6 3.3 6.6 2.0 4.1 8.2 1.3 2.7 5.5 1.6 3.3 6.6 1.0 2.0 4.1 8.2 1.3 2.7 5.5 2.0 4.1 4.1 8.2 ms 8.2 16.4 10.9 16.4 32.8 10.9 13.1 16.4 21.8 32.8 65.5 13.1 16.4 21.8 26.2 32.8 43.6 65.6 131.2 -- 0.8 -- 1.0 -- 1.3 -- 1.6 -- 2.0 -- 2.7 -- 4.0 -- 8.0 -- s : Recommended time setting Using an External Clock: Any value can be set. Normally, use of the minimum time is recommended. 20.6.4 Software Standby Mode Application Example Figure 20-2 shows an example in which a transition is made to software standby mode at the falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI pin. In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set to 1, and a SLEEP instruction is executed, causing a transition to software standby mode. Software standby mode is then cleared at the rising edge on the NMI pin. 674 Oscillator o NMI NMIEG SSBY NMI exception Software standby mode handling (power-down mode) NMIEG=1 SSBY=1 SLEEP instruction Oscillation stabilization time tOSC2 NMI exception handling Figure 20-2 Software Standby Mode Application Example 20.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained. If the OPE bit is set to 1, the address bus and bus control signal output is also retained. Therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. Current Dissipation during Oscillation Stabilization Wait Period: Current dissipation increases during the oscillation stabilization wait period. Write Data Buffer Function: The write data buffer function and software standby mode cannot be used at the same time. When the write data buffer function is used, the WDBE bit in BCRL should be cleared to 0 to cancel the write data buffer function before entering software standby mode. Also check that external writes have finished, by reading external addresses, etc., before executing a SLEEP instruction to enter software standby mode. See section 6.9, Write Data Buffer Function, for details of the write data buffer function. 675 20.7 20.7.1 Hardware Standby Mode Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state. In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while the H8S/2350 Series is in hardware standby mode. Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator stabilizes (at least 8 ms--the oscillation stabilization time--when using a crystal oscillator). When the RES pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 20.7.2 Hardware Standby Mode Timing Figure 20-3 shows an example of hardware standby mode timing. When the STBY pin is driven low after the RES pin has been driven low, a transition is made to hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting for the oscillation stabilization time, then changing the RES pin from low to high. 676 Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 20-3 Hardware Standby Mode Timing (Example) 20.8 o Clock Output Disabling Function Output of the o clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the o clock stops at the end of the bus cycle, and o output goes high. o clock output is enabled when the PSTOP bit is cleared to 0. When DDR for the corresponding port is cleared to 0, o clock output is disabled and input port mode is set. Table 20-5 shows the state of the o pin in each processing state. Table 20-5 o Pin State in Each Processing State DDR PSTOP Hardware standby mode Software standby mode Sleep mode Normal operating state 0 -- High impedance High impedance High impedance High impedance Fixed high o output o output Fixed high Fixed high 1 0 1 677 678 Section 21 Electrical Characteristics 21.1 Absolute Maximum Ratings Table 21-1 lists the absolute maximum ratings. Table 21-1 Absolute Maximum Ratings Item Power supply voltage Input voltage (except port 4) Input voltage (port 4) Reference voltage Analog power supply voltage Analog input voltage Operating temperature Symbol VCC Vin Vin Vref AVCC VAN Topr Value -0.3 to +7.0 -0.3 to VCC +0.3 -0.3 to AVCC +0.3 -0.3 to AVCC +0.3 -0.3 to +7.0 -0.3 to AVCC +0.3 Regular specifications: -20 to +75 Wide-range specifications: -40 to +85 Storage temperature Tstg -55 to +125 Unit V V V V V V C C C Caution: Permanent damage to the chip may result if absolute maximum rating are exceeded. 679 21.2 DC Characteristics Table 21-2 lists the DC characteristics. Table 21-3 lists the permissible output currents. Table 21-2 DC Characteristics Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES, STBY, NMI, MD2 to MD0 EXTAL Port 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Port 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage Input leakage current All output pins VOH All output pins VOL Port 1, A to C RES STBY, NMI, MD2 to MD0 Port 4 Note: | I in | VIL Symbol VT VT - + + - Min 1.0 -- 0.4 VCC - 0.7 Typ -- -- -- -- Max -- Unit V Test Conditions VCC x 0.7 V -- VCC + 0.3 V V VT - VT VIH VCC x 0.7 -- 2.0 -- VCC + 0.3 VCC + 0.3 V V 2.0 -0.3 -0.3 -- -- -- AVCC + 0.3 V 0.5 0.8 V V VCC - 0.5 3.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0.4 1.0 10.0 1.0 1.0 V V V V A A A I OH = -200 A I OH = -1 mA I OL = 1.6 mA I OL = 10 mA Vin = 0.5 to VCC - 0.5 V Vin = 0.5 to AVCC - 0.5 V 1. If the A/D and D/A converters are not used,do not leave the AV CC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 680 Table 21-2 DC Characteristics (cont) Conditions: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Three-state leakage current (off state) Port 1 to 3, 5, 6, A to G Symbol I TSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC - 0.5 V MOS input Port A to E pull-up current* 5 Input capacitance RES NMI All input pins except RES and NMI Current dissipation* 2 Normal operation Sleep mode Standby mode* 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage -I P Cin 50 -- -- -- -- -- -- -- 300 80 50 15 A pF pF pF Vin = 0 V Vin = 0 V f = 1 MHz T a = 25C I CC * 4 -- -- -- -- 60 95 (5.0 V) 45 78 (5.0 V) 0.01 -- 5.0 20 mA mA A mA f = 20 MHz f = 20 MHz Ta 50C 50C < Ta Al CC -- 0.8 2.0 (5.0 V) 0.01 5.0 -- Al CC -- A mA 1.9 3.0 (5.0 V) 0.01 -- 5.0 -- -- VRAM 2.0 A V Notes: 1. If the A/D and D/A converters are not used,do not leave the AV CC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 2. Current dissipation values are for V IH min = VCC -0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 4.5V, VIH min = VCC x 0.9, and V IL max = 0.3 V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 0.85 (mA/(MHz x V)) x V CC x f [normal mode] I CC max = 1.0 (mA) + 0.7 (mA/(MHz x V)) x V CC x f [sleep mode] 5. Only applies to the H8S/2351. 681 Table 21-2 DC Characteristics (cont) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Schmitt trigger input voltage Input high voltage Port 2, P64 to P6 7, PA4 to PA 7 RES, STBY, NMI, MD2 to MD0 EXTAL Port 1, 3, 5, B to G, P60 to P6 3, PA0 to PA 3 Port 4 Input low voltage RES, STBY, MD2 to MD0 NMI, EXTAL, Port 1, 3 to 5, B to G, P60 to P6 3, PA0 to PA 3 Output high voltage Output low voltage All output pins VOH VIL Symbol VT VT - + + - Min Typ Max -- Unit V Test Conditions VCC x 0.2 -- -- -- VCC x 0.07 -- VCC x 0.9 -- VCC x 0.7 V -- VCC +0.3 V V VT - VT VIH VCC x 0.7 -- VCC x 0.7 -- VCC +0.3 VCC +0.3 V V VCC x 0.7 -- -0.3 -0.3 -- -- AVCC +0.3 V VCC x 0.1 V VCC x 0.2 V VCC < 4.0 V 0.8 VCC - 0.5 VCC - 1.0 -- -- -- -- -- -- 0.4 1.0 V V V V VCC = 4.0 to 5.5 V I OH = -200 A I OH = -1 mA I OL = 1.6 mA VCC 4 V I OL = 5 mA 4.0 < VCC 5.5 V I OL = 10 mA Vin = 0.5 to VCC - 0.5V Vin = 0.5 to AVCC - 0.5V All output pins VOL Port 1, A to C -- -- Input leakage current RES STBY, NMI, MD2 to MD0 Port 4 | I in | -- -- -- -- -- -- 10.0 1.0 1.0 A A A Note: 1. If the A/D and D/A converters are not used,do not leave the AV CC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 682 Table 21-2 DC Characteristics (cont) Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Three-state leakage current (off state) Port 1 to 3, 5, 6, A to G Symbol I TSI Min -- Typ -- Max 1.0 Unit A Test Conditions Vin = 0.5 to VCC -0.5 V MOS input Port A to E pull-up current* 5 Input capacitance RES NMI All input pins except RES and NMI Current dissipation* 2 Normal operation Sleep mode Standby mode* 3 Analog power supply current During A/D and D/A conversion Idle Reference current During A/D and D/A conversion Idle RAM standby voltage -I P Cin 10 -- -- -- -- -- -- -- 300 80 50 15 A pF pF pF VCC = 2.7 V to 5.5 V, Vin = 0 V Vin = 0 V f = 1 MHz Ta = 25C I CC * 4 -- -- -- -- 20 48 (3.0 V) 12 40 (3.0 V) 0.01 -- 5.0 20 mA mA A mA f = 10 MHz f = 10 MHz Ta 50C 50C < Ta Al CC -- 0.2 2.0 (3.0 V) 0.01 5.0 -- Al CC -- A mA 1.2 3.0 (3.0 V) 0.01 -- 5.0 -- -- VRAM 2.0 A V Notes: 1. If the A/D and D/A converters are not used,do not leave the AV CC, AVSS, and V ref pins open. Connect AVCC and Vref to V CC, and connect AVSS to V SS . 2. Current dissipation values are for V IH min = VCC -0.5 V and VIL max = 0.5V with all output pins unloaded and the on-chip pull-up transistors in the off state. 3. The values are for VRAM VCC < 2.7 V, VIH min = VCC x 0.9, and V IL max = 0.3V. 4. I CC depends on VCC and f as follows: I CC max = 1.0 (mA) + 0.85 (mA/(MHz x V)) x V CC x f [normal mode] I CC max = 1.0 (mA) + 0.70 (mA/(MHz x V)) x V CC x f [sleep mode] 5. Only applies to the H8S/2351. 683 Table 21-3 Permissible Output Currents Conditions: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 to AVCC, VSS = AVSS = 0 V, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Item Permissible output low current (per pin) Permissible output low current (total) Port 1, A to C Other output pins Total of 32 pins including port 1 and A to C Total of all output pins, including the above Permissible output high current (per pin) Permissible output high current (total) All output pins Total of all output pins -I OH -I OH I OL Symbol I OL Min -- -- -- Typ -- -- -- Max 10 2.0 80 Unit mA mA mA -- -- 120 mA -- -- -- -- 2.0 40 mA mA Notes: 1. To protect chip reliability, do not exceed the output current values in table 21-3. 2. When driving a darlington pair or LED directly, always insert a current-limiting resistor in the output line, as show in figures 21-1 and 21-2. H8S/2350 Series 2k Port Darlington Pair Figure 21-1 Darlington Pair Drive Circuit (Example) 684 H8S/2350 Series 600 Port 1, A to C LED Figure 21-2 LED Drive Circuit (Example) 21.3 AC Characteristics Figure 21-3 show, the test conditions for the AC characteristics. 5V RL LSI output pin C = 90 pF: Port 1, A to F C = 30 pF: Port 2, 3, 5, 6, G RL = 2.4 k RH = 12 k I/O timing test levels * Low level: 0.8 V * High level: 2.0 V C RH Figure 21-3 Output Load Circuit 685 21.3.1 Clock Timing Table 21-4 lists the clock timing Table 21-4 Clock Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Clock cycle time Clock high pulse width Clock low pulse width Clock rise time Clock fall time Clock oscillator setting time at reset (crystal) Clock oscillator setting time in software standby (crystal) External clock output stabilization delay time Symbol t cyc t CH t CL t Cr t Cf t OSC1 t OSC2 t DEXT Min 100 35 35 -- -- 20 20 500 Max 500 -- -- 15 15 -- -- -- Condition B Min 50 20 20 -- -- 10 10 500 Max 500 -- -- 5 5 -- -- -- Unit ns ns ns ns ns ms ms s Figure 21-5 Figure 20-2 Figure 21-5 Test Conditions Figure 21-4 Figure 21-4 tcyc tCH o tCL tCr tCf Figure 21-4 System Clock Timing 686 EXTAL tDEXT VCC tDEXT STBY NMI tOSC1 RES tOSC2 o Figure 21-5 Oscillator Settling Timing 687 21.3.2 Control Signal Timing Table 21-5 lists the control signal timing. Table 21-5 Control Signal Timing-- Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item RES setup time RES pulse width NMI reset setup time NMI reset hold time NMI setup time NMI hold time NMI pulse width (exiting software standby mode) IRQ setup time IRQ hold time IRQ pulse width (exiting software standby mode) Symbol t RESS t RESW t NMIRS t NMIRH t NMIS t NMIH t NMIW t IRQS t IRQH t IRQW Min 200 20 250 200 250 10 200 250 10 200 Max -- -- -- -- -- -- -- -- -- -- Condition B Min 200 20 200 200 150 10 200 150 10 200 Max -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns Figure 21-7 Unit ns t cyc ns Test Conditions Figure 21-6 688 o tRESS RES tRESW tNMIRS NMI tRESS tNMIRH Figure 21-6 Reset Input Timing o tNMIS NMI tNMIW tNMIH IRQi (i= 0 to 2) tIRQS IRQ Edge input tIRQS IRQ Level input tIRQW tIRQH Figure 21-7 Interrupt Input Timing 689 21.3.3 Bus Timing Table 21-6 lists the bus timing. Table 21-6 Bus Timing Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o= 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Address delay time Address setup time Address hold time Precharge time CS delay time 1 CS delay time 2 AS delay time RD delay time 1 RD delay time 2 CAS delay time Read data setup time Read data hold time Read data access time1 Read data access time2 Read data access time3 Symbol t AD t AS t AH t PCH t CSD1 t CSD2 t ASD t RSD1 t RSD2 t CASD t RDS t RDH t ACC1 t ACC2 t ACC3 Min -- Max 40 Condition B Min -- Max 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns Test Conditions Figure 21-8 to Figure 21-15 0.5 x -- t cyc - 30 0.5 x -- t cyc - 20 1.5 x -- t cyc - 40 -- -- -- -- -- -- 30 0 -- -- -- 40 40 40 40 40 40 -- -- 0.5 x -- t cyc - 15 0.5 x -- t cyc - 10 1.5 x -- t cyc - 20 -- -- -- -- -- -- 15 0 20 20 20 20 20 20 -- -- 1.0 x -- t cyc - 50 1.5 x -- t cyc - 50 2.0 x -- t cyc - 50 1.0 x ns t cyc - 25 1.5 x ns t cyc - 25 2.0 x ns t cyc - 25 690 Table 21-6 Bus Timing (cont) Condition A: VCC = 2.7 to 5.5 V, AVCC = 2.7 to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o= 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Read data access time 4 Read data access time 5 WR delay time 1 WR delay time 2 WR pulse width 1 WR pulse width 2 Write data delay time Write data setup time Write data hold time WR setup time WR hold time CAS setup time WAIT setup time WAIT hold time BREQ setup time BACK delay time Bus-floating time BREQO delay time Symbol t ACC4 t ACC5 t WRD1 t WRD2 t WSW1 t WSW2 t WDD t WDS t WDH t WCS t WCH t CSR t WTS t WTH t BRQS t BACD t BZD t BRQOD Min -- -- -- -- Max 2.5 x -- t cyc - 50 3.0 x -- t cyc - 50 40 40 -- -- Condition B Min Max Unit Test Conditions Figure 21-8 to Figure 21-15 2.5 x ns t cyc - 25 3.0 x ns t cyc - 25 20 20 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 21-17 Figure 21-16 Figure 21-12 Figure 21-10 1.0 x -- t cyc - 40 1.5 x -- t cyc - 40 -- 60 0.5 x -- t cyc - 40 0.5 x -- t cyc - 20 0.5 x -- t cyc - 20 0.5 x -- t cyc - 20 0.5 x -- t cyc - 20 60 10 60 -- -- -- -- -- -- 30 100 60 1.0 x -- t cyc - 20 1.5 x -- t cyc - 20 -- 30 0.5 x -- t cyc - 20 0.5 x -- t cyc - 10 0.5 x -- t cyc - 10 0.5 x -- t cyc - 10 0.5 x -- t cyc - 10 30 5 30 -- -- -- -- -- -- 15 50 30 691 T1 T2 o tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC2 tRSD2 tACC3 D15 to D0 (read) tWRD2 HWR, LWR (write) tRDS tRDH tWRD2 tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 21-8 Basic Bus Timing (Two-State Access) 692 T1 T2 T3 o tAD A23 to A0 tCSD1 CS7 to CS0 tAS tAH tASD AS tASD tRSD1 RD (read) tAS tACC4 tRSD2 tACC5 D15 to D0 (read) tRDS tRDH tWRD1 HWR, LWR (write) tWDD tWDS D15 to D0 (write) tWSW2 tWRD2 tAH tWDH Figure 21-9 Basic Bus Timing (Three-State Access) 693 T1 T2 TW T3 o A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tWTS tWTH WAIT tWTS tWTH Figure 21-10 Basic Bus Timing (Three-State Access with One Wait State) 694 Tp Tr TC1 TC2 o tAD A23 to A0 tAS tPCH CS5 to CS2 (RAS) tCSD2 CAS tAH tAD tACC4 tCSD1 tCASD tACC1 tCASD tACC3 D15 to D0 (read) tWRD1 HWR, LWR (write) tWCS tWDD tWDS D15 to D0 (write) tWCH tRDS tRDH tWRD1 tWDH Figure 21-11 DRAM Bus Timing 695 TRp TRr TRc1 TRc2 o tCSD2 tCSD1 CS5 to CS2 (RAS) tCSR tCASD CAS tCASD Figure 21-12 CAS-Before-RAS Refresh Timing TRp TRr TRc TRc o tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD CAS tCASD Figure 21-13 Self-Refresh Timing 696 T1 T2 or T3 T1 T2 o tAD A23 to A0 tAS tAH CS7 to CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) tRDS tRDH Figure 21-14 Burst ROM Access Timing (Two-State Access) 697 T1 o T2 or T3 T1 tAD A23 to A0 CS7 to CS0 AS tRSD2 RD (read) tACC1 D15 to D0 (read) tRDS tRDH Figure 21-15 Burst ROM Access Timing (One-State Access) 698 o tBRQS tBRQS BREQ tBACD BACK tBZD A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS tBACD tBZD Figure 21-16 External Bus Release Timing o tBRQOD tBRQOD BREQO Figure 21-17 External Bus Request Output Timing 699 21.3.4 DMAC Timing Table 21-7 lists the DMAC timing. Table 21-7 DMAC Timing Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item DREQ setup time DREQ hold time TEND delay time DACK delay time 1 DACK delay time 2 Symbol t DRQS t DRQH t TED t DACD1 t DACD2 Min 40 10 -- -- -- Max -- -- 40 40 40 Condition B Min 30 10 -- -- -- Max -- -- 20 20 20 ns Figure 21-20 Figure 21-18, Figure 21-19 Unit ns Test Conditions Figure 21-21 700 T1 T2 o A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0 , DACK1 tDACD2 Figure 21-18 DMAC Single Address Transfer Timing (Two-State Access) 701 T1 o T2 T3 A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 DACK0, DACK1 tDACD2 Figure 21-19 DMAC Single Address Transfer Timing (Three-State Access) 702 T1 T2 or T3 o tTED TEND0, TEND1 tTED Figure 21-20 DMAC TEND Output Timing o tDRQS DREQ0, DREQ1 tDRQH Figure 21-21 DMAC DREQ Intput Timing 703 21.3.5 Timing of On-Chip Supporting Modules Table 21-8 lists the timing of on-chip supporting modules. Table 21-8 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item PORT Output data delay time Input data setup time Input data hold time PPG TPU Pulse output delay time Timer output delay time Timer input setup time Timer clock input setup time Timer clock pulse width Single edge Both edges Symbol t PWD t PRS t PRH t POD t TOCD t TICS t TCKS t TCKWH t TCKWL Min -- 50 50 -- -- 50 50 1.5 2.5 Max 100 -- -- 100 100 -- -- -- -- Condition B Min -- 30 30 -- -- 30 30 1.5 2.5 Max 50 -- -- 50 50 -- -- -- -- ns t cyc Figure 21-25 ns ns Figure 21-23 Figure 21-24 Unit ns Test Conditions Figure 21-22 704 Table 21-8 Timing of On-Chip Supporting Modules (cont) Condition A: VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = 5.0 V 10%, AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, Ta = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications Condition A Item WDT SCI Overflow output delay time Input clock cycle Symbol t WOVD Min -- 4 6 t SCKW t SCKr t SCKf t TXD 0.4 -- -- -- 100 100 50 Max 100 -- -- 0.6 1.5 1.5 100 -- -- -- Condition B Min -- 4 6 0.4 -- -- -- 50 50 30 Max 50 -- -- 0.6 1.5 1.5 50 -- -- -- ns ns ns ns Figure 21-29 Figure 21-28 t Scyc t cyc Unit ns t cyc Test Conditions Figure 21-26 Figure 21-27 Asynchro- t Scyc nous Synchronous Input clock pulse width Input clock rise time Input clock fall time Transmit data delay time Receive data setup t RXS time (synchronous) Receive data hold t RXH time (synchronous) A/D Trigger input setup t TRGS converter time 705 T1 o T2 tPRS Port 1 to 6, A to G (read) tPRH tPWD Port 1 to 3, 5, 6, A to G (write) Figure 21-22 I/O Port Input/Output Timing o tPOD PO15 to PO0 Figure 21-23 PPG Output Timing o tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 21-24 TPU Input/Output Timing 706 o tTCKS TCLKA to TCLKD tTCKWL tTCKWH tTCKS Figure 21-25 TPU Clock Input Timing o tWOVD WDTOVF tWOVD Figure 21-26 WDT Output Timing tSCKW SCK0, SCK1 tSCKr tSCKf tScyc Figure 21-27 SCK Clock Input Timing 707 SCK0, SCK1 tTXD TxD0, TxD1 (transmit data) tRXS RxD0, RxD1 (receive data) tRXH Figure 21-28 SCI Input/Output Timing (Clock Synchronous Mode) o tTRGS ADTRG Figure 21-29 A/D Converter External Trigger Input Timing 708 21.4 A/D Conversion Characteristics Table 21-9 lists the A/D conversion characteristics. Table 21-9 A/D Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, T a = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, T a = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Resolution Conversion time Analog input capacitance Permissible signal-source impedance Nonlinearity error Offset error Full-scale error Quantization Absolute accuracy Notes: 1. 2. 3. 4. 4.0 V AVCC 5.5 V 2.7 V AVCC < 4.0 V o 12 MHz o > 12 MHz Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 13.4 20 10* 5* 2 6.0 4.0 4.0 0.5 8.0 1 Condition B Min 10 -- -- -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- -- Max 10 6.7 20 10* 5* 4 3 Unit bits s pF k 3.0 2.0 2.0 0.5 4.0 LSB LSB LSB LSB LSB 709 21.5 D/A Convervion Characteristics Table 21-10 lists the D/A conversion characteristics Table 21-10 D/A Conversion Characteristics Condition A: VCC = AVCC = 2.7 V to 5.5 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, o = 2 to 10 MHz, T a = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition B: VCC = AVCC = 5.0 V 10%, Vref = 4.5 V to AVCC, VSS = AVSS = 0 V, o = 2 to 20 MHz, T a = -20 to +75C (regular specifications), Ta = -40 to +85C (wide-range specifications) Condition A Item Resolution Conversion time Absolute accuracy Min 8 -- -- -- Typ 8 -- 2.0 -- Max 8 10 3.0 2.0 Min 8 -- -- -- Condition B Typ 8 -- 1.0 -- Max 8 10 1.5 1.0 Unit bit s LSB LSB 20-pF capacitive load 2-M resistive load 4-M resistive load Test Conditions 21.6 Usage Note Although both the ZTAT and mask ROM versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip ROM, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. Therefore, if a system is evaluated using the ZTAT version, a similar evaluation should also be performed using the mask ROM version. 710 Appendix A Instruction Set A.1 Instruction List Operand Notation Rd Rs Rn ERn MAC (EAd) (EAs) EXR CCR N Z V C PC SP #IMM disp + - x / ( ) <> :8/:16/:24/:32 General register (destination)* 1 General register (source)* 1 General register* 1 General register (32-bit register) Multiply-and-accumulate register (32-bit register)*2 Destination operand Source operand Extended control register Condition-code register N (negative) flag in CCR Z (zero) flag in CCR V (overflow) flag in CCR C (carry) flag in CCR Program counter Stack pointer Immediate data Displacement Add Subtract Multiply Divide Logical AND Logical OR Logical exclusive OR Transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right Logical NOT (logical complement) Contents of operand 8-, 16-, 24-, or 32-bit length Notes: 1. General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0 to R7, E0 to E7), and 32-bit registers (ER0 to ER7). 2. The MAC register cannot be used in the H8S/2350 Series. 711 Condition Code Notation Symbol Changes according to the result of instruction * 0 1 -- Undetermined (no guaranteed value) Always cleared to 0 Always set to 1 Not affected by execution of the instruction 712 Table A-1 Instruction Set (1) Data Transfer Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation #xx:8Rd8 2 2 4 8 2 2 4 6 2 4 8 2 2 4 6 @aa:8Rd8 @aa:16Rd8 @aa:32Rd8 Rs8@ERd Rs8@(d:16,ERd) Rs8@(d:32,ERd) ERd32-1ERd32,Rs8@ERd Rs8@aa:8 Rs8@aa:16 Rs8@aa:32 #xx:16Rd16 W4 W W 2 2 Rs16Rd16 @ERsRd16 @(d:16,ERs)Rd8 @(d:32,ERs)Rd8 @ERsRd8,ERs32+1ERs32 @ERsRd8 Rs8Rd8 B2 B B B B B B B B B B B B B B B I H N Z V C Normal Advanced ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 1 1 2 3 5 3 2 3 4 2 3 5 3 2 3 4 2 1 2 MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W @ERs,Rd MOV.W Rs,Rd 713 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation @(d:16,ERs)Rd16 @(d:32,ERs)Rd16 2 4 6 2 4 8 2 4 6 Rs16@ERd Rs16@(d:16,ERd) Rs16@(d:32,ERd) @aa:32Rd16 @aa:16Rd16 W W W W W W W W W W W L6 L L L L L L L 4 6 10 4 6 8 2 8 4 -- MOV.L @aa:32,ERd @aa:32ERd32 ---- 714 Addressing Mode/ Instruction Length (Bytes) Condition Code ---- ---- 0-- 0-- 0-- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- Rs16@aa:16 Rs16@aa:32 #xx:32ERd32 ERs32ERd32 @ERsERd32 @(d:16,ERs)ERd32 @(d:32,ERs)ERd32 ---- ---- ---- ---- ---- ---- ---- @ERsERd32,ERs32+4ERs32 -- -- @aa:16ERd32 ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 3 5 3 3 4 2 3 5 3 3 4 3 1 4 5 7 5 5 6 @ERsRd16,ERs32+2ERs32 -- -- ERd32-2ERd32,Rs16@ERd -- -- Table A-1 Instruction Set (cont) (1) Data Transfer Instructions (cont) No. of States*1 I H N Z V C Normal Advanced MOV MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd Table A-1 Instruction Set (cont) (1) Data Transfer Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation ERs32@ERd 6 10 4 6 8 2 4 2 4 4 ERs32@aa:16 ERs32@aa:32 @SPRn16,SP+2SP @SPERn32,SP+4SP SP-2SP,Rn16@SP SP-4SP,ERn32@SP (@SPERn32,SP+4SP) Repeated for each register restored L 4 (SP-4SP,ERn32@SP) Repeated for each register saved Cannot be used in the H8S/2350 Series Cannot be used in the H8S/2350 Series ERs32@(d:32,ERd) ERs32@(d:16,ERd) L 4 I H N Z V C Normal Advanced ---- ---- ---- 0-- 0-- 0-- 0-- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- ------------ 4 5 7 5 5 6 3 5 3 5 7/9/11 [1] MOV MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) L MOV.L ERs,@(d:32,ERd) L L L L W L W L L MOV.L ERs,@-ERd ERd32-4ERd32,ERs32@ERd -- -- MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 POP POP.W Rn POP.L ERn PUSH.L ERn LDM LDM @SP+,(ERm-ERn) STM STM (ERm-ERn),@-SP ------------ PUSH PUSH.W Rn 7/9/11 [1] MOVFPE MOVFPE @aa:16,Rd [2] [2] MOVTPE MOVTPE Rs,@aa:16 715 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation Rd8+#xx:8Rd8 2 Rd16+#xx:16Rd16 2 Rd16+Rs16Rd16 ERd32+#xx:32ERd32 2 ERd32+ERs32ERd32 Rd8+#xx:8+CRd8 2 2 2 2 2 2 2 2 2 2 B W4 2 Rd8+Rs8+CRd8 ERd32+1ERd32 ERd32+2ERd32 ERd32+4ERd32 Rd8+1Rd8 Rd16+1Rd16 Rd16+2Rd16 ERd32+1ERd32 ERd32+2ERd32 Rd8 decimal adjustRd8 B Rd8-Rs8Rd8 Rd16-#xx:16Rd16 Rd8+Rs8Rd8 B2 B W4 W L6 L B2 B L L L B W W L L -- ADD ADD.B #xx:8,Rd -- -- ADDX Rs,Rd -- [5] SUB SUB.B Rs,Rd -- SUB.W #xx:16,Rd -- [3] 716 Addressing Mode/ Instruction Length (Bytes) Condition Code 1 1 -- [3] 2 -- [3] 1 -- [4] 3 -- [4] -- 1 [5] 1 1 ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- ---- -- --* * 1 1 1 1 1 1 1 1 1 1 2 Table A-1 Instruction Set (2) Arithmetic Instructions No. of States*1 I H N Z V C Normal Advanced ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDX ADDX #xx:8,Rd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA DAA Rd Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic W L6 L B2 B L L L B W W L L B B W 2 2 2 2 2 2 2 2 2 2 2 2 Rd8-#xx:8-CRd8 Rd8-Rs8-CRd8 ERd32-1ERd32 ERd32-2ERd32 ERd32-4ERd32 Rd8-1Rd8 Rd16-1Rd16 Rd16-2Rd16 ERd32-1ERd32 ERd32-2ERd32 Rd8 decimal adjustRd8 2 ERd32-ERs32ERd32 ERd32-#xx:32ERd32 2 Rd16-Rs16Rd16 Operation I H N Z V C Normal Advanced -- [3] 1 -- [4] 3 -- [4] -- -- 1 [5] [5] 1 1 ------------ ------------ ------------ ---- ---- ---- ---- ---- --* -- -- -- -- -- *-- 1 1 1 1 1 1 1 1 1 SUB SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBX Rs,Rd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DAS DAS Rd MULXU MULXU.B Rs,Rd Rd8xRs8Rd16 (unsigned multiplication) -- -- -- -- -- -- Rd16xRs16ERd32 (unsigned multiplication) DEC.L #2,ERd SUBX SUBX #xx:8,Rd 12 ------------ 20 MULXU.W Rs,ERd MULXS MULXS.B Rs,Rd B W 4 4 Rd8xRs8Rd16 (signed multiplication) Rd16xRs16ERd32 (signed multiplication) ---- ---- ---- ---- 13 21 MULXS.W Rs,ERd 717 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation B 2 -- NEG.L ERd L W L 2 2 2 0-ERd32ERd32 0( -- EXTU.L ERd ---- 0 718 Addressing Mode/ Instruction Length (Bytes) Condition Code Rd16/Rs8Rd16 (RdH: remainder, -- -- [6] [7] -- -- RdL: quotient) (unsigned division) W 2 ERd32/Rs16ERd32 (Ed: remainder, -- -- [6] [7] -- -- Rd: quotient) (unsigned division) B 4 Rd16/Rs8Rd16 (RdH: remainder, -- -- [8] [7] -- -- RdL: quotient) (signed division) W 4 ERd32/Rs16ERd32 (Ed: remainder, -- -- [8] [7] -- -- Rd: quotient) (signed division) B2 B W4 W L6 L B W 2 2 2 2 2 Rd8-#xx:8 Rd8-Rs8 Rd16-#xx:16 Rd16-Rs16 ERd32-#xx:32 ERd32-ERs32 0-Rd8Rd8 0-Rd16Rd16 -- -- 1 1 -- [3] 2 -- [3] 1 -- [4] 3 -- [4] -- -- 1 1 1 1 ---- 0 0-- 0-- 1 1 21 13 20 12 Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) No. of States*1 I H N Z V C Normal Advanced DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd DIVXS divxs.B Rs,Rd DIVXS.W Rs,ERd CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd NEG NEG.B Rd NEG.W Rd EXTU EXTU.W Rd Table A-1 Instruction Set (cont) (2) Arithmetic Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation ( I H N Z V C Normal Advanced EXTS EXTS.W Rd ---- 0-- 1 ( TAS TAS @ERd B 4 @ERd-0CCR set, (1) ( ---- EXTS.L ERd L 2 ( ---- 0-- 1 0-- 4 MAC MAC @ERn+, @ERm+ Cannot be used in the H8S/2350 Series [2] CLRMAC CLRMAC LDMAC LDMAC ERs,MACH LDMAC ERs,MACL STMAC STMAC MACH,ERd STMAC MACL,ERd 719 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation Rd8#xx:8Rd8 2 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 ERd32ERs32ERd32 Rd8#xx:8Rd8 2 Rd8Rs8Rd8 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 ERd32ERs32ERd32 Rd8#xx:8Rd8 2 Rd8Rs8Rd8 Rd16#xx:16Rd16 2 Rd16Rs16Rd16 ERd32#xx:32ERd32 4 B W L 2 2 2 ERd32ERs32ERd32 L Rd8Rd8 Rd16Rd16 ERd32ERd32 Rd8Rs8Rd8 B2 B W4 W L6 L B2 B W4 W L6 L B2 B W4 W L6 -- NOT.L ERd ---- 720 Addressing Mode/ Instruction Length (Bytes) Condition Code ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 0-- 1 1 2 1 3 2 1 1 2 1 3 2 1 1 2 1 3 2 1 1 1 Table A-1 Instruction Set (3) Logical Instructions No. of States*1 I H N Z V C Normal Advanced AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd NOT NOT.B Rd NOT.W Rd Table A-1 Instruction Set (4) Shift Instructions Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation B B W W L L B B W W L L B B W W L L 2 2 2 2 C MSB LSB 2 0 2 2 2 2 2 MSB LSB C 2 2 2 2 2 C MSB 2 LSB 2 0 2 I H N Z V C Normal Advanced ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L #2,ERd SHLL.L ERd 721 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation -- -- -- 0 -- -- -- -- -- -- -- -- -- -- -- -- -- MSB 2 2 2 -- -- L LSB C C MSB LSB MSB LSB C B B W W L L B B W W L L B B W W L 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -- ROTXR.L #2,ERd ---- 0 ---- 0 0 ---- 0 0 ---- 0 0 ---- 0 0 ---- 0 0 ---- 0 ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0 0 0 0 0 0 0 0 0 0 0 0 722 Addressing Mode/ Instruction Length (Bytes) Condition Code 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Table A-1 Instruction Set (cont) (4) Shift Instructions (cont) No. of States*1 I H N Z V C Normal Advanced SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd ROTXL ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd Table A-1 Instruction Set (cont) (4) Shift Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation B B W W C MSB L L B B W W L L 2 2 2 -- 1 2 -- MSB LSB C 2 -- 2 -- 2 2 2 2 LSB 2 2 I H N Z V C Normal Advanced ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L #2,ERd ROTR.L ERd 723 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation (#xx:3 of Rd8)1 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 4 B 6 (Rn8 of Rd8)1 (Rn8 of @ERd)1 (Rn8 of @aa:8)1 (Rn8 of @aa:16)1 (Rn8 of @aa:32)1 (#xx:3 of Rd8)0 (#xx:3 of @ERd)0 (#xx:3 of @aa:8)0 (#xx:3 of @aa:16)0 (#xx:3 of @aa:32)0 (Rn8 of Rd8)0 (Rn8 of @ERd)0 (Rn8 of @aa:8)0 B (Rn8 of @aa:16)0 (#xx:3 of @aa:16)1 (#xx:3 of @aa:32)1 (#xx:3 of @aa:8)1 (#xx:3 of @ERd)1 B B B B B B B B B B B B B B B B B 2 -- 724 Addressing Mode/ Instruction Length (Bytes) Condition Code ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 4 4 5 6 1 4 4 5 6 1 4 4 5 6 1 4 4 5 Table A-1 Instruction Set (5) Bit-Manipulation Instructions No. of States*1 I H N Z V C Normal Advanced BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- Operation (Rn8 of @aa:32)0 No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B B [ (#xx:3 of @ERd)] B 4 (#xx:3 of @aa:8) [ (#xx:3 of @aa:8)] B 6 (#xx:3 of @aa:16) [ (#xx:3 of @aa:16)] B 8 (#xx:3 of @aa:32) [ (#xx:3 of @aa:32)] B B B B 4 6 4 2 (Rn8 of Rd8)[ (Rn8 of Rd8)] 4 (#xx:3 of @ERd) 2 8 I H N Z V C Normal Advanced ------------ 6 1 ------------ 4 BCLR BCLR Rn,@aa:32 BNOT BNOT #xx:3,Rd (#xx:3 of Rd8)[ (#xx:3 of Rd8)] -- -- -- -- -- -- BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 ------------ 4 BNOT #xx:3,@aa:16 ------------ 5 BNOT #xx:3,@aa:32 ------------ 6 BNOT Rn,Rd ------------ (Rn8 of @ERd)[ (Rn8 of @ERd)] -- -- -- -- -- -- (Rn8 of @aa:8)[ (Rn8 of @aa:8)] -- -- -- -- -- -- (Rn8 of @aa:16) [ (Rn8 of @aa:16)] ------------ 1 4 4 5 BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 B 8 (Rn8 of @aa:32) [ (Rn8 of @aa:32)] ------------ 6 BTST BTST #xx:3,Rd B B B B 2 4 4 6 (#xx:3 of Rd8)Z (#xx:3 of @ERd)Z (#xx:3 of @aa:8)Z (#xx:3 of @aa:16)Z ------ ------ ------ ------ ---- ---- ---- ---- 1 3 3 4 BTST #xx:3,@ERd 725 BTST #xx:3,@aa:16 BTST #xx:3,@aa:8 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation (#xx:3 of @aa:32)Z (Rn8 of Rd8)Z 4 4 6 8 2 4 4 6 8 2 4 4 6 8 2 4 B 4 (Rn8 of @aa:8)Z (Rn8 of @aa:16)Z (Rn8 of @aa:32)Z (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C (#xx:3 of Rd8)C (#xx:3 of @ERd)C (#xx:3 of @aa:8)C (#xx:3 of @aa:16)C (#xx:3 of @aa:32)C C(#xx:3 of Rd8) C(#xx:3 of @ERd) B C(#xx:3 of @aa:8) (Rn8 of @ERd)Z B B B B B B B B B B B B B B B B B 2 8 -- BTST Rn,@aa:32 ------ BILD #xx:3,@aa:32 ---------- 726 Addressing Mode/ Instruction Length (Bytes) Condition Code ------ ------ ------ ------ ------ ---- ---- ---- ---- ---- ---- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 ------------ ------------ ------------ 1 4 4 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) No. of States*1 I H N Z V C Normal Advanced BTST BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic Operation C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8) 4 4 6 8 2 4 4 6 8 2 4 4 6 8 B B 2 4 C(#xx:3 of @ERd) C(#xx:3 of @aa:8) C(#xx:3 of @aa:16) C(#xx:3 of @aa:32) C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C B C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C B B B B B B B B B B B B B B B B 2 8 6 I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 5 6 1 4 4 5 6 1 3 3 4 5 1 3 3 4 5 1 3 BST BST #xx:3,@aa:16 BST #xx:3,@aa:32 BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,@ERd BOR BOR #xx:3,Rd 727 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C 4 4 6 8 2 4 4 6 8 2 4 4 6 8 C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C C(#xx:3 of Rd8)C C(#xx:3 of @ERd)C C(#xx:3 of @aa:8)C C(#xx:3 of @aa:16)C C(#xx:3 of @aa:32)C C[ (#xx:3 of Rd8)]C C[ (#xx:3 of @ERd)]C C[ (#xx:3 of @aa:8)]C C[ (#xx:3 of @aa:16)]C C[ (#xx:3 of @aa:32)]C B B B B B B B B B B B B B B B B B B 2 8 6 4 -- BIXOR #xx:3,@aa:32 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- 728 Addressing Mode/ Instruction Length (Bytes) Condition Code 3 4 5 1 3 3 4 5 1 3 3 4 5 1 3 3 4 5 Table A-1 Instruction Set (cont) (5) Bit-Manipulation Instructions (cont) No. of States*1 I H N Z V C Normal Advanced BOR BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 Table A-1 Instruction Set (6) Branch Instructions Addressing Mode/ Instruction Length (Bytes) Operation Condition Code Branching Condition Operand Size No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa -- Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 2 4 2 4 V=0 Z=1 Z=0 2 4 C=1 2 4 C=0 2 4 CZ=1 2 4 CZ=0 2 else next; 4 PCPC+d Never 2 if condition is true then Always I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 2 3 Bcc BRA d:8(BT d:8) BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 729 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- 730 Addressing Mode/ Instruction Length (Bytes) Operation Branching Condition Table A-1 Instruction Set (cont) (6) Branch Instructions (cont) Condition Code No. of States*1 Mnemonic -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4 2 4 2 4 2 4 NV=1 2 4 NV=0 2 4 N=1 2 N=0 4 2 V=1 I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 2 3 2 3 2 3 2 3 2 3 Bcc BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 Z(NV)=0 -- -- -- -- -- -- ------------ Z(NV)=1 -- -- -- -- -- -- ------------ 2 3 2 3 BGT d:16 BLE d:8 BLE d:16 Table A-1 Instruction Set (cont) (6) Branch Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic Operation PCERn 4 2 2 4 2 4 2 PC@aa:8 PC@-SP,PCPC+d:8 PC@-SP,PCPC+d:16 PC@-SP,PCERn PC@-SP,PCaa:24 PC@-SP,PC@aa:8 2 PC@SP+ PCaa:24 -- -- -- -- -- -- -- -- -- 2 I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 4 3 4 3 4 4 4 2 3 5 4 5 4 5 6 5 JMP JMP @ERn JMP @aa:24 JMP @@aa:8 BSR BSR d:8 BSR d:16 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 RTS RTS 731 Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa Mnemonic Operation PC@-SP,CCR@-SP, EXR@-SP, -- SLEEP ------------ ------------ ------------ 732 Addressing Mode/ Instruction Length (Bytes) Condition Code 1 -- -- -- -- -- 7 [9] RTE -- 5 [9] 2 1 ------------ 2 1 1 3 ------------ 3 4 4 6 ------------ 6 4 ------------ 4 4 ------------ 4 5 ------------ 5 Table A-1 Instruction Set (7) System Control Instructions No. of States*1 I H N Z V C Normal Advanced 8 [9] TRAPA RTE LDC Table A-1 Instruction Set (cont) (7) System Control Instructions (cont) Addressing Mode/ Instruction Length (Bytes) Operand Size Condition Code -- Operation CCRRd8 EXRRd8 No. of States*1 #xx Rn @ERn @(d,ERn) @aa @-ERn/@ERn+ @(d,PC) @@aa Mnemonic B B W W W W W W W W W W W W B2 B4 B2 B4 B2 B4 -- 6 8 8 6 4 4 10 10 6 6 4 EXR@ERd CCR@(d:16,ERd) EXR@(d:16,ERd) CCR@(d:32,ERd) EXR@(d:32,ERd) 4 CCR@ERd 2 2 I H N Z V C Normal Advanced ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 1 3 3 4 4 6 6 4 STC STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd ERd32-2ERd32,CCR@ERd -- -- -- -- -- -- ERd32-2ERd32,EXR@ERd CCR@aa:16 EXR@aa:16 CCR@aa:32 EXR@aa:32 CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR CCR#xx:8CCR EXR#xx:8EXR 2 PCPC+2 ------------ ------------ ------------ ------------ ------------ STC EXR,@-ERd 4 4 4 5 5 1 ------------ 2 1 ------------ 2 1 ------------ ------------ 2 1 STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR ORC ORC #xx:8,CCR ORC #xx:8,EXR XORC XORC #xx:8,CCR XORC #xx:8,EXR 733 NOP NOP Operand Size #xx Rn @ERn @(d,ERn) @-ERn/@ERn+ @aa @(d,PC) @@aa -- 734 Addressing Mode/ Instruction Length (Bytes) Condition Code Operation -- 4 if R4L0 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4L-1R4L Until R4L=0 else next; 4 if R40 Repeat @ER5@ER6 ER5+1ER5 ER6+1ER6 R4-1R4 Until R4=0 else next; ------------ 4+2n *2 -- ------------ 4+2n *2 Table A-1 Instruction Set (8) Block Transfer Instructions No. of States*1 Mnemonic I H N Z V C Normal Advanced EEPMOV EEPMOV.B EEPMOV.W Notes: 1. The number of states is the number of states required for execution when the instruction and its operands are located in on-chip memory. 2. n is the initial value of R4L or R4. [1] Seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] Cannot be used in the H8S/2350 Series. [3] Set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] Set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] Retains its previous value when the result is zero; otherwise cleared to 0. [6] Set to 1 when the divisor is negative; otherwise cleared to 0. [7] Set to 1 when the divisor is zero; otherwise cleared to 0. [8] Set to 1 when the quotient is negative; otherwise cleared to 0. [9] One additional state is required for execution when EXR is valid. A.2 Instruction Codes Table A-2 shows the instruction codes. 735 736 Instruction Format Size 1st byte 8 IMM rs 1 IMM rs 1 0 erd IMM 1 ers 0 erd 0 0 erd 0 erd 0 erd IMM rs IMM rs 6 IMM rs 6 0 erd 0 IMM 4 0 IMM 0 erd abs 1 3 disp 0 disp 1 0 8 disp 0 disp 0 0 7 0 7 6 6 rd 0 IMM 0 IMM abs abs 0 0 7 6 0 IMM 0 7 6 0 IMM 0 1 0 6 IMM 6 6 0 ers 0 erd F IMM rd rd rd rd 8 9 rd rd rd 0 7 0 7 0 0 0 0 9 0 E 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 1 8 0 A A E C 6 1 6 1 A 6 9 6 rd E rd B B B A A 9 9 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L L L L B B B B W W L L B B B B B B B -- -- -- -- Table A-2 Instruction Codes 10th byte Instruction Mnemonic ADD ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd ADDX ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 (BT d:8) BRA d:16 (BT d:16) BRN d:8 (BF d:8) BRN d:16 (BF d:16) Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 4 5 0 disp 3 0 disp 4 0 disp 5 0 disp 6 0 disp 7 0 disp 8 0 disp 9 0 disp A 0 disp B 0 disp C 0 disp D disp E disp 8 F 0 disp 0 disp 0 disp disp disp disp disp disp disp disp disp disp disp 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 F 8 E 8 D 8 C 8 B 8 A 8 9 8 8 8 7 8 6 8 5 8 4 8 3 8 disp 2 2 disp 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 9th byte 10th byte Instruction Mnemonic Bcc BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:8 (BHS d:8) BCC d:16 (BHS d:16) BCS d:8 (BLO d:8) BCS d:16 (BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 BVS d:8 BVS d:16 BPL d:8 BPL d:16 BMI d:8 BMI d:16 BGE d:8 BGE d:16 BLT d:8 BLT d:16 BGT d:8 BGT d:16 BLE d:8 BLE d:16 737 738 Instruction Format Size 1st byte 7 7 0 IMM 0 IMM abs 0 IMM 7 2 0 IMM abs 7 2 0 0 0 7 abs 1 3 rn 0 erd abs 1 abs abs 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 7 6 0 1 IMM 0 7 6 1 IMM 0 abs 1 3 1 IMM 0 erd 1 IMM 1 IMM abs abs 0 7 7 1 IMM 0 7 7 1 IMM 0 abs 1 3 1 IMM 0 erd abs 1 3 0 0 7 0 7 rd 4 4 1 IMM 1 IMM abs abs 0 0 7 4 1 IMM 0 7 4 1 IMM 0 0 0 7 7 0 7 7 0 rd 0 0 7 6 0 7 6 0 rd 8 8 6 2 rn 0 6 2 rn 0 6 2 rn 0 0 6 2 rn 0 rd 8 8 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 A A E C 4 A A E C 7 A A E C 6 A A F D 2 A A F 7 2 D 0 erd 0 7 2 0 2 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B B B B B B B B B B B Table A-2 Instruction Codes (cont) 10th byte Instruction Mnemonic BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 6 1 IMM 0 erd abs 1 abs abs 6 7 1 IMM 3 1 IMM 0 erd abs 1 abs abs 1 IMM 3 0 IMM 0 erd abs 1 abs abs 3 0 IMM 0 erd abs 1 3 rn 0 erd abs 1 3 8 8 0 6 6 rd 1 1 abs abs rn rn 0 0 6 1 rn 0 6 1 rn 0 8 8 abs abs 7 1 0 IMM 0 0 IMM 7 1 0 0 7 1 0 IMM 0 7 1 0 IMM 0 rd 0 0 7 7 7 0 IMM 7 0 0 IMM 0 7 7 0 IMM 0 0 0 IMM 7 7 0 rd 0 0 7 5 0 7 5 1 IMM 0 7 1 IMM 5 0 0 1 IMM 7 5 0 rd 8 8 6 7 0 1 IMM 0 6 1 IMM 7 0 0 1 IMM 6 7 0 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 A A F D 1 A A F D 1 A A E C 7 A A E C 5 A A F D 7 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte B B B B B B B B B B B B B B B B B B B B B B B B B 9th byte 10th byte Instruction Mnemonic BIST BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 739 740 Instruction Format Size 1st byte 7 7 7 abs 1 abs abs 7 4 0 IMM 0 IMM 3 0 IMM 0 erd 0 IMM 0 IMM abs abs 7 0 0 IMM 0 7 0 0 IMM 0 0 abs 1 3 rn 0 erd abs 1 abs abs 3 disp 0 disp 0 IMM 0 erd abs 1 3 0 IMM 0 erd abs 1 3 rn 3 C 0 erd 0 0 rd 0 6 3 rn 0 0 rd 7 7 3 3 0 IMM 0 IMM abs abs 0 0 7 3 0 IMM 0 7 3 0 IMM 0 8 8 6 7 0 6 7 0 IMM 0 IMM abs abs rd 0 0 6 7 0 IMM 0 6 7 0 IMM 0 0 8 8 6 0 6 0 rn 0 rn 0 6 0 rn 0 0 6 0 rn 0 rd 8 8 7 0 0 7 0 0 rd 0 0 7 4 0 0 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 A A E C 3 A A F D 7 C 5 A A F D 0 A A F D 0 A A E 0 IMM 7 4 0 C 0 IMM 0 erd 0 7 4 0 4 0 IMM rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B B B B B B B B B B B B B B -- -- B B B B B B B B B B B B Table A-2 Instruction Codes (cont) 10th byte Instruction Mnemonic BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 BSR BSR d:8 BSR d:16 BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 7 6 6 7 7 7 6 6 Cannot be used in the H8S/2350 Series A 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 B B 3 rs 5 D 1 rs 1 D 0 rd 0 erd C 4 5 5 9 9 8 8 F F 1 D 0 B F 0 erd 5 5 1 3 rs rs rd 0 erd B 7 0 erd B D rd B 5 rd A 0 rd F 0 rd F 0 rd F 1 ers 0 erd A IMM 2 0 erd D rs rd 9 IMM 2 rd C rs rd rd IMM A abs 3 0 7 A abs 0 IMM 1 0 7 5 0 5 0 IMM 0 E abs 0 IMM 7 5 0 C 0 IMM 0 erd 0 7 5 0 5 0 IMM rd A abs 3 0 6 3 rn 0 A abs 1 0 6 3 rn 0 E abs 6 3 rn 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte B B B B B B B B -- B B W W L L B B B W W L L B W B W -- -- 9th byte 10th byte Instruction Mnemonic BTST BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CLRMAC CMP CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAA Rd DAS DAS Rd DEC DEC.B Rd DEC.W #1,Rd DEC.W #2,Rd DEC.L #1,ERd DEC.L #2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV EEPMOV.B EEPMOV.W 741 742 Instruction Format Size 1st byte 1 1 0 erd rd 0 erd rd rd rd 0 erd 0 erd 0 abs abs 0 ern abs abs IMM 4 IMM 0 1 4 4 4 4 4 4 4 4 4 1 1 4 1 0 1 0 1 0 1 6 7 7 6 6 6 6 0 6 1 6 9 F F 8 8 D D B B 0 6 9 rs 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 ers 0 0 0 0 0 0 0 0 0 0 0 0 disp disp 6 6 B B disp disp 2 2 0 0 disp disp rs 1 0 7 0 1 1 0 0 0 0 0 5 0 ern 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 3 3 1 7 F E D B A 9 B F B 7 B D B 5 A 0 7 7 7 5 7 F 7 D rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W L W L B W W L L -- -- -- -- -- -- B B B B W W W W W W W W W W Table A-2 Instruction Codes (cont) 10th byte Instruction Mnemonic EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 JSR JSR @ERn JSR @aa:24 JSR @@aa:8 LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 0 0 0 0 ern+1 0 ern+2 0 ern+3 0 0 Cannot be used in the H8S/2350 Series 1 3 0 6 D 7 1 2 0 6 D 7 1 1 0 6 D 7 1 0 4 abs 1 6 B 2 1 0 4 abs 0 6 B 2 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte W W L L L L L -- B B B B B rd B B B B B B B B B B B W W W W W 7 6 F 8 6 9 0 D rs 0 ers 0 ers 0 ers 7 9 0 6 A A rs rd rd rd rd 0 6 B disp 2 rd disp IMM 6 A 8 rs 3 rs abs abs abs 6 C 1 erd rs 7 8 0 erd 0 6 A 6 E 1 erd rs disp A rs disp 6 8 1 erd rs 6 A 2 rd 6 A abs abs 0 rd 2 rd abs 6 C 0 ers rd 7 8 0 ers 0 6 A 2 6 E 0 ers disp disp rd 6 8 0 ers rd 0 C rs rd F rd IMM 9th byte 10th byte Instruction Mnemonic LDC LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ MOV MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd 743 MOV.W @(d:32,ERs),Rd 744 Instruction Format Size 1st byte 6 6 6 6 6 7 6 6 6 7 0 0 0 ers 0 erd 0 ers 0 erd 0 ers 0 ers 0 erd 0 0 erd 0 erd 2 abs abs 0 6 B disp 2 0 erd disp 0 0 0 0 0 0 0 0 0 0 0 1 0 0 6 1 0 0 6 1 0 0 6 D B B 1 0 0 7 8 1 0 0 6 F 1 0 0 6 9 1 0 0 6 B 1 0 0 6 B 1 0 0 6 D 1 0 0 7 8 1 0 0 6 F 1 0 0 6 9 F 1 ers 0 erd A 0 0 erd IMM B A rs abs B 8 rs abs D 1 erd rs 8 0 erd 0 6 B A rs disp F 1 erd rs disp 9 1 erd rs B 2 rd abs B 0 rd abs D 0 ers rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W W W W W W L L L L L L L L L L 1 erd 0 ers 1 erd 0 ers 0 erd 0 1 erd 0 ers 8 A 0 ers 0 ers abs abs 6 B disp A 0 ers disp L L L B B B 0 0 5 5 0 2 1 1 W B W C C rs rs 0 0 rd 0 erd 5 5 0 2 rs rs rd 0 erd Cannot be used in the H8S/2350 Series Table A-2 Instruction Codes (cont) 10th byte Instruction Mnemonic MOV MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)* L MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE MOVFPE @aa:16,Rd MOVTPE MOVTPE Rs,@aa:16 MULXS MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 1 1 1 0 erd 0 rd rd 0 erd IMM rs 4 IMM rs 4 0 erd IMM 6 4 0 ers 0 erd 0 IMM 4 0 4 IMM 7 0 6 D 7 F 0 6 D 8 C 9 D B F 0 erd 0 erd rd rd rd rd 0 F rn 0 ern 0 0 ern rn 1 F rd rd rd 0 1 1 1 C 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 2 2 2 2 2 2 1 D 1 D 1 4 1 A 4 9 4 rd 7 3 7 1 7 0 0 0 7 B 7 9 rd 7 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte B W L -- B W L B B W W L L B B W L W L B B W W L L 9th byte 10th byte Instruction Mnemonic NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOP NOT NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 745 746 Instruction Format Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 0 rd rd rd rd 0 erd 0 erd 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 0 F 0 B 0 D 0 9 0 C 0 8 4 7 6 7 3 7 3 3 3 5 3 1 3 4 3 0 2 7 2 3 2 5 2 1 2 4 2 0 3 F 3 B 3 D rd 3 9 rd 3 C rd 3 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte B B W W L L B B W W L L B B W W L L -- -- B B W W L L Table A-2 Instruction Codes (cont) 10th byte Instruction Mnemonic ROTR ROTR.B Rd ROTR.B #2, Rd ROTR.W Rd ROTR.W #2, Rd ROTR.L ERd ROTR.L #2, ERd ROTXL ROTXL.B Rd ROTXL.B #2, Rd ROTXL.W Rd ROTXL.W #2, Rd ROTXL.L ERd ROTXL.L #2, ERd ROTXR ROTXR.B Rd ROTXR.B #2, Rd ROTXR.W Rd ROTXR.W #2, Rd ROTXR.L ERd ROTXR.L #2, ERd RTE RTE RTS RTS SHAL SHAL.B Rd SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 1 1 1 1 1 0 erd 0 erd rd rd rd rd 0 erd 0 erd rd rd rd rd 0 erd 0 erd 0 rd rd 0 1 0 1 0 4 4 1 1 1 0 4 4 1 0 1 6 6 6 6 7 7 6 6 9 9 F F 8 8 D D 1 erd 1 erd 1 erd 1 erd 0 erd 0 erd 1 erd 1 erd 0 0 0 0 0 0 0 0 6 6 B B disp disp A A 0 0 disp disp 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 4 1 4 1 4 1 4 2 1 2 0 1 8 1 7 1 3 1 5 1 1 1 4 1 0 0 7 0 3 0 5 0 1 0 4 0 0 1 F 1 B 1 D rd 1 9 rd 1 C rd 1 8 rd 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte B B W W L L B B W W L L B B W W L L -- B B W W 9th byte 10th byte Instruction Mnemonic SHAR SHAR.B Rd SHAR.B #2, Rd SHAR.W Rd SHAR.W #2, Rd SHAR.L ERd SHAR.L #2, ERd SHLL SHLL.B Rd SHLL.B #2, Rd SHLL.W Rd SHLL.W #2, Rd SHLL.L ERd SHLL.L #2, ERd SHLR SHLR.B Rd SHLR.B #2, Rd SHLR.W Rd SHLR.W #2, Rd SHLR.L ERd SHLR.L #2, ERd SLEEP SLEEP STC STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W W STC.W CCR,@-ERd STC.W EXR,@-ERd 747 748 Instruction Format Size 1st byte 0 abs abs abs abs 0 0 0 0 0 ern 0 ern 0 ern 0 0 Cannot be used in the H8S/2350 Series 1 3 0 6 D F 1 2 0 6 D F 1 1 0 6 D F 1 4 1 6 B A 0 1 4 0 6 B A 0 1 4 1 6 B 8 0 1 4 0 6 B 8 0 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte W W W W L L L L L B W IMM W L IMM L L L L B IMM rs E 00 IMM IMM rs 5 rs 5 F rd rd 0 erd 0 6 5 IMM 0 ers 0 erd rd IMM 0 0 7 B rd 0 erd C B B -- B B W W L L 0 1 7 A 6 5 7 9 1 5 D rd 5 7 0 1 1 E B rd 1 B 9 0 erd 1 B 8 0 erd 1 B 0 0 erd 1 A 1 ers 0 erd 7 A 3 0 erd 1 9 rs rd 7 9 3 rd 1 8 rs rd Table A-2 Instruction Codes (cont) 10th byte Instruction Mnemonic STC STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 STM STM.L(ERn-ERn+1), @-SP STM.L (ERn-ERn+2), @-SP STM.L (ERn-ERn+3), @-SP STMAC STMAC MACH,ERd STMAC MACL,ERd SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBS #1,ERd SUBS #2,ERd SUBS #4,ERd SUBX SUBX #xx:8,Rd SUBX Rs,Rd TAS TAS @ERd TRAPA TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd Table A-2 Instruction Codes (cont) Instruction Format Size 1st byte 0 0 1 4 1 0 5 IMM 5 IMM 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte B B 9th byte 10th byte Instruction Mnemonic XORC XORC #xx:8,CCR XORC #xx:8,EXR Note: * Bit 7 of the 4th byte of the MOV.L ERs, @(d:32,ERd) instruction can be either 1 or 0. Legend IMM: abs: disp: rs, rd, rn: ers, erd, ern, erm: Immediate data (2, 3, 8, 16, or 32 bits) Absolute address (8, 16, 24, or 32 bits) Displacement (8, 16, or 32 bits) Register field (4 bits specifying an 8-bit or 16-bit register. The symbols rs, rd, and rn correspond to operand symbols Rs, Rd,and Rn.) Register field (3 bits specifying an address register or 32-bit register. The symbols ers, erd, ern, and erm correspond to operand symbols ERs, ERd, ERn, and ERm.) The register fields specify general registers as follows. 16-Bit Register Register Field 0000 0001 * * * 0111 1000 1001 * * * 1111 R0 R1 * * * R7 E0 E1 * * * E7 0000 0001 * * * 0111 1000 1001 * * * 1111 General Register Register Field 8-Bit Register General Register R0H R1H * * * R7H R0L R1L * * * R7L Address Register 32-Bit Register Register Field General Register 000 001 * * * 111 ER0 ER1 * * * ER7 749 750 Instruction when most significant bit of BH is 0. 2nd byte BH BL Instruction when most significant bit of BH is 1. 2 4 9 C MOV CMP ADD SUB A B ORC OR MOV.B XOR AND Table A.3(2) XORC ANDC LDC 5 6 7 8 3 D E ADDX SUBX F Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) Table A.3(2) BLS BCC BEQ TRAPA BST MOV MOV Table A.3(2) Table A.3(2) JMP BVC BVS BPL RTS BSR RTE BNE DIVXU BTST BCS BMI BGE BSR MOV EEPMOV Table A.3(3) BLT BGT JSR BLE XOR AND OR BIST BOR BLD BXOR BAND BIOR BILD BIXOR BIAND ADD ADDX CMP SUBX OR XOR AND MOV Table A.3(2) Table A.3(2) A.3 Table A-3 Operation Code Map (1) Instruction code 1st byte AH AL AL AH 0 1 0 NOP Operation Code Map 1 Table A.3(2) LDC Table STC * * A.3(2) STMAC LDMAC Table Table Table A.3(2) A.3(2) A.3(2) Table A-3 shows the operation code map. 2 3 4 BRA BRN BHI 5 MULXU DIVXU MULXU 6 BSET BNOT BCLR 7 8 9 A B C D E F Note: * Cannot be used in the H8S/2350 Series. Table A-3 Operation Code Map (2) 2nd byte BH BL Instruction code AL 1st byte AH BH 2 5 MAC* SLEEP CLRMAC * 6 7 B 8 STM STC LDC 3 4 9 A AH AL 0 1 C Table A.3(3) ADD D Table A.3(3) E TAS F Table A.3(3) 01 MOV LDM 0A INC INC ADDS INC 0B ADDS INC MOV INC 0F SHLL SHLL SHLR ROTXL ROTXR EXTU EXTU SHAR ROTL ROTR NEG SHAL SHLR ROTXL ROTXR NOT DAA 10 SHLL SHAL SHAR ROTL ROTR NEG SUB EXTS SHAL SHAR ROTL ROTR EXTS 11 SHLR 12 ROTXL 13 ROTXR 17 NOT 1A DEC DEC DEC SUBS 1B SUBS DEC CMP DEC 1F BHI MOV CMP CMP SUB SUB OR OR Table * A.3(4) MOVFPE XOR XOR BLS BCC BCS DAS BNE BEQ BVC MOV AND AND BVS BPL MOV BMI 58 BRA BRN BGE MOVTPE* BLT BGT BLE 6A MOV Table A.3(4) 79 MOV ADD 7A MOV ADD Note: * Cannot be used in the H8S/2350 Series. 751 752 2nd byte BH BL CH CL DH DL 3rd byte 4th byte Instruction when most significant bit of DH is 0. Instruction when most significant bit of DH is 1. 1 MULXS DIVXS OR BTST BTST BCLR BCLR BTST BTST BCLR BCLR XOR AND 2 3 4 5 6 7 8 9 A B C D E F BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST Table A-3 Operation Code Map (3) Instruction code 1st byte AH AL CL AH AL BH BL CH 0 01C05 MULXS 01D05 DIVXS 01F06 7Cr06 *1 7Cr07 *1 7Dr06 *1 BSET BNOT 7Dr07 *1 BSET BNOT 7Eaa6 *2 7Eaa7 *2 7Faa6 *2 BSET BNOT 7Faa7 *2 BSET BNOT Notes: 1. r is the register specification field. 2. aa is the absolute address specification. Table A-3 Operation Code Map (4) 2nd byte BH BL CH CL DH DL EH EL FH FL Instruction when most significant bit of FH is 0. Instruction when most significant bit of FH is 1. 1 4 5 6 7 8 9 A BTST BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 2 3 B C D E F 3rd byte 4th byte 5th byte 6th byte Instruction code 1st byte AH AL EL AHALBHBLCHCLDHDLEH 0 6A10aaaa6* 6A10aaaa7* 6A18aaaa6* BCLR BSET BNOT 6A18aaaa7* Instruction code BH BL CH CL DH DL EH 1st byte 2nd byte 3rd byte 4th byte 5th byte EL 6th byte FH FL 7th byte GH GL 8th byte HH HL Instruction when most significant bit of HH is 0. Instruction when most significant bit of HH is 1. AH AL GL 1 4 5 BTST 2 3 AHALBHBL ... FHFLGH 0 6 7 8 9 A B C D E F 6A30aaaaaaaa6* 6A30aaaaaaaa7* 6A38aaaaaaaa6* BCLR BSET BNOT BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 6A38aaaaaaaa7* Note: * aa is the absolute address specification. 753 A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A-4 indicates the number of states required for each cycle. The number of states required for execution of an instruction can be calculated from these two tables as follows: Execution states = I x SI + J x SJ + K x SK + L xS L + M x SM + N x SN Examples: Advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. BSET #0, @FFFFC7:8 From table A-5: I = L = 2, J = K = M = N = 0 From table A-4: S I = 4, SL = 2 Number of states required for execution = 2 x 4 + 2 x 2 = 12 2. JSR @@30 From table A-5: I = J = K = 2, L = M = N = 0 From table A-4: S I = SJ = SK = 4 Number of states required for execution = 2 x 4 + 2 x 4 + 2 x 4 = 24 754 Table A-4 Number of States per Cycle Access Conditions On-Chip Supporting Module External Device 8-Bit Bus 16-Bit Bus Cycle Instruction fetch SI On-Chip 8-Bit Memory Bus 1 4 16-Bit Bus 2 2-State 3-State 2-State 3-State Access Access Access Access 4 6 + 2m 2 3+m Branch address read SJ Stack operation Byte data access Word data access Internal operation SK SL SM SN 1 2 4 1 1 2 4 1 3+m 6 + 2m 1 1 1 Legend m: Number of wait states inserted into external device access 755 Table A-5 Number of Cycles in Instruction Execution Branch Address Read J Instruction Fetch Instruction ADD Mnemonic ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS ADDX ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC ANDC #xx:8,CCR ANDC #xx:8,EXR BAND BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 Bcc BRA d:8 BRN d:8 BHI d:8 BLS d:8 BCC d:8 BCS d:8 BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 BLE d:8 BRA d:16 BRN d:16 (BT d:16) (BF d:16) (BHS d:8) (BLO d:8) (BT d:8) (BF d:8) I 1 1 2 1 3 1 1 1 1 1 1 2 1 3 2 1 2 1 2 2 3 4 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 756 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Address Read J Instruction Fetch Instruction Bcc Mnemonic BHI d:16 BLS d:16 BCC d:16 BCS d:16 BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR BIOR #xx:8,Rd BIOR #xx:8,@ERd BIOR #xx:8,@aa:8 BIOR #xx:8,@aa:16 BIOR #xx:8,@aa:32 (BHS d:16) (BLO d:16) I 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 757 Table A-5 Number of Cycles in Instruction Execution (cont) Instruction Fetch Branch Address Read J Stack Operation K Byte Data Access L 2 2 2 2 Word Data Access M Internal Operation N Instruction BIST Mnemonic BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 I 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 BIXOR BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 1 1 1 1 BLD BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 1 1 1 1 BNOT BNOT #xx:3,Rd BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 2 2 2 2 2 2 2 2 BOR BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 1 1 1 1 BSET BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 2 2 2 2 2 2 2 2 758 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Address Read J Instruction Fetch Instruction BSR Mnemonic BSR d:8 Normal Advanced BSR d:16 Normal Advanced BST BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC CMP CLRMAC CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA DAS DEC DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU DIVXU.B Rs,Rd DIVXU.W Rs,ERd I 2 2 2 2 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 1 2 2 3 4 Stack Operation K 1 2 1 2 Byte Data Access L Word Data Access M Internal Operation N 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 Cannot be used in the H8S/2350 Series 1 1 2 1 3 1 1 1 1 1 1 2 2 1 1 11 19 11 19 759 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Address Read J Instruction Fetch Instruction EEPMOV Mnemonic EEPMOV.B EEPMOV.W EXTS EXTS.W Rd EXTS.L ERd EXTU EXTU.W Rd EXTU.L ERd INC INC.B Rd INC.W #1/2,Rd INC.L #1/2,ERd JMP JMP @ERn JMP @aa:24 JMP @@aa:8 Normal Advanced JSR JSR @ERn Normal Advanced JSR @aa:24 Normal Advanced JSR @@aa:8 Normal Advanced LDC LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM LDM.L @SP+, (ERn-ERn+1) LDM.L @SP+, (ERn-ERn+2) LDM.L @SP+, (ERn-ERn+3) LDMAC LDMAC ERs,MACH LDMAC ERs,MACL I 2 2 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 1 2 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 Stack Operation K Byte Data Access L 2n+2 *2 2n+2 *2 Word Data Access M Internal Operation N 1 1 2 1 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 Cannot be used in the H8S/2350 Series 760 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Address Read J Instruction Fetch Instruction MAC MOV Mnemonic MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+,Rd MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) I 1 1 1 2 4 1 1 2 3 1 2 4 1 1 2 3 2 1 1 2 4 1 2 3 1 2 4 1 2 3 3 1 2 3 5 2 3 4 2 3 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Cannot be used in the H8S/2350 Series 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 1 761 Table A-5 Number of Cycles in Instruction Execution (cont) Instruction Fetch Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M 2 2 2 2 1 Internal Operation N Instruction MOV Mnemonic MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 I 5 2 3 4 MOVFPE MOVTPE MULXS MOVFPE @:aa:16,Rd MOVTPE Rs,@:aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd Can not be used in the H8S/2350 Series 2 2 1 1 1 1 1 1 1 1 1 1 1 2 1 3 2 1 2 1 2 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 2 11 19 11 19 MULXU MULXU.B Rs,Rd MULXU.W Rs,ERd NEG NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT NOP NOT.B Rd NOT.W Rd NOT.L ERd OR OR.B #xx:8,Rd OR.B Rs,Rd OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC ORC #xx:8,CCR ORC #xx:8,EXR POP POP.W Rn POP.L ERn 1 1 1 1 PUSH PUSH.W Rn PUSH.L ERn ROTL ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd 762 Table A-5 Number of Cycles in Instruction Execution (cont) Branch Address Read J Instruction Fetch Instruction ROTXL Mnemonic ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd RTE RTS RTE RTS Normal Advanced SHAL SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP SLEEP I 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Stack Operation K Byte Data Access L Word Data Access M Internal Operation N 2 / 3 *1 1 2 1 1 1 1 763 Table A-5 Number of Cycles in Instruction Execution (cont) Instruction Fetch Branch Address Read J Stack Operation K Byte Data Access L Word Data Access M Internal Operation N Instruction STC Mnemonic STC.B CCR,Rd STC.B EXR,Rd STC.W CCR,@ERd STC.W EXR,@ERd STC.W CCR,@(d:16,ERd) STC.W EXR,@(d:16,ERd) STC.W CCR,@(d:32,ERd) STC.W EXR,@(d:32,ERd) STC.W CCR,@-ERd STC.W EXR,@-ERd STC.W CCR,@aa:16 STC.W EXR,@aa:16 STC.W CCR,@aa:32 STC.W EXR,@aa:32 I 1 1 2 2 3 3 5 5 2 2 3 3 4 4 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 4 6 8 1 1 1 1 1 STM STM.L (ERn-ERn+1),@-SP STM.L (ERn-ERn+2),@-SP STM.L (ERn-ERn+3),@-SP STMAC STMAC MACH,ERd STMAC MACL,ERd Cannot be used in the H8S/2350 Series 1 2 1 3 1 1 1 1 2 Normal Advanced 2 2 1 1 2 1 3 2 1 2 1 2 2 / 3 *1 2 / 3 *1 2 2 2 SUB SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS SUBX SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS TRAPA TAS @ERd TRAPA #x:2 XOR XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd XORC XORC #xx:8,CCR XORC #xx:8,EXR Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 764 A.5 Bus States During Instruction Execution Table A-6 indicates the types of cycles that occur during instruction execution by the CPU. See table A-4 for the number of states per cycle. How to Read the Table: Order of execution Instruction JMP@aa:24 1 R:W 2nd 2 3 4 5 6 7 8 Internal operation R:W EA 1 state End of instruction Read effective address (word-size read) No read or write Read 2nd word of current instruction (word-size read) Legend R:B R:W W:B W:W :M 2nd 3rd 4th 5th NEXT EA VEC Byte-size read Word-size read Byte-size write Word-size write Transfer of the bus is not performed immediately after this cycle Address of 2nd word (3rd and 4th bytes) Address of 3rd word (5th and 6th bytes) Address of 4th word (7th and 8th bytes) Address of 5th word (9th and 10th bytes) Address of next instruction Effective address Vector address 765 Figure A-1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. o Address bus RD HWR, LWR High level R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1nd byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A-1 Address Bus, RD, HWR, and LWR Timing (8-Bit Bus, Three-State Access, No Wait States) 766 Table A-6 Instruction Execution Cycles 2 3 4 5 6 7 8 9 R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:W 3rd R:W NEXT R:W NEXT R:B EA R:B EA R:W 3rd R:W 3rd R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W NEXT Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.L ERs,ERd ANDC #xx:8,CCR ANDC #xx:8,EXR BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BRA d:8 (BT d:8) BRN d:8 (BF d:8) BHI d:8 BLS d:8 BCC d:8 (BHS d:8) BCS d:8 (BLO d:8) BNE d:8 BEQ d:8 BVC d:8 BVS d:8 BPL d:8 BMI d:8 BGE d:8 BLT d:8 BGT d:8 1 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 767 768 3 R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA R:W EA 4 5 6 7 8 9 2 R:W EA Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W:M NEXT W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Table A-6 Instruction Execution Cycles (cont) Instruction BLE d:8 BRA d:16 (BT d:16) 1 R:W NEXT R:W 2nd BRN d:16 (BF d:16) R:W 2nd BHI d:16 R:W 2nd BLS d:16 R:W 2nd BCC d:16 (BHS d:16) R:W 2nd BCS d:16 (BLO d:16) R:W 2nd BNE d:16 R:W 2nd BEQ d:16 R:W 2nd BVC d:16 R:W 2nd BVS d:16 R:W 2nd BPL d:16 R:W 2nd BMI d:16 R:W 2nd BGE d:16 R:W 2nd BLT d:16 R:W 2nd BGT d:16 R:W 2nd BLE d:16 R:W 2nd BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:W NEXT R:W 2nd R:W 2nd R:W 2nd Table A-6 Instruction Execution Cycles (cont) 2 R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W 4th 4 R:B:M EA 5 6 R:W:M NEXT W:B EA 7 8 9 R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #xx:3,@aa:32 BLD #xx:3,Rd BLD #xx:3,@ERd BLD #xx:3,@aa:8 BLD #xx:3,@aa:16 BLD #xx:3,@aa:32 BNOT #xx:3,Rd 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT 769 770 2 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:B EA R:W 3rd R:W 3rd R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:W stack W:W:M stack (H) R:W EA W:W stack (L) W:W stack W:W:M stack (H) W:W stack (L) R:W EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA R:W:M NEXT R:W:M NEXT R:B EA R:W:M NEXT R:W 4th R:B EA R:W:M NEXT R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 3 R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th 4 5 6 W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA 7 8 9 R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:W EA R:W EA Internal operation, 1 state Internal operation, 1 state R:B:M EA R:B:M EA R:W 3rd R:W 3rd R:B EA R:W:M NEXT R:W:M NEXT R:B:M EA R:W 4th R:W:M NEXT W:B EA W:B EA R:W:M NEXT W:B EA R:B:M EA R:W:M NEXT W:B EA Table A-6 Instruction Execution Cycles (cont) Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3,Rd BSET #xx:3,@ERd BSET #xx:3,@aa:8 BSET #xx:3,@aa:16 BSET #xx:3,@aa:32 BSET Rn,Rd BSET Rn,@ERd BSET Rn,@aa:8 BSET Rn,@aa:16 BSET Rn,@aa:32 Normal BSR d:8 Advanced Normal BSR d:16 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd Advanced R:W 2nd BST #xx:3,Rd BST #xx:3,@ERd BST #xx:3,@aa:8 BST #xx:3,@aa:16 BST #xx:3,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd Table A-6 Instruction Execution Cycles (cont) 4 R:W:M NEXT R:B EA R:W:M NEXT 5 6 7 8 9 R:W:M NEXT R:B EA R:W:M NEXT Instruction BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 BTST #xx:3,@aa:32 BTST Rn,Rd BTST Rn,@ERd BTST Rn,@aa:8 BTST Rn,@aa:16 BTST Rn,@aa:32 BXOR #xx:3,Rd BXOR #xx:3,@ERd BXOR #xx:3,@aa:8 BXOR #xx:3,@aa:16 BXOR #xx:3,@aa:32 CLRMAC R:W:M NEXT R:B EA R:W:M NEXT 1 2 3 R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th R:W NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:B EA R:W:M NEXT R:W 2nd R:W 3rd R:B EA R:W 2nd R:W 3rd R:W 4th Cannot be used in the H8S/2350 Series R:W NEXT R:W 3rd R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 R:B EAd*1 R:B EAs*2 W:B EAd*2 R:B EAs*1 Repeated n times*2 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 771 772 2 3 4 5 6 7 8 9 R:W EA Internal operation, R:W EA 1 state R:W aa:8 Internal operation, R:W EA 1 state R:W:M aa:8 R:W aa:8 Internal operation, R:W EA 1 state R:W EA W:W stack R:W EA W:W:M stack (H) W:W stack (L) Internal operation, R:W EA W:W stack 1 state Internal operation, R:W EA W:W:M stack (H) W:W stack (L) 1 state R:W aa:8 W:W stack R:W EA R:W:M aa:8 R:W aa:8 W:W:M stack (H) W:W stack (L) R:W EA R:W NEXT R:W NEXT R:W NEXT R:W 3rd R:W 3rd R:W 3rd R:W 3rd R:W NEXT R:W EA R:W EA R:W 5th R:W 5th R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W EA R:W NEXT R:W EA R:W:M stack (H)*3 R:W stack (L)*3 R:W NEXT R:W NEXT R:W EA R:W EA R:W EA R:W EA R:W NEXT R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W NEXT Internal operation, 1 state R:W 3rd R:W NEXT R:W 3rd R:W NEXT R:W 3rd R:W 4th R:W 3rd R:W 4th R:W:M NEXT Internal operation, 1 state Table A-6 Instruction Execution Cycles (cont) Instruction INC.W #1/2,Rd INC.L #1/2,ERd JMP @ERn JMP @aa:24 1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd JMP @@aa:8 Normal R:W NEXT Advanced R:W NEXT JSR @ERn JSR @aa:24 Normal R:W NEXT Advanced R:W NEXT Normal R:W 2nd Advanced R:W 2nd JSR @@aa:8 Normal Advanced LDC #xx:8,CCR LDC #xx:8,EXR LDC Rs,CCR LDC Rs,EXR LDC @ERs,CCR LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR R:W 2nd LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.L @SP+, (ERn-ERn+1) R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd Table A-6 Instruction Execution Cycles (cont) 2 R:W NEXT 6 7 8 9 Instruction LDM.L @SP+,(ERn-ERn+2) 1 R:W 2nd LDM.L @SP+,(ERn-ERn+3) LDMAC ERs,MACH 3 4 5 Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state R:W 2nd R:W NEXT Internal operation, R:W:M stack (H)*3 R:W stack (L)*3 1 state Cannot be used in the H8S/2350 Series LDMAC ERs,MACL R:W NEXT R:W EAn R:W EAm MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd R:B EA R:W 4th R:B EA R:W NEXT R:B EA R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:B EA MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@-ERd W:B EA R:W 4th W:B EA R:W NEXT W:B EA R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:B EA R:W NEXT R:W 3rd Internal operation, 1 state R:B EA R:W NEXT R:W 3rd W:B EA R:W NEXT R:W 3rd Internal operation, 1 state W:B EA R:W NEXT R:W 3rd R:W NEXT W:B EA R:W NEXT W:B EA MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd MOV.W @ERs+, Rd R:W EA R:W 4th R:W EA R:W EA R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W EA MOV.W @aa:16,Rd MOV.W @aa:32,Rd MOV.W Rs,@ERd R:W 2nd R:W 2nd R:W NEXT R:W EA R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd W:W EA R:B EA 773 774 4 R:W NEXT W:W EA 3 W:W EA R:E 4th W:W EA 5 6 7 8 9 2 R:W NEXT R:W 3rd Internal operation, 1 state R:W NEXT R:W 3rd R:W 3rd W:W EA R:W NEXT R:W NEXT W:W EA R:W:M NEXT R:W:M 3rd R:W:M 3rd R:W:M NEXT R:W EA+2 R:W NEXT R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W EA+2 R:W:M EA R:W 5th R:W:M EA R:W EA+2 R:W EA+2 R:W:M EA R:W NEXT W:W EA+2 W:W:M EA R:W 5th W:W:M EA W:W EA+2 R:W NEXT W:W EA+2 W:W EA+2 W:W:M EA W:W:M EA R:W NEXT W:W:M EA W:W EA+2 W:W EA+2 R:W NEXT Internal operation, 11 states R:W NEXT Internal operation, 19 states Internal operation, 11 states Internal operation, 19 states Table A-6 Instruction Execution Cycles (cont) Instruction MOV.W Rs,@(d:16,ERd) MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd 1 R:W 2nd R:W 2nd R:W NEXT MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd R:W:M EA R:W NEXT R:W:M 4th Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th R:W 2nd R:W:M NEXT W:W:M EA R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W:M 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M 3rd R:W NEXT R:W 2nd R:W:M 3rd R:W 4th Cannot be used in the H8S/2350 Series R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Table A-6 Instruction Execution Cycles (cont) 2 R:W NEXT R:W 3rd R:W NEXT R:W NEXT 3 4 5 6 7 8 9 Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn R:W EA+2 1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT POP.L ERn R:W 2nd PUSH.W Rn W:W EA+2 R:W NEXT PUSH.L ERn R:W 2nd R:W NEXT Internal operation, R:W EA 1 state R:W:M NEXT Internal operation, R:W:M EA 1 state Internal operation, W:W EA 1 state R:W:M NEXT Internal operation, W:W:M EA 1 state ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd ROTR.B Rd ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd ROTXL.B Rd ROTXL.B #2,Rd ROTXL.W Rd ROTXL.W #2,Rd ROTXL.L ERd ROTXL.L #2,ERd ROTXR.B Rd ROTXR.B #2,Rd ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT 775 776 2 R:W stack (EXR) R:W stack (H) R:W stack R:W stack (L) Internal operation, R:W*4 1 state 1 R:W NEXT R:W NEXT R:W NEXT 3 4 5 6 7 8 9 Internal operation, R:W*4 1 state R:W:M stack (H) R:W stack (L) Internal operation, R:W*4 1 state R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd Internal operation:M R:W NEXT R:W NEXT R:W 3rd W:W EA W:W EA R:W NEXT W:W EA Table A-6 Instruction Execution Cycles (cont) Instruction ROTXR.L #2,ERd RTE RTS Normal Advanced R:W NEXT SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.L ERd SHAR.L #2,ERd SHLL.B Rd SHLL.B #2,Rd SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd SHLR.B Rd SHLR.B #2,Rd SHLR.W Rd SHLR.W #2,Rd SHLR.L ERd SHLR.L #2,ERd SLEEP STC CCR,Rd STC EXR,Rd STC CCR,@ERd STC EXR,@ERd STC CCR,@(d:16,ERd) Table A-6 Instruction Execution Cycles (cont) 5 R:W NEXT R:W NEXT W:W EA W:W EA 2 R:W 3rd R:W 3rd R:W 3rd R:W NEXT W:W EA W:W EA W:W EA R:W NEXT W:W EA R:W NEXT W:W EA W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 W:W:M stack (H)*3 W:W stack (L)*3 4 W:W EA R:W 5th R:W 5th W:W EA 6 7 8 9 Instruction STC EXR,@(d:16,ERd) STC CCR,@(d:32,ERd) STC EXR,@(d:32,ERd) STC CCR,@-ERd 1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd STC EXR,@-ERd STC CCR,@aa:16 STC EXR,@aa:16 STC CCR,@aa:32 STC EXR,@aa:32 STM.L(ERn-ERn+1),@-SP STM.L(ERn-ERn+2),@-SP STM.L(ERn-ERn+3),@-SP 3 R:W NEXT R:W 4th R:W 4th Internal operation, 1 state R:W 2nd R:W NEXT Internal operation, 1 state R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W NEXT R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W 3rd R:W 4th R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state R:W 2nd R:W:M NEXT Internal operation, 1 state Cannot be used in the H8S/2350 Series R:W NEXT R:W 3rd R:W NEXT STMAC MACH,ERd STMAC MACL,ERd SUB.B Rs,Rd SUB.W #xx:16,Rd SUB.W Rs,Rd SUB.L #xx:32,ERd SUB.L ERs,ERd SUBS #1/2/4,ERd SUBX #xx:8,Rd SUBX Rs,Rd TAS @ERd TRAPA #x:2 Normal W:B EA W:W stack (H) W:W stack (H) R:W NEXT R:B:M EA Internal operation, W:W stack (L) 1 state Internal operation, W:W stack (L) 1 state R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT W:W stack (EXR) R:W VEC W:W stack (EXR) R:W:M VEC Advanced R:W NEXT Internal operation, R:W*8 1 state R:W VEC+2 Internal operation, R:W*8 1 state XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd R:W 3rd R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT 777 778 2 R:W NEXT 3 4 5 6 7 8 9 W:W stack (EXR) W:W stack (EXR) R:W:M VEC R:W NEXT Internal operation, R:W*5 1 state R:W VEC+2 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state R:W VEC Internal operation, R:W*7 1 state R:W VEC+2 Internal operation, R:W*7 1 state Table A-6 Instruction Execution Cycles (cont) Instruction XOR.L ERs,ERd XORC #xx:8,CCR XORC #xx:8,EXR Normal Reset exception handling Advanced 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC R:W VEC R:W*6 Interrupt exception Normal handling Advanced R:W*6 Notes: 1. 2. 3. 4. 5. 6. 7. EAs is the contents of ER5. EAd is the contents of ER6. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4. If n = 0, these bus cycles are not executed. Repeated two times to save or restore two registers, three times for three registers, or four times for four registers. Start address after return. Start address of the program. Prefetch address, equal to two plus the PC value pushed onto the stack. In recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. Start address of the interrupt-handling routine. A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below. m= 31 for longword operands 15 for word operands 7 for byte operands Si Di Ri Dn -- The i-th bit of the source operand The i-th bit of the destination operand The i-th bit of the result The specified bit in the destination operand Not affected Modified according to the result of the instruction (see definition) 0 1 * Z' C' Always cleared to 0 Always set to 1 Undetermined (no guaranteed value) Z flag before instruction execution C flag before instruction execution 779 Table A-7 Instruction ADD Condition Code Modification H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm ADDS ADDX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm AND -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 Stores the corresponding bits of the result. No flags change when the operand is EXR. ANDC BAND Bcc BCLR BIAND BILD BIOR BIST BIXOR BLD BNOT BOR BSET BSR BST BTST BXOR CLRMAC -------- ---------- ---------- -------- -------- -------- ---------- -------- -------- ---------- -------- ---------- ---------- ---------- ---- ---- C = C' * Dn C = C' * Dn C = Dn C = C' + Dn C = C' * Dn + C' * Dn C = Dn C = C' + Dn Z = Dn C = C' * Dn + C' * Dn Cannot be used in the H8S/2350 Series -------- 780 Table A-7 Instruction CMP Condition Code Modification (cont) H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm DAA * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic carry DAS * * N = Rm Z = Rm * Rm-1 * ...... * R0 C: decimal arithmetic borrow DEC -- -- N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm N = Sm * Dm + Sm * Dm Z = Sm * Sm-1 * ...... * S0 N = Sm Z = Sm * Sm-1 * ...... * S0 DIVXS -- ---- DIVXU -- ---- EEPMOV EXTS ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 Z = Rm * Rm-1 * ...... * R0 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm EXTU INC --0 -- 0 -- -- JMP JSR LDC ---------- ---------- Stores the corresponding bits of the result. No flags change when the operand is EXR. LDM LDMAC MAC ---------- Cannnot be used in the H8S/2350 Series 781 Table A-7 Instruction MOV Condition Code Modification (cont) H -- N Z V 0 C -- Definition N = Rm Z = Rm * Rm-1 * ...... * R0 Can not be used in the H8S/2350 Series MOVFPE MOVTPE MULXS -- ---- N = R2m Z = R2m * R2m-1 * ...... * R0 MULXU NEG ---------- H = Dm-4 + Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Rm C = Dm + Rm NOP NOT ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 OR -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ORC Stores the corresponding bits of the result. No flags change when the operand is EXR. POP -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 PUSH -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 ROTL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) 782 Table A-7 Instruction ROTXL Condition Code Modification (cont) H -- N Z V 0 C Definition N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) ROTXR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE RTS SHAL ---------- -- Stores the corresponding bits of the result. N = Rm Z = Rm * Rm-1 * ...... * R0 V = Dm * Dm-1 + Dm * Dm-1 (1-bit shift) V = Dm * Dm-1 * Dm-2 * Dm * Dm-1 * Dm-2 (2-bit shift) C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHAR -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SHLL -- 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = Dm (1-bit shift) or C = Dm-1 (2-bit shift) SHLR --0 0 N = Rm Z = Rm * Rm-1 * ...... * R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) SLEEP STC STM STMAC ---------- ---------- ---------- Cannot be used in the H8S/2350 Series 783 Table A-7 Instruction SUB Condition Code Modification (cont) H N Z V C Definition H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Rm * Rm-1 * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm SUBS SUBX ---------- H = Sm-4 * Dm-4 + Dm-4 * Rm-4 + Sm-4 * Rm-4 N = Rm Z = Z' * Rm * ...... * R0 V = Sm * Dm * Rm + Sm * Dm * Rm C = Sm * Dm + Dm * Rm + Sm * Rm TAS -- 0 -- N = Dm Z = Dm * Dm-1 * ...... * D0 TRAPA XOR ---------- -- 0 -- N = Rm Z = Rm * Rm-1 * ...... * R0 XORC Stores the corresponding bits of the result. No flags change when the operand is EXR. 784 Appendix B Internal I/O Register B.1 Addresses Bit 6 SM0 Bit 5 DM1 Bit 4 DM0 Bit 3 MD1 Bit 2 MD0 Bit 1 DTS Bit 0 Sz Module Name DTC Data Bus Width 16/32* bit Address Register (low) Name Bit 7 H'F800 to H'FBFF MRA SAR SM1 MRB DAR CHNE DISEL -- -- -- -- -- -- CRA CRB H'FE80 H'FE81 H'FE82 H'FE83 H'FE84 H'FE85 H'FE86 H'FE87 H'FE88 H'FE89 H'FE8A H'FE8B H'FE8C H'FE8D H'FE8E H'FE8F TCR3 TMDR3 CCLR2 -- CCLR1 -- IOB2 IOD2 -- -- CCLR0 BFB IOB1 IOD1 -- -- CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU3 16 bit TIOR3H IOB3 TIOR3L TIER3 TSR3 TCNT3 IOD3 TTGE -- TGR3A TGR3B TGR3C TGR3D Note: * Located in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register information, and 16 bits otherwise. 785 Address Register (low) Name Bit 7 H'FE90 H'FE91 H'FE92 H'FE94 H'FE95 H'FE96 H'FE97 H'FE98 H'FE99 H'FE9A H'FE9B H'FEA0 H'FEA1 H'FEA2 H'FEA4 H'FEA5 H'FEA6 H'FEA7 H'FEA8 H'FEA9 H'FEAA H'FEAB H'FEB0 H'FEB1 H'FEB2 H'FEB4 H'FEB5 H'FEB9 H'FEBA H'FEBB H'FEBC H'FEBD H'FEBE H'FEBF P1DDR P2DDR P3DDR P5DDR P6DDR PADDR TGR5B TGR5A TCR5 TMDR5 TIOR5 TIER5 TSR5 TCNT5 -- -- IOB3 TTGE TCFD TGR4B TGR4A TCR4 TMDR4 TIOR4 TIER4 TSR4 TCNT4 -- -- IOB3 TTGE TCFD Bit 6 CCLR1 -- IOB2 -- -- Bit 5 CCLR0 -- IOB1 TCIEU TCFU Bit 4 Bit 3 Bit 2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Name TPU4 Data Bus Width 16 bit CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- -- CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU5 16 bit P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR -- -- -- -- P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR -- -- P53DDR P52DDR P51DDR P50DDR Port 8 bit P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR PBDDR* PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR PCDDR* PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR PDDDR* PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR PEDDR PFDDR PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR -- -- PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR PGDDR -- Note: * Only applies to the H8S/2351. 786 Address Register (low) Name Bit 7 H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE H'FED0 H'FED1 H'FED2 H'FED3 H'FED4 H'FED5 H'FED6 H'FED7 H'FED8 H'FED9 H'FEE0 H'FEE1 H'FEE2 H'FEE3 H'FEE4 H'FEE5 H'FEE6 H'FEE7 H'FEE8 H'FEE9 H'FEEA H'FEEB H'FEEC H'FEED H'FEEE H'FEEF ETCR0B IOAR0B MAR0BL MAR0BH -- ETCR0A IOAR0A MAR0AL IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK -- -- -- -- -- -- -- -- -- -- -- Bit 6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 IPR6 ABW6 AST6 W70 W30 ICIS0 Bit 5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 IPR5 ABW5 AST5 W61 W21 Bit 4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 IPR4 ABW4 AST4 W60 W20 Bit 3 -- -- -- -- -- -- -- -- -- -- -- ABW3 AST3 W51 W11 Bit 2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 IPR2 ABW2 AST2 W50 W10 Bit 1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 IPR1 ABW1 AST1 W41 W01 Bit 0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 IPR0 ABW0 AST0 W40 W00 Module Name Interrupt controller Data Bus Width 8 bit ABWCR ABW7 ASTCR WCRH WCRL BCRH BCRL MCR AST7 W71 W31 ICIS1 BRLE TPC Bus controller 8 bit BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMST0 WDBE RLW1 CKS1 WAITE RLW0 CKS0 BREQOE EAE -- CW2 LCASS MXC1 CMIE -- MXC0 CKS2 BE RCDM DRAMCR RFSHE RCW RTCNT RTCOR MAR0AH -- -- RMODE CMF -- -- -- -- -- -- DMAC 16 bit -- -- -- -- -- -- -- 787 Address Register (low) Name Bit 7 H'FEF0 H'FEF1 H'FEF2 H'FEF3 H'FEF4 H'FEF5 H'FEF6 H'FEF7 H'FEF8 H'FEF9 H'FEFA H'FEFB H'FEFC H'FEFD H'FEFE H'FEFF H'FF00 H'FF01 H'FF02 DMAWER-- DMATCR -- DMACR0A DTSZ Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 -- Bit 0 -- Module Name DMAC Data Bus Width 16 bit MAR1AH -- MAR1AL IOAR1A ETCR1A MAR1BH -- -- -- -- -- -- -- -- MAR1BL IOAR1B ETCR1B -- -- DTID SAID DTID DAID DTID SAID DTID DAID FAE0 FAE0 DTE1A -- TEE1 RPE SAIDE RPE DAIDE RPE SAIDE RPE DAIDE SAE1 -- DTE0B -- TEE0 DTDIR WE1B -- DTF3 WE1A -- DTF2 -- DTF2 DTF2 DTF2 -- DTF2 DTF2 DTA1A -- WE0B -- DTF1 -- DTF1 DTF1 DTF1 -- DTF1 DTF1 DTA0B DTA0 WE0A -- DTF0 -- DTF0 DTF0 DTF0 -- DTF0 DTF0 DTA0A -- Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode Short address mode Full address mode 8 bit 16 bit DTSZ H'FF03 DMACR0B DTSZ BLKDIR BLKE DTDIR -- DTDIR DTF3 DTF3 DTF3 -- H'FF04 DMACR1A DTSZ DTSZ H'FF05 DMACR1B DTSZ BLKDIR BLKE DTDIR -- SAE0 -- DTE0A DTF3 DTF3 DTA1B DTA1 -- H'FF06 DMABCRH FAE1 FAE1 H'FF07 DMABCRL DTE1B DTIE1B DTIE1A DTIE0B DTIE0A DTIE1B DTIE1A DTIE0B DTIE0A DTME1 DTE1 DTME0 DTE0 788 Address Register (low) Name Bit 7 H'FF2C H'FF2D H'FF2E H'FF2F ISCRH ISCRL IER ISR Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name Interrupt controller Data Bus Width 8 bit IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA IRQ7E IRQ7F DTCE7 IRQ6E IRQ6F DTCE6 IRQ5E IRQ5F DTCE5 IRQ4E IRQ4F DTCE4 IRQ3E IRQ3F DTCE3 IRQ2E IRQ2F DTCE2 IRQ1E IRQ1F DTCE1 IRQ0E IRQ0F DTCE0 DTC 8 bit H'FF30 to DTCER H'FF35 H'FF37 H'FF38 H'FF39 H'FF3A DTVECR SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 SBYCR SYSCR SCKCR SSBY -- STS2 -- STS1 INTM1 -- STS0 INTM0 -- OPE NMIEG -- -- -- SCK2 -- -- SCK1 -- RAME SCK0 Power-down mode MCU Clock pulse generator 8 bit 8 bit 8 bit PSTOP -- H'FF3B H'FF3C H'FF3D H'FF44 H'FF46 H'FF47 H'FF48 H'FF49 H'FF4A H'FF4B MDCR -- -- -- -- -- MDS2 MDS1 MDS0 MSTP8 MCU Power-down mode Reserved 8 bit 8 bit MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTPCRL MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0 -- -- -- -- -- -- -- Reserved -- PCR PMR NDERH NDERL -- 8 bit G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 PPG G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 NDER7 NDER6 NDER5 NDER4 NDER3 NDER2 NDER1 NDER0 POD14 POD6 NDR14 NDR6 -- -- POD13 POD5 NDR13 NDR5 -- -- POD12 POD4 NDR12 NDR4 -- -- POD11 POD3 NDR11 NDR3 NDR11 NDR3 POD10 POD2 NDR10 NDR2 NDR10 NDR2 POD9 POD1 NDR9 NDR1 NDR9 NDR1 POD8 POD0 NDR8 NDR0 NDR8 NDR0 PODRH POD15 PODRL POD7 NDR15 NDR7 -- -- H'FF4C* NDRH H'FF4D* NDRL H'FF4E* NDRH H'FF4F* NDRL Note: * If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C. Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the same according to the PCR setting, the NDRL address will be H'FF4D, and if different, the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D. 789 Address Register (low) Name Bit 7 H'FF50 H'FF51 H'FF52 H'FF53 H'FF54 H'FF55 H'FF59 H'FF5A H'FF5B H'FF5C H'FF5D H'FF5E H'FF5F H'FF60 H'FF61 H'FF62 H'FF64 H'FF65 H'FF69 H'FF6A H'FF6B H'FF6C H'FF6D H'FF6E H'FF6F H'FF70 H'FF71 H'FF72 H'FF73 H'FF74 H'FF76 H'FF77 PORT1 PORT2 PORT3 PORT4 PORT5 PORT6 PORTA P17 P27 -- P47 -- P67 PA7 Bit 6 P16 P26 -- P46 -- P66 PA6 PB6 PC6 PD6 PE6 PF6 -- P16DR P26DR -- -- P66DR Bit 5 P15 P25 P35 P45 -- P65 PA5 PB5 PC5 PD5 PE5 PF5 -- P15DR P25DR P35DR -- P65DR Bit 4 P14 P24 P34 P44 -- P64 PA4 PB4 PC4 PD4 PE4 PF4 PG4 P14DR P24DR P34DR -- P64DR Bit 3 P13 P23 P33 P43 P53 P63 PA3 PB3 PC3 PD3 PE3 PF3 PG3 P13DR P23DR P33DR P53DR P63DR Bit 2 P12 P22 P32 P42 P52 P62 PA2 PB2 PC2 PD2 PE2 PF2 PG2 P12DR P22DR P32DR P52DR P62DR Bit 1 P11 P21 P31 P41 P51 P61 PA1 PB1 PC1 PD1 PE1 PF1 PG1 P11DR P21DR P31DR P51DR P61DR Bit 0 P10 P20 P30 P40 P50 P60 PA0 PB0 PC0 PD0 PE0 PF0 PG0 P10DR P20DR P30DR P50DR P60DR Module Name Port Data Bus Width 8 bit PORTB* PB7 PORTC* PC7 PORTD* PD7 PORTE PORTF PORTG P1DR P2DR P3DR P5DR P6DR PADR PBDR* PCDR* PDDR* PEDR PFDR PGDR PAPCR PBPCR PCPCR PDPCR PEPCR P3ODR PAODR PE7 PF7 -- P17DR P27DR -- -- P67DR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR PF7DR -- PF6DR -- PF5DR -- PF4DR PF3DR PF2DR PF1DR PF0DR PG4DR PG3DR PG2DR PG1DR PG0DR PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR -- -- P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Note: * Only applies to the H8S/2351. 790 Address Register (low) Name Bit 7 H'FF78 SMR0 C/A/ GM* 1 H'FF79 H'FF7A H'FF7B H'FF7C BRR0 SCR0 TDR0 SSR0 TDRE TIE Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module Name SCI0, Smart card interface 0 Data Bus Width 8 bit RIE TE RE MPIE TEIE CKE1 CKE0 RDRF ORER FER/ ERS*2 PER TEND MPB MPBT H'FF7D H'FF7E H'FF80 RDR0 SCMR0 SMR1 -- C/A/ GM* 1 -- CHR -- PE -- O/E SDIR STOP SINV MP -- CKS1 SMIF CKS0 SCI1, Smart card interface 1 TIE RIE TE RE MPIE TEIE CKE1 CKE0 8 bit H'FF81 H'FF82 H'FF83 H'FF84 BRR1 SCR1 TDR1 SSR1 TDRE RDRF ORER FER/ ERS*2 PER TEND MPB MPBT H'FF85 H'FF86 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 H'FF98 H'FF99 H'FFA4 H'FFA5 H'FFA6 RDR1 SCMR1 -- -- AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE -- AD7 -- AD7 -- AD7 -- AD7 -- ADST -- AD6 -- AD6 -- AD6 -- AD6 -- SCAN -- SDIR AD5 -- AD5 -- AD5 -- AD5 -- CKS -- SINV AD4 -- AD4 -- AD4 -- AD4 -- -- -- -- AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- SMIF AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- D/A converter 8 bit A/D converter 8 bit ADDRAH AD9 ADDRAL AD1 ADDRBH AD9 ADDRBL AD1 ADDRCH AD9 ADDRCL AD1 ADDRDH AD9 ADDRDL AD1 ADCSR ADCR DADR0 DADR1 DACR ADF TRGS1 TRGS0 -- DAOE1 DAOE0 DAE -- -- -- -- -- Notes: 1. Functions as C/A for SCI use, and as GM for smart card interface use. 2. Functions as FER for SCI use, and as ERS for smart card interface use. 791 Address Register (low) Name Bit 7 H'FFBC (read) H'FFBD (read) H'FFBF (read) H'FFC0 H'FFC1 H'FFD0 H'FFD1 H'FFD2 H'FFD3 H'FFD4 H'FFD5 H'FFD6 H'FFD7 H'FFD8 H'FFD9 H'FFDA H'FFDB H'FFDC H'FFDD H'FFDE H'FFDF H'FFE0 H'FFE1 H'FFE2 H'FFE4 H'FFE5 H'FFE6 H'FFE7 H'FFE8 H'FFE9 H'FFEA H'FFEB TGR1B TGR1A TCR1 TMDR1 TIOR1 TIER1 TSR1 TCNT1 -- -- IOB3 TTGE TCFD TGR0D TGR0C TGR0B TGR0A TSTR TSYR TCR0 TMDR0 -- -- CCLR2 -- RSTCSR WOVF TCNT TCSR OVF Bit 6 WT/IT Bit 5 TME Bit 4 -- Bit 3 -- Bit 2 CKS2 Bit 1 CKS1 Bit 0 CKS0 Module Name WDT Data Bus Width 16 bit RSTE RSTS -- -- -- -- -- -- -- CCLR1 -- IOB2 IOD2 -- -- CST5 CST4 CST3 CST2 CST1 CST0 TPU 16 bit SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 CCLR0 BFB IOB1 IOD1 -- -- CKEG1 CKEG0 TPSC2 BFA IOB0 IOD0 TCIEV TCFV MD3 IOA3 IOC3 TGIED TGFD MD2 IOA2 IOC2 TGIEC TGFC TPSC1 MD1 IOA1 IOC1 TGIEB TGFB TPSC0 MD0 IOA0 IOC0 TGIEA TGFA TPU0 16 bit TIOR0H IOB3 TIOR0L TIER0 TSR0 TCNT0 IOD3 TTGE -- CCLR1 -- IOB2 -- -- CCLR0 -- IOB1 TCIEU TCFU CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- -- TPSC1 MD1 IOA1 TGIEB TGFB TPSC0 MD0 IOA0 TGIEA TGFA TPU1 16 bit 792 Address Register (low) Name Bit 7 H'FFF0 H'FFF1 H'FFF2 H'FFF4 H'FFF5 H'FFF6 H'FFF7 H'FFF8 H'FFF9 H'FFFA H'FFFB TGR2B TGR2A TCR2 TMDR2 TIOR2 TIER2 TSR2 TCNT2 -- -- IOB3 TTGE TCFD Bit 6 CCLR1 -- IOB2 -- -- Bit 5 CCLR0 -- IOB1 TCIEU TCFU Bit 4 Bit 3 Bit 2 Bit 1 TPSC1 MD1 IOA1 TGIEB TGFB Bit 0 TPSC0 MD0 IOA0 TGIEA TGFA Module Name TPU2 Data Bus Width 16 bit CKEG1 CKEG0 TPSC2 -- IOB0 TCIEV TCFV MD3 IOA3 -- -- MD2 IOA2 -- -- 793 B.2 Functions H'F800--H'FBFF 5 DM1 -- 4 DM0 -- 3 MD1 -- 2 MD0 -- 1 DTS -- 0 Sz -- MRA--DTC Mode Register A Bit : 7 SM1 Initial value : Read/Write : -- 6 SM0 -- DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined DTC Data Transfer Size 0 1 Byte-size transfer Word-size transfer DTC Transfer Mode Select 0 1 DTC Mode 0 0 1 1 0 1 Destination Address Mode 0 1 -- 0 1 Source Address Mode 0 1 -- 0 1 SAR is fixed SAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) SAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) DAR is fixed DAR is incremented after a transfer (by +1 when Sz = 0; by +2 when Sz = 1) DAR is decremented after a transfer (by -1 when Sz = 0; by -2 when Sz = 1) Normal mode Repeat mode Block transfer mode -- Destination side is repeat area or block area Source side is repeat area or block area 794 MRB--DTC Mode Register B Bit : 7 CHNE Initial value : Read/Write : -- 6 DISEL -- 5 -- -- 4 -- -- H'F800--H'FBFF 3 -- -- 2 -- -- 1 -- -- 0 -- -- DTC Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Reserved Only 0 should be written to these bits DTC Interrupt Select 0 1 After a data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 After a data transfer ends, the CPU interrupt is enabled DTC Chain Transfer Enable 0 1 End of DTC data transfer DTC chain transfer SAR--DTC Source Address Register Bit : 23 22 21 20 19 H'F800--H'FBFF --------4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies transfer data source address DAR--DTC Destination Address Register Bit : 23 22 21 20 19 H'F800--H'FBFF --------4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Undefined fined fined fined fined Unde- Unde- Unde- Unde- Undefined fined fined fined fined -- -- -- -- -- -- -- -- -- -- Specifies transfer data destination address 795 CRA--DTC Transfer Count Register A Bit : 15 14 13 12 11 10 9 8 H'F800--H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CRAH CRAL Specifies the number of DTC data transfers CRB--DTC Transfer Count Register B Bit : 15 14 13 12 11 10 9 8 H'F800--H'FBFF 7 6 5 4 3 2 1 DTC 0 Initial value : Read/Write : Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Specifies the number of DTC block data transfers 796 TCR3--Timer Control Register 3 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FE80 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU3 CKEG1 CKEG0 R/W Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture *2 TCNT cleared by TGRD compare match/input capture *2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation *1 -- Count at rising edge Count at falling edge Count at both edges Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input Internal clock: counts on o/1024 Internal clock: counts on o/256 Internal clock: counts on o/4096 1 0 0 1 1 0 1 Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 797 TMDR3--Timer Mode Register 3 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W H'FE81 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU3 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- * : Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. Buffer Operation A 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation Buffer Operation B 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation 798 TIOR3H--Timer I/O Control Register 3H Bit : 7 IOB3 0 Read/Write : R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FE82 1 IOA1 0 R/W 0 IOA0 0 R/W TPU3 Initial value : TGR3A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3A is input capture register Capture input source is TIOCA3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock * : Don't care TGR3B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3B is input capture register Capture input source is TIOCB3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input source is channel 4/count clock Input capture at TCNT4 count-up/ count-down * : Don't care Note: 1. If bits TPSC2 to TPSC0 in TCR4 are set to B'000, and o/1 is used as the TCNT4 count clock, this setting will be invalid and input capture will not occur. TGR3B Output disabled is output compare Initial output is register 0 output TGR3A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 799 TIOR3L--Timer I/O Control Register 3L Bit : 7 IOD3 Initial value : Read/Write : 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 H'FE83 1 IOC1 0 R/W 0 IOC0 0 R/W TPU3 IOC2 0 R/W TRG3C I/O Control 0 0 0 0 TGR3C Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR3C is input 1 capture * register * Capture input source is TIOCC3 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT4 count-up/ source is channel count-down 4/count clock * : Don't care Note: When the BFA bit in TMDR3 is set to 1 and TGR3C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR3D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR3D is input capture register Capture input source is TIOCD3 pin Capture input source is channel 4/count clock Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Input capture at TCNT4 count-up/ count-down*1 * : Don't care Notes: When the BFB bit in TMDR3 is set to 1 and TGR3D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 1 When bits TPSC2 to TPSC0 in TCR4 are set to B'000 and o/1 is used as the TCNT4 count clock, this setting is invalid and input capture is not generated. Note: When GRC or GRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. TGR3D Output disabled is output compare Initial output is 0 0 output at compare match register output 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 * 800 TIER3--Timer Interrupt Enable Register 3 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 TGIED 0 R/W H'FE84 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU3 TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled 801 TSR3--Timer Status Register 3 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* H'FE85 2 TGFC 0 R/(W)* 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU3 Input Capture/Output Compare Flag A 0 [Clearing condition] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 [Setting condition] * When TCNT=TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing condition] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting condition] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing condition] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting condition] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing condition] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting condition] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting condition] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 802 TCNT3--Timer Counter 3 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FE86 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU3 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A--Timer General Register 3A TGR3B--Timer General Register 3B TGR3C--Timer General Register 3C TGR3D--Timer General Register 3D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FE88 H'FE8A H'FE8C H'FE8E 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU3 TPU3 TPU3 TPU3 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 803 TCR4--Timer Control Register 4 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FE90 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU4 CKEG1 CKEG0 Timer Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 Counts on TCNT5 overflow/underflow Note: This setting is ignored when channel 4 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Counter Clear 0 0 1 1 0 1 Note: This setting is ignored when channel 4 is in phase counting mode. TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. 804 TMDR4--Timer Mode Register 4 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- 3 H'FE91 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU4 MD3 0 R/W Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- * : Don't care Notes: MD3 is a reserved bit. In a write, it should always be written with 0. 805 TIOR4--Timer I/O Control Register 4 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 H'FE92 1 IOA1 0 R/W 0 IOA0 0 R/W TPU4 IOA2 0 R/W TGR4A I/O Control 0 0 0 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4A is input capture register Capture input source is TIOCA4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3A TGR3A compare match/input compare match/ capture input capture * : Don't care TGR4B I/O Control 0 0 0 0 TGR4B Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR4B is input capture register Capture input source is TIOCB4 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR3C TGR3C compare match/input compare match/ capture input capture * : Don't care 0 output at compare match 1 output at compare match Toggle output at compare match 1 0 output at compare match 1 output at compare match Toggle output at compare match 1 806 TIER4--Timer Interrupt Enable Register 4 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- H'FE94 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU4 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled 807 TSR4--Timer Status Register 4 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- H'FE95 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU4 Input Capture/Output Compare Flag A 0 [Clearing condition] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing condition] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 808 TCNT4--Timer Counter 4 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 H'FE96 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU4 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR4A--Timer General Register 4A TGR4B--Timer General Register 4B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FE98 H'FE9A 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU4 TPU4 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 809 TCR5--Timer Control Register 5 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FEA0 2 TPSC2 0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 TPU5 1 TPSC1 0 R/W 0 TPSC0 0 R/W CKEG1 CKEG0 External clock: counts on TCLKA pin input External clock: counts on TCLKC pin input Internal clock: counts on o/256 External clock: counts on TCLKD pin input Note: This setting is ignored when channel 5 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 5 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. 810 TMDR5--Timer Mode Register 5 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FEA1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU5 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- * : Don't care Notes: MD3 is a reserved bit. In a write, it should always be written with 0. 811 TIOR5--Timer I/O Control Register 5 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 H'FEA2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU5 IOA2 0 R/W TGR5A I/O Control 0 0 0 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR5A is input 1 capture * register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCA5 Input capture at falling edge pin Input capture at both edges * : Don't care TGR5B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR5B is input capture register Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Capture input Input capture at rising edge source is TIOCB5 Input capture at falling edge pin Input capture at both edges * : Don't care TGR5B Output disabled is output compare Initial output is 0 register output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 0 output at compare match 1 output at compare match Toggle output at compare match 812 TIER5--Timer Interrupt Enable Register 5 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- H'FEA4 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU5 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled 813 TSR5--Timer Status Register 5 Bit : 7 TCFD Initial value : Read/Write : 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- H'FEA5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU5 Input Capture/Output Compare Flag A 0 [Clearing condition] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing condition] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 814 TCNT5--Timer Counter 5 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FEA6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU5 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR5A--Timer General Register 5A TGR5B--Timer General Register 5B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FEA8 H'FEAA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU5 TPU5 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W P1DDR--Port 1 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB0 3 0 W 2 0 W 1 0 W 0 0 W Port 1 P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Initial value : Read/Write : Specify input or output for individual port 1 pins 815 P2DDR--Port 2 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB1 3 0 W 2 0 W 1 0 W 0 0 Port 2 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : Read/Write : W Specify input or output for individual port 2 pins P3DDR--Port 3 Data Direction Register Bit : 7 -- Initial value : Read/Write : -- 6 -- -- 5 0 W 4 0 W H'FEB2 3 0 W 2 0 W 1 0 W 0 0 Port 3 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR W Undefined Undefined Specify input or output for individual port 3 pins P5DDR--Port 5 Data Direction Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FEB4 3 0 W 2 0 W 1 0 W 0 0 W Port 5 P53DDR P52DDR P51DDR P50DDR Initial value : Undefined Undefined Undefined Undefined Specify input or output for individual port 5 pins 816 P6DDR--Port 6 Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB5 3 0 W 2 0 W 1 0 W Port 6 0 0 W P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : Read/Write : Specify input or output for individual port 6 pins PADDR--Port A Data Direction Register Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W H'FEB9 3 0 W 2 0 W 1 0 W Port A 0 0 W PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Specify input or output for individual port A pins PBDDR--Port B Data Direction Register H'FEBA Port B [H8S/2351 Only] 2 0 W 1 0 W 0 0 W Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR Specify input or output for individual port B pins 817 PCDDR--Port C Data Direction Register H'FEBB Port C [H8S/2351 Only] 2 0 W 1 0 W 0 0 W Bit Initial value Read/Write : : : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Specify input or output for individual port C pins PDDDR--Port D Data Direction Register H'FEBC Port D [H8S/2351 Only] 2 0 W 1 0 W 0 0 W Bit : 7 0 W 6 0 W 5 0 W 4 0 W 3 0 W PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : Read/Write : Specify input or output for individual port D pins PEDDR--Port E Data Direction Register Bit : 7 0 W 6 0 W 5 0 W 4 0 W H'FEBD 3 0 W 2 0 W 1 0 W Port E 0 0 W PE7DDR PE6DDR PE5DDR PE4DDR PE3DDR PE2DDR PE1DDR PE0DDR Initial value : Read/Write : Specify input or output for individual port E pins 818 PFDDR--Port F Data Direction Register Bit : 7 6 5 4 H'FEBE 3 2 1 0 Port F PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 1, 2, 4 to 6 Initial value Read/Write Modes 3, 7 Initial value Read/Write : : 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W : : 1 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Specify input or output for individual port F pins PGDDR--Port G Data Direction Register Bit Modes 1, 4, 5 Initial value Read/Write Initial value Read/Write : Undefined Undefined Undefined : -- -- -- 1 W 0 W : 7 -- 6 -- 5 -- 4 H'FEBF 3 2 1 Port G 0 PG4DDR PG3DDR PG2DDR PG1DDR PG0DDR 0 W 0 W 0 W 0 W 0 W 0 W 0 W 0 W Modes 2, 3, 6, 7 : Undefined Undefined Undefined : -- -- -- Specify input or output for individual port G pins 819 IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Bit -- -- -- -- -- -- -- -- -- -- -- Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K : 7 -- 0 -- 6 IPR6 1 R/W 5 IPR5 1 R/W 4 IPR4 1 R/W H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FECC H'FECD H'FECE 3 -- 0 -- 2 IPR2 1 R/W Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller Interrupt Controller 1 IPR1 1 R/W 0 IPR0 1 R/W Initial value : Read/Write : Set priority (levels 7 to 0) for interrupt sources Correspondence between Interrupt Sources and IPR Settings Bits Register 6 to 4 IPRA IPRB IRQ0 IRQ2 IRQ3 IPRC IRQ6 IRQ7 IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK WDT --* TPU channel 0 TPU channel 2 TPU channel 4 --* DMAC SCI channel 1 Refresh timer A/D converter TPU channel 1 TPU channel 3 TPU channel 5 --* SCI channel 0 --* IRQ1 IRQ4 IRQ5 DTC 2 to 0 Note: * Reserved bits. These bits cannot be modified and are always read as 1. 820 ABWCR--Bus Width Control Register Bit : 7 ABW7 Modes 1, 2, 3, 5, 7 Initial value : R/W Mode 4 Initial value : Read/Write : 0 R/W 0 R/W 0 R/W 0 R/W : 1 R/W 1 R/W 1 R/W 1 R/W 6 ABW6 5 ABW5 4 H'FED0 3 ABW3 1 R/W 0 R/W 2 ABW2 1 R/W 0 R/W 1 Bus Controller 0 ABW0 1 R/W 0 R/W ABW4 ABW1 1 R/W 0 R/W Area 7 to 0 Bus Width Control 0 1 Area n is designated for 16-bit access Area n is designated for 8-bit access (n = 7 to 0) ASTCR--Access State Control Register Bit : 7 AST7 Initial value : Read/Write : 1 R/W 6 AST6 1 R/W 5 AST5 1 R/W 4 AST4 1 R/W H'FED1 3 AST3 1 R/W 2 AST2 1 R/W 1 Bus Controller 0 AST0 1 R/W AST1 1 R/W Area 7 to 0 Access State Control 0 Area n is designated for 2-state access Wait state insertion in area n external space is disabled 1 Area n is designated for 3-state access Wait state insertion in area n external space is enabled (n = 7 to 0) 821 WCRH--Wait Control Register H Bit : 7 W71 Initial value : Read/Write : 1 R/W 6 W70 1 R/W 5 W61 1 R/W 4 W60 1 R/W 3 H'FED2 2 W50 1 R/W 1 W41 1 R/W 0 W40 1 R/W Bus Controller W51 1 R/W Area 4 Wait Control 0 0 1 1 0 1 Area 5 Wait Control 0 0 1 1 0 1 Area 6 Wait Control 0 0 1 1 0 1 Area 7 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 822 WCRL--Wait Control Register L Bit : 7 W31 Initial value : Read/Write : 1 R/W 6 W30 1 R/W 5 W21 1 R/W 4 W20 1 R/W 3 H'FED3 2 W10 1 R/W 1 W01 1 R/W 0 W00 1 R/W Bus Controller W11 1 R/W Area 0 Wait Control 0 0 1 1 0 1 Area 1 Wait Control 0 0 1 1 0 1 Area 2 Wait Control 0 0 1 1 0 1 Area 3 Wait Control 0 0 1 1 0 1 Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted Program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 823 BCRH--Bus Control Register H Bit : 7 ICIS1 Initial value : Read/Write : 1 R/W 6 ICIS0 1 R/W 5 0 R/W 4 1 R/W H'FED4 3 0 R/W 2 0 R/W 1 0 R/W Bus Controller 0 0 R/W BRSTRM BRSTS1 BRSTS0 RMTS2 RMTS1 RMTS0 RAM Type Select RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 0 1 1 0 1 1 -- -- Normal space Normal space Normal space DRAM space DRAM space DRAM space -- Note: When areas selected in DRAM space are all 8-bit space, the PF2 pin can be used as an I/O port, BREQO, or WAIT. Burst Cycle Select 0 0 1 Max. 4 words in burst access Max. 8 words in burst access Burst Cycle Select 1 0 1 Burst cycle comprises 1 state Burst cycle comprises 2 states Area 0 Burst ROM Enable 0 1 Area 0 is basic bus interface Area 0 is burst ROM interface Idle Cycle Insert 0 0 1 Idle cycle not inserted in case of successive external read and external write cycles Idle cycle inserted in case of successive external read and external write cycles Idle Cycle Insert 1 0 1 Idle cycle not inserted in case of successive external read cycles in different areas Idle cycle inserted in case of successive external read cycles in different areas 824 BCRL--Bus Control Register L Bit : 7 BRLE Initial value : Read/Write : 0 R/W 6 BREQOE 0 R/W 5 -- 1 R/W 4 LCASS 1 R/W 3 DDS 1 R/W H'FED5 2 -- 1 R/W 1 WDBE 0 R/W 0 WAITE 0 R/W Bus Controller WAIT Pin Enable 0 Wait input by WAIT pin disabled Wait input by WAIT pin enabled 1 Write Data Buffer Enable 0 Write data buffer function not used Write data buffer function used 1 Reserved Only 1 should be written to this bit DACK Timing Select 0 When DMAC single address transfer is performed in DRAM/PSRAM space, full access is always executed DACK signal goes low from Tr or T1 cycle Burst access is possible when DMAC single address transfer is performed in DRAM/PSRAM space DACK signal goes low from Tc1 or T2 cycle 1 LCAS Select Write 0 to this bit when using the DRAM interface Reserved Only 0 should be written to this bit BREQO Pin Enable 0 1 BREQO output disabled BREQO output enabled Bus Release Enable 0 1 External bus release is disabled External bus release is enabled 825 MCR--Memory Control Register Bit : 7 TPC Initial value : Read/Write : 0 R/W 6 BE 0 R/W 5 RCDM 0 R/W 4 CW2 0 R/W 3 MXC1 0 R/W H'FED6 2 MXC0 0 R/W 1 RLW1 0 R/W 0 RLW0 0 R/W Bus Controller Refresh Cycle Wait Control 0 0 1 1 0 1 Multiplex Shift Count 0 0 1 1 0 1 2-CAS Method Select 0 1 16-bit DRAM space selected 8-bit DRAM space selected 8-bit shift 9-bit shift 10-bit shift -- No wait state inserted 1 wait state inserted 2 wait states inserted 3 wait states inserted RAS/CS Down Mode 0 1 DRAM interface: RAS up mode selected DRAM interface: RAS down mode selected Burst Access Enable 0 1 TP Cycle Control 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted Burst disabled (always full access) For DRAM space access, access in fast page mode 826 DRAMCR--DRAM Control Register Bit : 7 RFSHE Initial value : Read/Write : 0 R/W 6 RCW 0 R/W 5 RMODE 0 R/W 4 CMF 0 R/W H'FED7 3 CMIE 0 R/W 2 CKS2 0 R/W 1 CKS1 0 R/W Bus Controller 0 CKS0 0 R/W Refresh Counter Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Count operation disabled Count uses o/2 Count uses o/8 Count uses o/32 Count uses o/128 Count uses o/512 Count uses o/2048 Count uses o/4096 Compare Match Interrupt Enable 0 1 Interrupt request (CMI) by CMF flag disabled Interrupt request (CMI) by CMF flag enabled Compare Match Flag 0 [Clearing condition] Cleared by reading the CMF flag when CMF = 1, then writing 0 to the CMF flag [Setting condition] Set when RTCNT = RTCOR 1 Refresh Mode 0 1 RAS-CAS Wait 0 1 Wait state insertion in CAS-before-RAS refreshing disabled RAS falls in TRr cycle One wait state inserted in CAS-before-RAS refreshing RAS falls in TRc1 cycle DRAM interface: CAS-before-RAS refreshing used Self-refreshing used Refresh Control 0 1 Refresh control is not performed Refresh control is performed 827 RTCNT--Refresh Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FED8 3 0 R/W 2 0 R/W Bus Controller 1 0 R/W 0 0 R/W Initial value : Read/Write : Internal clock count value RTCOR--Refresh Time Constant Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FED9 3 1 R/W 2 1 R/W Bus Controller 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the period for compare match operations with RTCNT MAR0AH--Memory Address Register 0AH MAR0AL--Memory Address Register 0AL Bit MAR0AH : : 31 -- 0 -- 15 * 30 -- 0 -- 14 * 29 -- 0 -- 13 * 28 -- 0 -- 12 * 27 -- 0 -- 11 * 26 -- 0 -- 10 * 25 -- 0 -- 9 * H'FEE0 H'FEE2 24 -- 0 * * * * * * * 23 22 21 20 19 18 DMAC DMAC 17 16 * Initial value : Read/Write : Bit MAR0AL : : -- R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address 828 IOAR0A--I/O Address Register 0A Bit IOAR0A : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEE4 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR0A--Transfer Count Register 0A Bit ETCR0A : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEE6 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer number storage register Block transfer mode Block size storage register Transfer counter Block size counter * : Undefined Transfer counter 829 MAR0BH--Memory Address Register 0BH MAR0BL--Memory Address Register 0BL Bit MAR0BH : : 31 -- 0 -- 15 * 30 -- 0 -- 14 * 29 -- 0 -- 13 * 28 -- 0 -- 12 * 27 -- 0 -- 11 * 26 -- 0 -- 10 * 25 -- 0 -- 9 * H'FEE8 H'FEEA 24 -- 0 * * * * * * * 23 22 21 20 19 18 DMAC DMAC 17 16 * Initial value : Read/Write : Bit MAR0BL : : -- R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address IOAR0B--I/O Address Register 0B Bit IOAR0B : : 15 14 13 12 11 10 9 8 H'FEEC 7 6 5 4 3 2 1 DMAC 0 Initial value : * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used 830 ETCR0B--Transfer Count Register 0B Bit ETCR0B : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEEE 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode and idle mode Repeat mode Transfer number storage register Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. Transfer counter Transfer counter MAR1AH--Memory Address Register 1AH MAR1AL--Memory Address Register 1AL Bit MAR1AH : : 31 -- 0 -- 15 * 30 -- 0 -- 14 * 29 -- 0 -- 13 * 28 -- 0 -- 12 * 27 -- 0 -- 11 * 26 -- 0 -- 10 * 25 -- 0 -- 9 * H'FEF0 H'FEF2 24 -- 0 * * * * * * * 23 22 21 20 19 18 DMAC DMAC 17 16 * Initial value : Read/Write : Bit MAR1AL : : -- R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer source address 831 IOAR1A--I/O Address Register 1A Bit IOAR1A : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEF4 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1A--Transfer Count Register 1A Bit ETCR1A : : * * * * * * * 15 14 13 12 11 10 9 H'FEF6 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer number storage register Block transfer mode Block size storage register Block size counter * : Undefined Transfer counter Transfer counter 832 MAR1BH -- Memory Address Register 1BH MAR1BL -- Memory Address Register 1BL Bit MAR1BH : : 31 -- 0 -- 15 * 30 -- 0 -- 14 * 29 -- 0 -- 13 * 28 -- 0 -- 12 * 27 -- 0 -- 11 * 26 -- 0 -- 10 * 25 -- 0 -- 9 * H'FEF8 H'FEFA 24 -- 0 * * * * * * * 23 22 21 20 19 18 DMAC DMAC 17 16 * Initial value : Read/Write : Bit MAR1BL : : -- R/W R/W R/W R/W R/W R/W R/W R/W 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Specifies transfer destination address IOAR1B--I/O Address Register 1B Bit IOAR1B : : * * * * * * * * 15 14 13 12 11 10 9 8 H'FEFC 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1B--Transfer Count Register 1B Bit ETCR1B : : * * * * * * * 15 14 13 12 11 10 9 H'FEFE 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1 * DMAC 0 * Initial value : Read/Write : Sequential mode and idle mode Repeat mode R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Transfer counter Transfer number storage register Transfer counter Block transfer mode Block transfer counter * : Undefined Note: Not used in normal mode. 833 DMAWER--DMA Write Enable Register Bit : 7 -- 0 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FF00 3 WE1B 0 R/W 2 WE1A 0 R/W 1 WE0B 0 R/W 0 DMAC DMAWER : Initial value : Read/Write : WE0A 0 R/W Write Enable 0A 0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled 1 Write Enable 0B 0 Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are disabled Writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR are enabled 1 Write Enable 1A 0 1 Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are disabled Writes to all bits in DMACR1A, and bits 10, 6, and 2 in DMABCR are enabled Write Enable 1B 0 1 Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are disabled Writes to all bits in DMACR1B, bits 11, 7, and 3 in DMABCR, and bit 5 in DMATCR are enabled 834 DMATCR--DMA Terminal Control Register Bit DMATCR : : 7 -- 0 -- 6 -- 0 -- 5 TEE1 0 R/W 4 TEE0 0 R/W H'FF01 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- DMAC 0 -- 0 -- Initial value : Read/Write : Transfer End Enable 0 0 1 TEND0 pin output disabled TEND0 pin output enabled Transfer End Enable 1 0 1 TEND1 pin output disabled TEND1 pin output enabled 835 DMACR0A--DMA Control Register 0A DMACR0B--DMA Control Register 0B DMACR1A--DMA Control Register 1A DMACR1B--DMA Control Register 1B Full address mode Bit DMACRA : : 15 DTSZ 0 R/W 14 SAID 0 R/W 13 SAIDE 0 R/W 12 BLKDIR 0 R/W H'FF02 H'FF03 H'FF04 H'FF05 DMAC DMAC DMAC DMAC 11 BLKE 0 R/W 10 -- 0 R/W 9 -- 0 R/W 8 -- 0 R/W Initial value : Read/Write : Block Direction/Block Enable 0 0 1 1 0 1 Transfer in normal mode Transfer in block transfer mode, destination side is block area Transfer in normal mode Transfer in block transfer mode, source side is block area Source Address Increment/Decrement 0 0 1 1 0 1 Data Transfer Size 0 1 Byte-size transfer Word-size transfer MARA is fixed MARA is incremented after a data transfer MARA is fixed MARA is decremented after a data transfer 836 Full address mode (cont) Bit DMACRB : : 7 -- 0 R/W 6 DAID 0 R/W 5 DAIDE 0 R/W 4 -- 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Read/Write : Data Transfer Factor DTF DTF DTF DTF 3 210 000 0 -- 1 1 0 Block Transfer Mode -- -- Normal Mode Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt Activated by DREQ pin low-level input 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 -- -- Auto-request (cycle steal) Auto-request (burst) -- -- -- -- -- -- -- -- -- -- Destination Address Increment/Decrement 0 0 1 1 0 1 MARB is fixed MARB is incremented after a data transfer MARB is fixed MARB is decremented after a data transfer 837 Short address mode Bit DMACR : : 7 DTSZ 0 R/W 6 DTID 0 R/W 5 RPE 0 R/W 4 DTDIR 0 R/W 3 DTF3 0 R/W 2 DTF2 0 R/W 1 DTF1 0 R/W 0 DTF0 0 R/W Initial value : Read/Write : Data Transfer Factor Channel A Data Transfer Direction 0 Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe Dual address mode: Transfer with IOAR as source address and MAR as destination address Single address mode: Transfer with DACK pin as read strobe and MAR as destination address 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 1 0 1 -- Activated by A/D converter conversion end interrupt -- -- Activated by DREQ pin falling edge input Activated by DREQ pin low-level input Channel B 1 Activated by SCI channel 0 transmission complete interrupt Activated by SCI channel 0 reception complete interrupt Activated by SCI channel 1 transmission complete interrupt Activated by SCI channel 1 reception complete interrupt Activated by TPU channel 0 compare match/input capture A interrupt Activated by TPU channel 1 compare match/input capture A interrupt Activated by TPU channel 2 compare match/input capture A interrupt Activated by TPU channel 3 compare match/input capture A interrupt Activated by TPU channel 4 compare match/input capture A interrupt Activated by TPU channel 5 compare match/input capture A interrupt -- -- Repeat Enable 0 1 Transfer in sequential mode Transfer in repeat mode or idle mode Data Transfer Increment/Decrement 0 1 MAR is incremented after a data transfer MAR is decremented after a data transfer Data Transfer Size 0 1 Byte-size transfer Word-size transfer 838 DMABCRH -- DMA Band Control Register DMABCRL -- DMA Band Control Register Full address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 -- 0 R/W 12 -- 0 R/W 11 DTA1 0 R/W H'FF06 H'FF07 DMAC DMAC 10 -- 0 R/W 9 DTA0 0 R/W 8 -- 0 R/W DMABCRH : Initial value : Read/Write : Channel 0 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1 Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0 Full Address Enable 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode (Continued on next page) 839 Full address mode (cont) Bit : 7 DTME1 0 R/W 6 DTE1 0 R/W 5 DTME0 0 R/W 4 DTE0 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A Channel 0 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 0 Data Transfer Interrupt Enable A 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1 Data Transfer Interrupt Enable B 0 1 Transfer suspended interrupt disabled Transfer suspended interrupt enabled Channel 0 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0 Data Transfer Master Enable 0 1 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Data transfer enabled Channel 1 Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0 Data Transfer Master Enable 0 1 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt Data transfer enabled (Continued on next page) 840 Short address mode Bit : 15 FAE1 0 R/W 14 FAE0 0 R/W 13 SAE1 0 R/W 12 SAE0 0 R/W 11 DTA1B 0 R/W 10 DTA1A 0 R/W 9 DTA0B 0 R/W 8 DTA0A 0 R/W DMABCRH : Initial value : Read/Write : Channel 0A Data Transfer Acknowledge 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled 1 Channel 0B Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1A Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 1B Data Transfer Acknowledge 0 1 Clearing of selected internal interrupt source at time of DMA transfer is disabled Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode Channel 1B Single Address Enable 0 1 Transfer in dual address mode Transfer in single address mode Channel 0 Full Address Enable 0 1 Short address mode Full address mode Channel 1 Full Address Enable 0 1 Short address mode Full address mode (Continued on next page) 841 Short address mode (cont) Bit : 7 DTE1B 0 R/W 6 DTE1A 0 R/W 5 DTE0B 0 R/W 4 DTE0A 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Channel 0A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled DMABCRL : Initial value : Read/Write : DTIE1B DTIE1A DTIE0B DTIE0A Channel 0B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1A Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 1B Data Transfer Interrupt Enable 0 1 Transfer end interrupt disabled Transfer end interrupt enabled Channel 0A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 0B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1A Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled Channel 1B Data Transfer Enable 0 1 Data transfer disabled Data transfer enabled 842 ISCRH -- IRQ Sense Control Register H ISCRL -- IRQ Sense Control Register L ISCRH Bit : 15 0 R/W 14 0 R/W 13 0 R/W 12 0 R/W H'FF2C H'FF2D Interrupt Controller Interrupt Controller 11 0 R/W 10 0 R/W 9 0 R/W 8 0 R/W IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : Read/Write : IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial value : Read/Write : IRQ3 to IRQ0 Sense Control IRQnSCB IRQnSCA 0 0 1 1 0 1 Interrupt Request Generation IRQn input low level Falling edge of IRQn input Rising edge of IRQn input Both falling and rising edges of IRQn input (n = 7 to 0) 843 IER--IRQ Enable Register Bit : 7 IRQ7E Initial value : Read/Write : 0 R/W 6 IRQ6E 0 R/W 5 IRQ5E 0 R/W 4 H'FF2E 3 IRQ3E 0 R/W 2 IRQ2E 0 R/W Interrupt Controller 1 IRQ1E 0 R/W 0 IRQ0E 0 R/W IRQ4E 0 R/W IRQn Enable 0 1 IRQn interrupt disabled IRQn interrupt enabled (n = 7 to 0) ISR--IRQ Status Register Bit : 7 IRQ7F Initial value : Read/Write : 0 R/(W)* 6 IRQ6F 0 R/(W)* 5 IRQ5F 0 R/(W)* 4 H'FF2F 3 IRQ3F 0 R/(W)* 2 IRQ2F 0 R/(W)* Interrupt Controller 1 IRQ1F 0 R/(W)* 0 IRQ0F 0 R/(W)* IRQ4F 0 R/(W)* Indicate the status of IRQ7 to IRQ0 interrupt requests Note: * Can only be written with 0 for flag clearing. 844 DTCERA to DTCERF--DTC Enable Registers Bit : 7 DTCE7 Initial value : Read/Write : 0 R/W 6 DTCE6 0 R/W 5 DTCE5 0 R/W 4 DTCE4 0 R/W H'FF30 to H'FF35 3 DTCE3 0 R/W 2 DTCE2 0 R/W 1 DTCE1 0 R/W 0 DTC DTCE0 0 R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] * When the DISEL bit is 1 and data transfer has ended *When the specified number of transfers have ended DTC activation by this interrupt is enabled [Holding condition] When the DISEL bit is 0 and the specified number of transfers have not ended 1 Correspondence between Interrupt Sources and DTCER Bits Register DTCERA DTCERB DTCERC DTCERD DTCERE DTCERF 7 IRQ0 -- TGI2A -- DMTEND0A -- 6 IRQ1 ADI TGI2B -- DMTEND0B -- 5 IRQ2 TGI0A TGI3A TGI5A DMTEND1A -- 4 IRQ3 TGI0B TGI3B TGI5B 3 IRQ4 TGI0C TGI3C -- 2 IRQ5 TGI0D TGI3D -- TXI0 -- 1 IRQ6 TGI1A TGI4A -- RXI1 -- 0 IRQ7 TGI1B TGI4B -- TXI1 -- DMTEND1B RXI0 -- -- 845 DTVECR--DTC Vector Register Bit : 7 0 R/(W)* 6 0 R/W 5 0 R/W 4 0 R/W H'FF37 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W DTC SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : Read/Write : Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing condition] When the DISEL bit is 0 and the specified number of transfers have not ended DTC software activation is enabled [Holding conditions] * When the DISEL bit is 1 and data transfer has ended * When the specified number of transfers have ended * During data transfer due to software activation 1 Note: * A value of 1 can always be written to the SWDTE bit, but 0 can only be written after 1 is read. 846 SBYCR--Standby Control Register Bit : 7 SSBY Initial value : Read/Write : 0 R/W 6 STS2 0 R/W 5 STS1 0 R/W 4 STS0 0 R/W H'FF38 3 OPE 1 R/W 2 -- 0 -- 1 -- 0 -- Power-Down State 0 -- 0 R/W Reserved Only 0 should be written to this bit Output Port Enable 0 In software standby mode, address bus and bus control signals are high-impedance In software standby mode, address bus and bus control signals retain output state 1 Standby Timer Select 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Software Standby 0 1 Transition to sleep mode after execution of SLEEP instruction Transition to software standby mode after execution of SLEEP instruction Standby time = 8192 states Standby time = 16384 states Standby time = 32768 states Standby time = 65536 states Standby time = 131072 states Standby time = 262144 states Reserved Standby time = 16 states 847 SYSCR--System Control Register Bit : 7 -- Initial value : Read/Write : 0 R/W 6 -- 0 -- 5 INTM1 0 R/W 4 INTM0 0 R/W H'FF39 3 NMIEG 0 R/W 2 -- 0 -- 1 -- 0 R/W 0 RAME 1 R/W MCU RAM Enable 0 1 On-chip RAM disabled On-chip RAM enabled Reserved Only 0 should be written to this bit NMI Input Edge Select 0 1 Falling edge Rising edge Interrupt Control Mode Selection 0 0 1 1 0 1 Interrupt control mode 0 Setting prohibited Interrupt control mode 2 Setting prohibited Reserved Only 0 should be written to this bit 848 SCKCR--System Clock Control Register Bit : 7 PSTOP Initial value : Read/Write : 0 R/W 6 -- 0 R/W 5 -- 0 -- 4 -- 0 -- 3 -- 0 -- H'FF3A 2 SCK2 0 R/W 1 SCK1 0 R/W Clock Pulse Generator 0 SCK0 0 R/W Bus Master Clock Select 0 0 0 1 1 0 1 1 0 0 1 1 o Clock Output Control PSTOP 0 1 Normal Operation o output Fixed high Sleep Mode o output Fixed high Software Standby Mode Fixed high Fixed high Hardware Standby Mode High impedance High impedance -- Bus master is in high-speed mode Medium-speed clock is o/2 Medium-speed clock is o/4 Medium-speed clock is o/8 Medium-speed clock is o/16 Medium-speed clock is o/32 -- 849 MDCR--Mode Control Register Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 0 -- 5 -- 0 -- 4 -- 0 -- H'FF3B 3 -- 0 -- 2 MDS2 --* R 1 MDS1 --* R 0 MCU MDS0 --* R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 MSTPCRH -- Module Stop Control Register H MSTPCRL -- Module Stop Control Register L MSTPCRH Bit : 15 0 14 0 13 1 12 1 11 1 10 1 9 1 8 1 H'FF3C H'FF3D Power-Down State Power-Down State MSTPCRL 7 1 6 1 5 1 4 1 3 1 2 1 1 1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Specifies module stop mode 0 1 Module stop mode cleared Module stop mode set Reserved Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 -- 0 R/W 4 -- 0 -- H'FF44 3 -- 0 -- 2 -- 0 -- 1 -- 0 -- 0 -- 0 -- Reserved Only 0 should be written to these bits 850 PCR--PPG Output Control Register Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF46 3 1 R/W 2 1 R/W 1 1 R/W 0 1 R/W PPG G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : Read/Write : Output Trigger for Pulse Output Group 0 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 1 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 2 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 3 0 0 1 1 0 1 Compare match in TPU channel 0 Compare match in TPU channel 1 Compare match in TPU channel 2 Compare match in TPU channel 3 851 PMR--PPG Output Mode Register Bit : 7 G3INV Initial value : Read/Write : 1 R/W 6 G2INV 1 R/W 5 G1INV 1 R/W 4 H'FF47 3 0 R/W 2 0 R/W 1 0 R/W 0 0 PPG G0INV 1 R/W G3NOV G2NOV G1NOV G0NOV R/W Pulse Output Group n Normal/Non-Overlap Operation Select 0 Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) Non-overlapping operation in pulse output group n (independent 1 and 0 output at compare match A or B in the selected TPU channel) n=3 to 0 Pulse Output Group n Direct/Inverted Output 0 Inverted output for pulse output group n (low-level output at pin for a 1 in PODRH) Direct output for pulse output group n (high-level output at pin for a 1 in PODRH) n=3 to 0 1 1 852 NDERH -- Next Data Enable Registers H NDERL -- Next Data Enable Registers L NDERH H'FF48 H'FF49 PPG PPG Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : Read/Write : Pulse Output Enable/Disable 0 1 NDERL Pulse outputs PO15 to PO8 are disabled Pulse outputs PO15 to PO8 are enabled Bit : 7 NDER7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W 2 NDER2 0 R/W 1 0 R/W 0 0 R/W NDER6 NDER5 NDER4 NDER3 NDER1 NDER0 Initial value : Read/Write : Pulse Output Enable/Disable 0 1 Pulse outputs PO7 to PO0 are disabled Pulse outputs PO7 to PO0 are enabled 853 PODRH -- Output Data Register H PODRL -- Output Data Register L PODRH H'FF4A H'FF4B PPG PPG Bit : 7 POD15 0 R/(W)* 6 POD14 0 R/(W)* 5 POD13 0 R/(W)* 4 POD12 0 R/(W)* 3 POD11 0 R/(W)* 2 POD10 0 R/(W)* 1 POD9 0 R/(W)* 0 POD8 0 R/(W)* Initial value : Read/Write : Stores output data for use in pulse output PODRL Bit : 7 POD7 0 R/(W)* 6 POD6 0 R/(W)* 5 POD5 0 R/(W)* 4 POD4 0 R/(W)* 3 POD3 0 R/(W)* 2 POD2 0 R/(W)* 1 POD1 0 R/(W)* 0 POD0 0 R/(W)* Initial value : Read/Write : Stores output data for use in pulse output Note: * A bit that has been set for pulse output by NDER is read-only. 854 NDRH--Next Data Register H H'FF4C (FF4E) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4C Bit : 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Initial value : Read/Write : Stores the next data for pulse output groups 3 and 2 (b) Address: H'FF4E Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : Read/Write : (2) When pulse output group output triggers are different (a) Address: H'FF4C Bit : 7 NDR15 0 R/W 6 NDR14 0 R/W 5 NDR13 0 R/W 4 NDR12 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : Read/Write : Stores the next data for pulse output group 3 (b) Address: H'FF4E Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR11 0 R/W 2 NDR10 0 R/W 1 NDR9 0 R/W 0 NDR8 0 R/W Initial value : Read/Write : Stores the next data for pulse output group 2 855 NDRL--Next Data Register L H'FF4D (FF4F) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4D Bit : 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Initial value : Read/Write : Stores the next data for pulse output groups 1 and 0 (b) Address: H'FF4F Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : Read/Write : (2) When pulse output group output triggers are different (a) Address: H'FF4D Bit : 7 NDR7 0 R/W 6 NDR6 0 R/W 5 NDR5 0 R/W 4 NDR4 0 R/W 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- Initial value : Read/Write : Stores the next data for pulse output group 1 (b) Address: H'FF4F Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 NDR3 0 R/W 2 NDR2 0 R/W 1 NDR1 0 R/W 0 NDR0 0 R/W Initial value : Read/Write : Stores the next data for pulse output group 0 856 PORT1--Port 1 Register Bit : 7 P17 Initial value : Read/Write : --* R 6 P16 --* R 5 P15 --* R 4 P14 --* R H'FF50 3 P13 --* R 2 P12 --* R 1 P11 --* R Port 1 0 P10 --* R State of port 1 pins Note: * Determined by the state of pins P17 to P10. PORT2--Port 2 Register Bit : 7 P27 Initial value : Read/Write : --* R 6 P26 --* R 5 P25 --* R 4 P24 --* R H'FF51 3 P23 --* R 2 P22 --* R 1 P21 --* R Port 2 0 P20 --* R State of port 2 pins Note: * Determined by the state of pins P27 to P20. PORT3--Port 3 Register Bit : 7 -- Read/Write : -- 6 -- -- 5 P35 --* R 4 P34 --* R H'FF52 3 P33 --* R 2 P32 --* R 1 P31 --* R Port 3 0 P30 --* R Initial value : Undefined Undefined State of port 3 pins Note: * Determined by the state of pins P35 to P30. 857 PORT4--Port 4 Register Bit : 7 P47 Initial value : Read/Write : --* R 6 P46 --* R 5 P45 --* R 4 P44 --* R H'FF53 3 P43 --* R 2 P42 --* R 1 P41 --* R Port 4 0 P40 --* R State of port 4 pins Note: * Determined by the state of pins P47 to P40. PORT5--Port 5 Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF54 3 P53 --* R 2 P52 --* R 1 P51 --* R Port 5 0 P50 --* R Initial value : Undefined Undefined Undefined Undefined State of port 5 pins Note: * Determined by the state of pins P53 to P50. PORT6--Port 6 Register Bit : 7 P67 Initial value : Read/Write : --* R 6 P66 --* R 5 P65 --* R 4 P64 --* R H'FF55 3 P63 --* R 2 P62 --* R 1 P61 --* R Port 6 0 P60 --* R State of port 6 pins Note: * Determined by the state of pins P67 to P60. 858 PORTA--Port A Register Bit : 7 PA7 Initial value : Read/Write : --* R 6 PA6 --* R 5 PA5 --* R 4 PA4 --* R H'FF59 3 PA3 --* R 2 PA2 --* R 1 PA1 --* R Port A 0 PA0 --* R State of port A pins Note: * Determined by the state of pins PA7 to PA0. PORTB--Port B Register H'FF5A Port B [H8S/2351 Only] 2 PB2 --* R 1 PB1 --* R 0 PB0 --* R Bit : 7 PB7 --* R 6 PB6 --* R 5 PB5 --* R 4 PB4 --* R 3 PB3 --* R Initial value : Read/Write : State of port B pins Note: * Determined by the state of pins PB7 to PB0. PORTC--Port C Register H'FF5B Port C [H8S/2351 Only] 2 PC2 --* R 1 PC1 --* R 0 PC0 --* R Bit : 7 PC7 --* R 6 PC6 --* R 5 PC5 --* R 4 PC4 --* R 3 PC3 --* R Initial value : Read/Write : State of port C pins Note: * Determined by the state of pins PC7 to PC0. 859 PORTD--Port D Register H'FF5C Port D [H8S/2351 Only] 2 PD2 --* R 1 PD1 --* R 0 PD0 --* R Bit : 7 PD7 --* R 6 PD6 --* R 5 PD5 --* R 4 PD4 --* R 3 PD3 --* R Initial value : Read/Write : State of port D pins Note: * Determined by the state of pins PD7 to PD0. PORTE--Port E Register Bit : 7 PE7 Initial value : Read/Write : --* R 6 PE6 --* R 5 PE5 --* R 4 PE4 --* R H'FF5D 3 PE3 --* R 2 PE2 --* R 1 PE1 --* R Port E 0 PE0 --* R State of port E pins Note: * Determined by the state of pins PE7 to PE0. PORTF--Port F Register Bit : 7 PF7 Initial value : Read/Write : --* R 6 PF6 --* R 5 PF5 --* R 4 PF4 --* R H'FF5E 3 PF3 --* R 2 PF2 --* R 1 PF1 --* R Port F 0 PF0 --* R State of port F pins Note: * Determined by the state of pins PF7 to PF0. 860 PORTG--Port G Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 PG4 --* R H'FF5F 3 PG3 --* R 2 PG2 --* R 1 PG1 --* R Port G 0 PG0 --* R Initial value : Undefined Undefined Undefined State of port G pins Note: * Determined by the state of pins PG4 to PG0. P1DR--Port 1 Data Register Bit : 7 P17DR Initial value : Read/Write : 0 R/W 6 P16DR 0 R/W 5 P15DR 0 R/W 4 H'FF60 3 P13DR 0 R/W 2 P12DR 0 R/W 1 P11DR 0 R/W Port 1 0 P10DR 0 R/W P14DR 0 R/W Stores output data for port 1 pins (P17 to P10) P2DR--Port 2 Data Register Bit : 7 P27DR Initial value : Read/Write : 0 R/W 6 P26DR 0 R/W 5 P25DR 0 R/W 4 H'FF61 3 P23DR 0 R/W 2 P22DR 0 R/W 1 P21DR 0 R/W Port 2 0 P20DR 0 R/W P24DR 0 R/W Stores output data for port 2 pins (P27 to P20) 861 P3DR--Port 3 Data Register Bit : 7 -- Read/Write : -- 6 -- -- 5 P35DR 0 R/W 4 H'FF62 3 P33DR 0 R/W 2 P32DR 0 R/W 1 P31DR 0 R/W Port 3 0 P30DR 0 R/W P34DR 0 R/W Initial value : Undefined Undefined Stores output data for port 3 pins (P35 to P30) P5DR--Port 5 Data Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 -- -- H'FF64 3 P53DR 0 R/W 2 P52DR 0 R/W 1 P51DR 0 R/W 0 Port 5 P50DR 0 R/W Initial value : Undefined Undefined Undefined Undefined Stores output data for port 5 pins (P53 to P50) P6DR--Port 6 Data Register Bit : 7 P67DR Initial value : Read/Write : 0 R/W 6 P66DR 0 R/W 5 P65DR 0 R/W 4 H'FF65 3 P63DR 0 R/W 2 P62DR 0 R/W 1 P61DR 0 R/W Port 6 0 P60DR 0 R/W P64DR 0 R/W Stores output data for port 6 pins (P67 to P60) 862 PADR--Port A Data Register Bit : 7 PA7DR Initial value : Read/Write : 0 R/W 6 PA6DR 0 R/W 5 PA5DR 0 R/W 4 H'FF69 3 PA3DR 0 R/W 2 PA2DR 0 R/W 1 PA1DR 0 R/W Port A 0 PA0DR 0 R/W PA4DR 0 R/W Stores output data for port A pins (PA7 to PA0) PBDR--Port B Data Register H'FF6A Port B [H8S/2351 Only] 2 PB2DR 0 R/W 1 PB1DR 0 R/W 0 PB0DR 0 R/W Bit : 7 PB7DR 0 R/W 6 PB6DR 0 R/W 5 PB5DR 0 R/W 4 PB4DR 0 R/W 3 PB3DR 0 R/W Initial value : Read/Write : Stores output data for port B pins (PB7 to PB0) PCDR--Port C Data Register H'FF6B Port C [H8S/2351 Only] 2 PC2DR 0 R/W 1 0 R/W 0 0 R/W Bit : 7 PC7DR 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PC6DR PC5DR PC4DR PC3DR PC1DR PC0DR Initial value : Read/Write : Stores output data for port C pins (PC7 to PC0) 863 PDDR--Port D Data Register H'FF6C Port D [H8S/2351 Only] 2 PD2DR 0 R/W 1 0 R/W 0 0 R/W Bit : 7 PD7DR 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PD6DR PD5DR PD4DR PD3DR PD1DR PD0DR Initial value : Read/Write : Stores output data for port D pins (PD7 to PD0) PEDR--Port E Data Register Bit : 7 PE7DR Initial value : Read/Write : 0 R/W 6 PE6DR 0 R/W 5 PE5DR 0 R/W 4 H'FF6D 3 PE3DR 0 R/W 2 PE2DR 0 R/W 1 PE1DR 0 R/W Port E 0 PE0DR 0 R/W PE4DR 0 R/W Stores output data for port E pins (PE7 to PE0) PFDR--Port F Data Register Bit : 7 PF7DR Initial value : Read/Write : 0 R/W 6 PF6DR 0 R/W 5 PF5DR 0 R/W 4 H'FF6E 3 PF3DR 0 R/W 2 PF2DR 0 R/W 1 PF1DR 0 R/W Port F 0 PF0DR 0 R/W PF4DR 0 R/W Stores output data for port F pins (PF7 to PF0) 864 PGDR--Port G Data Register Bit : 7 -- Read/Write : -- 6 -- -- 5 -- -- 4 0 R/W H'FF6F 3 0 R/W 2 0 R/W 1 0 R/W Port G 0 0 R/W PG4DR PG3DR PG2DR PG1DR PG0DR Initial value : Undefined Undefined Undefined Stores output data for port G pins (PG4 to PG0) PAPCR--Port A MOS Pull-Up Control Register H'FF70 Port A [H8S/2351 Only] 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port A on a bit-by-bit basis PBPCR--Port B MOS Pull-Up Control Register H'FF71 Port B [H8S/2351 Only] 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port B on a bit-by-bit basis 865 PCPCR--Port C MOS Pull-Up Control Register H'FF72 Port C [H8S/2351 Only] 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis PDPCR--Port D MOS Pull-Up Control Register H'FF73 Port D [H8S/2351 Only] 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port D on a bit-by-bit basis PEPCR--Port E MOS Pull-Up Control Register H'FF74 Port E [H8S/2351 Only] 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : Read/Write : Controls the MOS input pull-up function incorporated into port E on a bit-by-bit basis 866 P3ODR--Port 3 Open Drain Control Register Bit : 7 -- Read/Write : -- 6 -- -- 5 0 R/W 4 0 R/W H'FF76 3 0 R/W 2 0 R/W 1 0 R/W Port 3 0 0 R/W P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : Undefined Undefined Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR--Port A Open Drain Control Register H'FF77 Port A [H8S/2351 Only] 2 0 R/W 1 0 R/W 0 0 R/W Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W 3 0 R/W PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : Read/Write : Controls the PMOS on/off status for each port A pin (PA7 to PA0) 867 SMR0--Serial Mode Register 0 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI0 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected o clock o/4 clock o/16 clock o/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode 868 SMR0--Serial Mode Register 0 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF78 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 0 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 o clock o/4 clock o/16 clock o/64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Interval for transfer of one bit 869 BRR0--Bit Rate Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF79 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 13.2.8, Bit Rate Register (BRR), for details. 870 SCR0--Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI0 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled 871 SCR0--Serial Control Register 0 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF7A 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 0 SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled 872 TDR0--Transmit Data Register 0 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 H'FF7B 3 1 R/W SCI0, Smart Card Interface 0 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : R/W Stores data for serial transmission 873 SSR0--Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI0 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing condition] * When 0 is written to RDRF after reading RDRF = 1 * When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. 874 SSR0--Serial Status Register 0 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF7C 1 MPB 0 R 0 MPBT 0 R/W Smart Card Interface 0 Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received Transmit End 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 1 Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing condition] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS = 1 [Setting condition] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing condition] * When 0 is written to RDRF after reading RDRF = 1 * When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. 875 RDR0--Receive Data Register 0 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF7D 3 0 R SCI0, Smart Card Interface 0 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR0--Smart Card Mode Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 H'FF7E 2 SINV 0 R/W SCI0, Smart Card Interface 0 1 -- 1 -- 0 SMIF 0 R/W SDIR 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 876 SMR1--Serial Mode Register 1 Bit : 7 C/A Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W SCI1 Clock Select 0 0 1 1 0 1 Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Parity bit addition and checking disabled Parity bit addition and checking enabled Even parity Odd parity 1 stop bit 2 stop bits Multiprocessor function disabled Multiprocessor format selected o clock o/4 clock o/16 clock o/64 clock Character Length 0 1 8-bit data 7-bit data* Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted. Asynchronous Mode/Synchronous Mode Select 0 1 Asynchronous mode Synchronous mode 877 SMR1--Serial Mode Register 1 Bit : 7 GM Initial value : Read/Write : 0 R/W 6 CHR 0 R/W 5 PE 0 R/W 4 O/E 0 R/W H'FF80 3 STOP 0 R/W 2 MP 0 R/W Smart Card Interface 1 1 CKS1 0 R/W Clock Select 0 0 1 1 0 1 o clock o/4 clock o/16 clock o/64 clock 0 CKS0 0 R/W Multiprocessor Mode 0 1 Stop Bit Length 0 1 Parity Mode 0 1 Parity Enable 0 1 Setting prohibited Parity bit addition and checking enabled Even parity Odd parity Setting prohibited 2 stop bits Multiprocessor function disabled Setting prohibited Character Length 0 1 GSM Mode 0 Normal smart card interface mode operation * TEND flag generated 12.5 etu after beginning of start bit * Clock output on/off control only GSM mode smart card interface mode operation * TEND flag generated 11.0 etu after beginning of start bit * Fixed high/low-level control possible (set in SCR) in addition to clock output on/off control 8-bit data Setting prohibited 1 Note: etu (Elementary Time Unit): Interval for transfer of one bit 878 BRR1--Bit Rate Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF81 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Sets the serial transfer bit rate Note: See section 13.2.8, Bit Rate Register (BRR), for details. 879 SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable 0 0 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode 0 CKE0 0 R/W SCI1 Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Internal clock/SCK pin functions as serial clock output External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input External clock/SCK pin functions as clock input*2 External clock/SCK pin functions as serial clock input 1 1 0 1 Notes: 1. Outputs a clock of the same frequency as the bit rate. 2. Inputs a clock with a frequency 16 times the bit rate. Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled 880 SCR1--Serial Control Register 1 Bit : 7 TIE Initial value : Read/Write : 0 R/W 6 RIE 0 R/W 5 TE 0 R/W 4 RE 0 R/W 3 MPIE 0 R/W 2 TEIE 0 R/W H'FF82 1 CKE1 0 R/W Clock Enable SMCR SMR 0 CKE0 0 R/W Smart Card Interface 1 SCR setting CKE0 SMIF C/A,GM CKE1 0 1 1 1 1 1 1 0 0 1 1 1 1 0 0 0 0 1 1 SCK pin function See SCI specification 0 1 0 1 0 1 Operates as port input pin Clock output as SCK output pin Fixed-low output as SCK output pin Clock output as SCK output pin Fixed-high output as SCK output pin Clock output as SCK output pin Transmit End Interrupt Enable 0 1 Transmit end interrupt (TEI) request disabled Transmit end interrupt (TEI) request enabled Multiprocessor Interrupt Enable 0 Multiprocessor interrupts disabled [Clearing conditions] * When the MPIE bit is cleared to 0 * When MPB= 1 data is received Multiprocessor interrupts enabled Receive interrupt (RXI) requests, receive error interrupt (ERI) requests, and setting of the RDRF, FER, and ORER flags in SSR are disabled until data with the multiprocessor bit set to 1 is received 1 Receive Enable 0 1 Reception disabled Reception enabled Transmit Enable 0 1 Transmission disabled Transmission enabled Receive Interrupt Enable 0 1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled Transmit Interrupt Enable 0 1 Transmit data empty interrupt (TXI) requests disabled Transmit data empty interrupt (TXI) requests enabled 881 TDR1--Transmit Data Register 1 Bit : 7 1 R/W 6 1 R/W 5 1 R/W 4 1 R/W H'FF83 3 1 R/W SCI1, Smart Card Interface 1 2 1 R/W 1 1 R/W 0 1 R/W Initial value : Read/Write : Stores data for serial transmission 882 SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 FER 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Multiprocessor Bit Transfer 0 1 SCI1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition] * When the TE bit in SCR is 0 * When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character [Clearing condition] When data with a 0 multiprocessor bit is received [Setting condition] When data with a 1 multiprocessor bit is received 1 Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Framing Error 0 1 [Clearing condition] When 0 is written to FER after reading FER = 1 [Setting condition] When the SCI checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing condition] * When 0 is written to RDRF after reading RDRF = 1 * When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. 883 SSR1--Serial Status Register 1 Bit : 7 TDRE Initial value : Read/Write : 1 R/(W)* 6 RDRF 0 R/(W)* 5 ORER 0 R/(W)* 4 ERS 0 R/(W)* 3 PER 0 R/(W)* 2 TEND 1 R H'FF84 1 MPB 0 R 0 MPBT 0 R/W Smart Card Interface 1 Multiprocessor Bit Transfer 0 1 Data with a 0 multiprocessor bit is transmitted Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 1 Transmit End 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting conditions] * On reset, or in standby mode or module stop mode * When the TE bit in SCR is 0 and the ERS bit is 0 * When TDRE = 1 and ERS = 0 (normal transmission) 2.5 etu after a 1-byte serial character is sent when GM = 0 * When TDRE = 1 and ERS = 0 (normal transmission) 1.0 etu after a 1-byte serial character is sent when GM = 1 [Clearing condition] When data with a 0 multiprocessor bit is received [Setting conditions] When data with a 1 multiprocessor bit is received 1 Note: etu: Elementary Time Unit (the time taken to transmit one bit) Parity Error 0 1 [Clearing condition] When 0 is written to PER after reading PER = 1 [Setting condition] When, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the O/E bit in SMR Error Signal Status 0 [Clearing condition] * On reset, or in standby mode or module stop mode * When 0 is written to ERS after reading ERS =1 [Setting conditions] When the error signal is sampled at the low level 1 Note: Clearing the TE bit in SCR to 0 does not affect the ERS flag, which retains its prior state. Overrun Error 0 1 [Clearing condition] When 0 is written to ORER after reading ORER = 1 [Setting condition] When the next serial reception is completed while RDRF = 1 Receive Data Register Full 0 [Clearing condition] * When 0 is written to RDRF after reading RDRF = 1 * When the DMAC or DTC is activated by an RXI interrupt and read data from RDR [Setting condition] When serial reception ends normally and receive data is transferred from RSR to RDR 1 Transmit Data Register Empty 0 [Clearing condition] * When 0 is written to TDRE after reading TDRE = 1 * When the DMAC or DTC is activated by a TXI interrupt and write data to TDR [Setting condition] * When the TE bit in SCR is 0 * When data is transferred from TDR to TSR and data can be written to TDR 1 Note: * Can only be written with 0 for flag clearing. 884 RDR1--Receive Data Register 1 Bit : 7 0 R 6 0 R 5 0 R 4 0 R H'FF85 3 0 R SCI1, Smart Card Interface 1 2 0 R 1 0 R 0 0 R Initial value : Read/Write : Stores received serial data SCMR1--Smart Card Mode Register 1 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 1 -- 4 -- 1 -- 3 SDIR 0 R/W H'FF86 2 SINV 0 R/W SCI1, Smart Card Interface 1 1 -- 1 -- 0 SMIF 0 R/W Smart Card Interface Mode Select 0 1 Smart Card interface function is disabled Smart Card interface function is enabled Smart Card Data Invert 0 1 TDR contents are transmitted as they are Receive data is stored in RDR as it is TDR contents are inverted before being transmitted Receive data is stored in RDR in inverted form Smart Card Data Direction 0 1 TDR contents are transmitted LSB-first Receive data is stored in RDR LSB-first TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first 885 ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL -- -- -- -- -- -- -- -- A/D Data Register AH A/D Data Register AL A/D Data Register BH A/D Data Register BL A/D Data Register CH A/D Data Register CL A/D Data Register DH A/D Data Register DL H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter Bit : 15 0 R 14 0 R 13 0 R 12 0 R 11 0 R 10 0 R 9 0 R 8 0 R 7 0 R 6 0 R 5 0 R 4 -- 0 R 3 -- 0 R 2 -- 0 R 1 -- 0 R 0 -- 0 R AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 -- Initial value : Read/Write : Stores the results of A/D conversion Analog Input Channel Group 0 AN0 AN1 AN2 AN3 Group 1 AN4 AN5 AN6 AN7 A/D Data Register ADDRA ADDRB ADDRC ADDRD 886 ADCSR--A/D Control/Status Register Bit : 7 ADF Initial value : Read/Write : 0 R/(W)* 6 ADIE 0 R/W 5 ADST 0 R/W 4 SCAN 0 R/W H'FF98 3 CKS 0 R/W Channel Select Group select CH2 0 Channel select CH1 0 1 1 0 1 CH0 0 1 0 1 0 1 0 1 Group Select 0 1 Scan Mode 0 1 Single mode Scan mode AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 A/D Converter 2 CH2 0 R/W 1 CH1 0 R/W 0 CH0 0 R/W Single Mode Group Mode AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 AN4 AN4, AN5 AN4 to AN6 AN4 to AN7 Conversion time= 266 states (max.) Conversion time= 134 states (max.) A/D Start 0 1 A/D conversion stopped * Single mode: A/D conversion is started. Cleared to 0 automatically when conversion ends * Scan mode: A/D conversion is started. Conversion continues sequentially on the selected channels until ADST is cleared to 0 by software, a reset, or transition to standby mode or module stop mode A/D Interrupt Enable 0 A/D End Flag 0 1 A/D conversion end interrupt (ADI) request disabled A/D conversion end interrupt (ADI) request enabled [Clearing conditions] * When 0 is written to the ADF flag after reading ADF = 1 * When the DTC is activated by an ADI interrupt, and ADDR is read [Setting conditions] * Single mode: When A/D conversion ends * Scan mode: When one round of conversion has been performed on all specified channels 1 Note: * Can only be written with 0 for flag clearing. 887 ADCR--A/D Control Register Bit : 7 TRGS1 Initial value : Read/Write : 0 R/W 6 TRGS0 0 R/W 5 -- 1 -- 4 -- 1 -- H'FF99 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- A/D Timer Trigger Select TRGS1 TRGS1 0 0 1 1 0 1 Description A/D conversion start by software is enabled A/D conversion start by TPU conversion start trigger is enabled -- A/D conversion start by external trigger pin (ADTRG) is enabled 888 DADR0--D/A Data Register 0 DADR1--D/A Data Register 1 Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFA4 H'FFA5 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W D/A D/A Initial value : Read/Write : Stores data for D/A conversion 889 DACR--D/A Control Register Bit : 7 DAOE1 Initial value : Read/Write : 0 R/W 6 DAOE0 0 R/W 5 DAE 0 R/W 4 -- 1 -- H'FFA6 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 -- 1 -- D/A D/A Output Enable 0 0 1 Analog output DA0 is disabled Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 1 Analog output DA1 is disabled Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAOE1 0 DAOE0 0 1 DAE * 0 Description Channel 0 and 1 D/A conversion disabled Channel 0 D/A conversion enabled Channel 1 D/A conversion disabled 1 1 0 0 Channel 0 and 1 D/A conversions enabled Channel 0 D/A conversion disabled Channel 1 D/A conversion enabled 1 1 * Channel 0 and 1 D/A conversion enabled Channel 0 and 1 D/A conversion enabled * : Don't care 890 TCSR--Timer Control/Status Register Bit : 7 OVF 6 WT/IT 0 R/W 5 TME 0 R/W 4 -- 1 -- 3 -- 1 -- H'FFBC (W) H'FFBC (R) 2 CKS2 0 R/W 1 CKS1 0 R/W 0 CKS0 0 R/W WDT Initial value : 0 Read/Write : R/(W)* Clock Select CKS2 CKS1 CKS0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Overflow period* (when o = 20 MHz) 819.2s 1.6ms 6.6ms 26.2ms 104.9ms 419.4ms 1.68s o/2 (initial value) 25.6s o/64 o/128 o/512 o/2048 o/8192 o/32768 o/131072 Timer Enable 0 1 Note: * The overflow period is the time from when TCNT starts counting up from H'00 until overflow occurs. TCNT is initialized to H'00 and halted TCNT counts Timer Mode Select 0 1 Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when OVF = 1, then writing 0 to OVF [Setting condition] Set when TCNT overflows from H'FF to H'00 in interval timer mode Interval timer mode: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows Watchdog timer mode: Generates the WDTOVF signal when TCNT overflows The method for writing to TCSR is different from that for general registers to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. Note: * Can only be written with 0 for flag clearing. 891 TCNT--Timer Counter Bit : 7 0 R/W 6 0 R/W 5 0 R/W 4 0 R/W H'FFBC (W) H'FFBD (R) 3 0 R/W 2 0 R/W 1 0 R/W 0 0 WDT Initial value : Read/Write : R/W RSTCSR--Reset Control/Status Register Bit : 7 WOVF Initial value : Read/Write : 0 R/(W)* 6 RSTE 0 R/W 5 RSTS 0 R/W 4 -- 1 -- H'FFBE (W) H'FFBF (R) 3 -- 1 -- 2 -- 1 -- 1 -- 1 -- 0 WDT -- 1 -- Reset Select 0 1 Reset Enable 0 1 Reset signal is not generated if TCNT overflows* Reset signal is generated if TCNT overflows Power-on reset Manual reset Note: * The modules H8S/2350 Series are not reset, but TCNT and TCSR in WDT are reset. Watchdog Timer Overflow Flag 0 1 [Clearing condition] Cleared by reading TCSR when WOVF = 1, then writing 0 to WOVF [Setting condition] Set when TCNT overflows (changed from H'FF to H'00) during watchdog timer operation Note: * Can only be written with 0 for flag clearing. The method for writing to RSTCSR is different from that for general registers to prevent accidental overwriting. For details see section 12.2.4, Notes on Register Access. 892 TSTR--Timer Start Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 CST5 0 R/W 4 CST4 0 R/W H'FFC0 3 CST3 0 R/W 2 CST2 0 R/W 1 CST1 0 R/W 0 CST0 0 R/W TPU Counter Start 0 1 TCNTn count operation is stopped TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained. If TIOR is written to when the CST bit is cleared to 0, the pin output level will be changed to the set initial output value. TSYR--Timer Synchro Register Bit : 7 -- Initial value : Read/Write : 0 -- 6 -- 0 -- 5 SYNC5 0 R/W 4 SYNC4 0 R/W H'FFC1 3 SYNC3 0 R/W 2 SYNC2 0 R/W 1 SYNC1 0 R/W 0 SYNC0 0 R/W TPU Timer Synchronization 0 1 TCNTn operates independently (TCNT presetting/ clearing is unrelated to other channels) TCNTn performs synchronous operation TCNT synchronous presetting/synchronous clearing is possible (n = 5 to 0) Notes: 1. To set synchronous operation, the SYNC bits for at least two channels must be set to 1. 2. To set synchronous clearing, in addition to the SYNC bit , the TCNT clearing source must also be set by means of bits CCLR2 to CCLR0 in TCR. 893 TCR0--Timer Control Register 0 Bit : 7 CCLR2 Initial value : Read/Write : 0 R/W 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 R/W H'FFD0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU0 CKEG1 CKEG0 Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Clock Edge 0 0 1 1 Counter Clear 0 0 0 1 1 0 1 1 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 TCNT clearing disabled TCNT cleared by TGRC compare match/input capture*2 TCNT cleared by TGRD compare match/input capture*2 TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation*1 -- Count at rising edge Count at falling edge Count at both edges Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input External clock: counts on TCLKD pin input Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1. 2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 894 TMDR0--Timer Mode Register 0 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 BFB 0 R/W 4 BFA 0 R/W H'FFD1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU0 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- * : Don't care Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0. 2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always be written to MD2. TGRA Buffer Operation 0 1 TGRA operates normally TGRA and TGRC used together for buffer operation TGRB Buffer Operation 0 1 TGRB operates normally TGRB and TGRD used together for buffer operation 895 TIOR0H--Timer I/O Control Register 0H Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFD2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU0 TGR0A I/O Control 0 0 0 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 1 1 0 0 1 1 0 1 1 0 0 0 TGR0A is input 1 capture * register * Capture input source is TIOCA0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock * : Don't care TGR0B Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match TGR0B is input capture register Capture input source is TIOCB0 pin Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock * : Don't care Note: *1. When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 1 TGR0B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * * 896 TIOR0L--Timer I/O Control Register 0L Bit : : Initial value : Read/Write : 7 IOD3 0 R/W 6 IOD2 0 R/W 5 IOD1 0 R/W 4 IOD0 0 R/W 3 IOC3 0 R/W 2 IOC2 0 R/W H'FFD3 1 IOC1 0 R/W 0 IOC0 0 R/W TPU0 TGR0C I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0C is input capture register Capture input source is TIOCC0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down 1/count clock * : Don't care TGR0C Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Note: When the BFA bit in TMDR0 is set to 1 and TGR0C is used as a buffer register, this setting is invalid and input capture/output compare is not generated. TGR0D I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR0D is input capture register Capture input source is TIOCD0 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at TCNT1 count-up/ source is channel count-down*1 1/count clock TGR0D Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match * : Don't care Note: When the BFB bit in TMDR0 is set to 1 and TGR0D is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 1 When bits TPSC2 to TPSC0 in TCR1 are set to B'000, and o/1 is used as the TCNT1 count clock, this setting is invalid and input capture is not generated. Note: When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register operates as a buffer register. 897 TIER0--Timer Interrupt Enable Register 0 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 -- 0 -- 4 TCIEV 0 R/W 3 H'FFD4 2 TGIEC 0 R/W 1 TGIEB 0 R/W 0 TGIEA 0 R/W TPU0 TGIED 0 R/W TGR Interrupt Enable A 0 1 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled TGR Interrupt Enable C 0 1 Interrupt requests (TGIC) by TGFC bit disabled Interrupt requests (TGIC) by TGFC bit enabled TGR Interrupt Enable D 0 1 Interrupt requests (TGID) by TGFD bit disabled Interrupt requests (TGID) by TGFD bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled 898 TSR0--Timer Status Register 0 Bit : 7 -- 1 -- 6 -- 1 -- 5 -- 0 -- 4 TCFV 0 R/(W)* 3 TGFD 0 R/(W)* 2 TGFC 0 R/(W)* H'FFD5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU0 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing condition] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing condition] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Input Capture/Output Compare Flag C 0 [Clearing condition] * When DTC is activated by TGIC interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFC after reading TGFC = 1 [Setting conditions] * When TCNT = TGRC while TGRC is functioning as output compare register * When TCNT value is transferred to TGRC by input capture signal while TGRC is functioning as input capture register 1 Input Capture/Output Compare Flag D 0 [Clearing condition] * When DTC is activated by TGID interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFD after reading TGFD = 1 [Setting conditions] * When TCNT = TGRD while TGRD is functioning as output compare register * When TCNT value is transferred to TGRD by input capture signal while TGRD is functioning as input capture register 1 Overflow Flag 0 1 [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 899 TCNT0--Timer Counter 0 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFD6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU0 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR0A--Timer General Register 0A TGR0B--Timer General Register 0B TGR0C--Timer General Register 0C TGR0D--Timer General Register 0D Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFD8 H'FFDA H'FFDC H'FFDE 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU0 TPU0 TPU0 TPU0 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 900 TCR1--Timer Control Register 1 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFE0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU1 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input Internal clock: counts on o/256 Counts on TCNT2 overflow/underflow Note: This setting is ignored when channel 1 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 1 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit in TSYR to 1. 901 TMDR1--Timer Mode Register 1 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FFE1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU1 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 1Phase counting mode 4 -- * : Don't care Notes: MD3 is a reserved bit. In a write, it should always be written with 0. 902 TIOR1--Timer I/O Control Register 1 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFE2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU1 TGR1A I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1A is input capture register Capture input source is TIOCA1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0A channel 0/TGR0A compare match/ compare match/ input capture input capture * : Don't care TGR1B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 0 0 0 1 1 1 * * * TGR1B is input capture register Capture input source is TIOCB1 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges Capture input Input capture at generation of source is TGR0C TGR0B compare match/input compare match/ capture input capture * : Don't care TGR1B Output disabled is output compare Initial output is register 0 output TGR1A Output disabled is output compare Initial output is register 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 903 TIER1--Timer Interrupt Enable Register 1 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- H'FFE4 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A TPU1 0 Interrupt requests (TGIA) by TGFA bit disabled 1 Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled 904 TSR1--Timer Status Register 1 Bit : 7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- H'FFE5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU1 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing condition] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing condition] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 905 TCNT1--Timer Counter 1 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFE6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU1 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR1A--Timer General Register 1A TGR1B--Timer General Register 1B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 H'FFE8 H'FFEA 8 1 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU1 TPU1 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 906 TCR2--Timer Control Register 2 Bit : 7 -- Initial value : Read/Write : 0 -- 6 CCLR1 0 R/W 5 CCLR0 0 R/W 4 0 R/W 3 0 H'FFF0 2 TPSC2 0 R/W 1 TPSC1 0 R/W 0 TPSC0 0 R/W TPU2 CKEG1 CKEG0 R/W Time Prescaler 0 0 0 1 1 0 1 1 0 0 1 1 0 1 Internal clock: counts on o/1 Internal clock: counts on o/4 Internal clock: counts on o/16 Internal clock: counts on o/64 External clock: counts on TCLKA pin input External clock: counts on TCLKB pin input External clock: counts on TCLKC pin input Internal clock: counts on o/1024 Note: This setting is ignored when channel 2 is in phase counting mode. Clock Edge 0 0 1 1 -- Count at rising edge Count at falling edge Count at both edges Note: This setting is ignored when channel 2 is in phase counting mode. Counter Clear 0 0 1 1 0 1 TCNT clearing disabled TCNT cleared by TGRA compare match/input capture TCNT cleared by TGRB compare match/input capture TCNT cleared by counter clearing for another channel performing synchronous clearing/synchronous operation* Note: * Synchronous operating setting is performed by setting the SYNC bit TSYR to 1. 907 TMDR2--Timer Mode Register 2 Bit : 7 -- Initial value : Read/Write : 1 -- 6 -- 1 -- 5 -- 0 -- 4 -- 0 -- H'FFF1 3 MD3 0 R/W 2 MD2 0 R/W 1 MD1 0 R/W 0 MD0 0 R/W TPU2 Mode 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * * * Normal operation Reserved PWM mode 1 PWM mode 2 Phase counting mode 1 Phase counting mode 2 Phase counting mode 3 Phase counting mode 4 -- * : Don't care Notes: MD3 is a reserved bit. In a write, it should always be written with 0. 908 TIOR2--Timer I/O Control Register 2 Bit : 7 IOB3 Initial value : Read/Write : 0 R/W 6 IOB2 0 R/W 5 IOB1 0 R/W 4 IOB0 0 R/W 3 IOA3 0 R/W 2 IOA2 0 R/W H'FFF2 1 IOA1 0 R/W 0 IOA0 0 R/W TPU2 TGR2A I/O Control 0 0 0 0 TGR2A is output 1 compare 0 register 1 1 0 0 1 1 0 1 1 * 0 0 TGR2A is input 1 capture * register Capture input source is TIOCA2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don't care TGR2B I/O Control 0 0 0 0 1 1 0 1 1 0 0 1 1 0 1 1 * 0 0 1 1 * TGR2B is input capture register Capture input source is TIOCB2 pin Output disabled Initial output is 1 output 0 output at compare match 1 output at compare match Toggle output at compare match Input capture at rising edge Input capture at falling edge Input capture at both edges * : Don't care TGR2B is output compare register Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match Output disabled Initial output is 0 output 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 909 TIER2--Timer Interrupt Enable Register 2 Bit : 7 TTGE Initial value : Read/Write : 0 R/W 6 -- 1 -- 5 TCIEU 0 R/W 4 TCIEV 0 R/W 3 -- 0 -- H'FFF4 2 -- 0 -- 1 TGIEB 0 R/W 0 TGIEA 0 R/W TGR Interrupt Enable A 0 1 TPU2 Interrupt requests (TGIA) by TGFA bit disabled Interrupt requests (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 1 Interrupt requests (TGIB) by TGFB bit disabled Interrupt requests (TGIB) by TGFB bit enabled Overflow Interrupt Enable 0 1 Interrupt requests (TCIV) by TCFV disabled Interrupt requests (TCIV) by TCFV enabled Underflow Interrupt Enable 0 1 Interrupt requests (TCIU) by TCFU disabled Interrupt requests (TCIU) by TCFU enabled A/D Conversion Start Request Enable 0 1 A/D conversion start request generation disabled A/D conversion start request generation enabled 910 TSR2--Timer Status Register 2 Bit : 7 TCFD 1 R 6 -- 1 -- 5 TCFU 0 R/(W)* 4 TCFV 0 R/(W)* 3 -- 0 -- 2 -- 0 -- H'FFF5 1 TGFB 0 R/(W)* 0 TGFA 0 R/(W)* TPU2 Initial value : Read/Write : Input Capture/Output Compare Flag A 0 [Clearing condition] * When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 * When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC is 1 * When 0 is written to TGFA after reading TGFA = 1 [Setting conditions] * When TCNT = TGRA while TGRA is functioning as output compare register * When TCNT value is transferred to TGRA by input capture signal while TGRA is functioning as input capture register 1 Input Capture/Output Compare Flag B 0 [Clearing condition] * When DTC is activated by TGIB interrupt while DISEL bit of MRB in DTC is 0 * When 0 is written to TGFB after reading TGFB = 1 [Setting conditions] * When TCNT = TGRB while TGRB is functioning as output compare register * When TCNT value is transferred to TGRB by input capture signal while TGRB is functioning as input capture register 1 Overflow Flag 0 1 Underflow Flag 0 1 Count Direction Flag 0 1 TCNT counts down TCNT counts up [Clearing condition] When 0 is written to TCFU after reading TCFU = 1 [Setting conditions] When the TCNT value underflows (changes from H'0000 to H'FFFF) [Clearing condition] When 0 is written to TCFV after reading TCFV = 1 [Setting conditions] When the TCNT value overflows (changes from H'FFFF to H'0000 ) Note: * Can only be written with 0 for flag clearing. 911 TCNT2--Timer Counter 2 Bit : 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 H'FFF6 7 0 6 0 5 0 4 0 3 0 2 0 1 0 TPU2 0 0 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter. TGR2A--Timer General Register 2A TGR2B--Timer General Register 2B Bit : 15 1 14 1 13 1 12 1 11 1 10 1 9 1 8 1 H'FFF8 H'FFFA 7 1 6 1 5 1 4 1 3 1 2 1 1 1 TPU2 TPU2 0 1 Initial value : Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W 912 Appendix C I/O Port Block Diagrams C.1 Port 1 Block Diagram Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C * WDR1 P1n RDR1 RPOR1 Legend WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 n = 0 or 1 Note: * Priority order: Output compare output/PWM output > DMA transfer acknowledge output > pulse output > DR output Figure C-1 (a) Port 1 Block Diagram (Pins P10 and P11) Internal data bus PPG module Pulse output enable Pulse output DMA controller DMA transfer acknowledge enable DMA transfer acknowledge TPU module Output compare output/ PWM output enable Output compare output/ PWM output Input capture input 913 Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n * RDR1 RPOR1 Input capture input External clock input Legend WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 n = 2, 3, 5, 7 Note: * Priority order: Output compare output/PWM output > pulse output > DR output Figure C-1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17) 914 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output Reset R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C WDR1 P1n * RDR1 RPOR1 Input capture input Legend WDDR1 : Write to P1DDR WDR1 : Write to P1DR RDR1 : Read P1DR RPOR1 : Read port 1 n = 4 or 6 Note: * Priority order: Output compare output/PWM output > pulse output > DR output Figure C-1 (c) Port 1 Block Diagram (Pins P14 and P16) Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output 915 C.2 Port 2 Block Diagram Reset R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C WDR2 P2n * RDR2 RPOR2 Input capture input Legend WDDR2 : Write to P2DDR WDR2 : Write to P2DR RDR2 : Read P2DR RPOR2 : Read port 2 n = 0 to 7 Note: * Priority order: Output compare output/PWM output > pulse output > DR output Figure C-2 Port 2 Block Diagram (Pin P2n) 916 Internal data bus PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output C.3 Port 3 Block Diagram Reset R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 P3n RPOR3 Legend WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR n = 0 or 1 Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (a) Port 3 Block Diagram (Pins P30 and P31) Internal data bus 917 Reset R Q D P3nDDR C *1 WDDR3 Reset P3n R Q D P3nDR C *2 WDR3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial receive data enable RDR3 RPOR3 Internal data bus Serial receive data Legend WDDR3 WDR3 WODR3 RDR3 RPOR3 RODR3 n = 2 or 3 : Write to P3DDR : Write to P3DR : Write to P3ODR : Read P3DR : Read port 3 : Read P3ODR Notes: 1. Output enable signal 2. Open drain control signal Figure C-3 (b) Port 3 Block Diagram (Pins P32 and P33) 918 Reset R Q D P3nDDR C WDDR3 *2 Reset R Q D P3nDR C WDR3 *3 Reset R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable P3n *1 RPOR3 Legend WDDR3 : Write to P3DDR WDR3 : Write to P3DR WODR3 : Write to P3ODR RDR3 : Read P3DR RPOR3 : Read port 3 RODR3 : Read P3ODR n = 4 or 5 Notes: 1. Priority order: Serial clock input > serial clock output > DR output 2. Output enable signal 3. Open drain control signal Figure C-3 (c) Port 3 Block Diagram (Pins P34 and P35) Internal data bus Serial clock input 919 C.4 Port 4 Block Diagram Internal data bus A/D converter module Analog input RPOR4 : Read port 4 n = 0 to 5 Internal data bus A/D converter module Analog input D/A converter module Output enable Analog output RPOR4 P4n Figure C-4 (a) Port 4 Block Diagram (Pins P40 to P45) RPOR4 P4n RPOR4 : Read port 4 n = 6 or 7 Figure C-4 (b) Port 4 Block Diagram (Pins P46 and P47) 920 C.5 Port 5 Block Diagram Reset R Q D P5nDDR C WDDR5 Reset P5n R Q D P5nDR C WDR5 RDR5 RPOR5 Legend WDDR5 : Write to P5DDR WDR5 : Write to P5DR RDR5 : Read P5DR RPOR5 : Read port 5 n = 0 to 2 Figure C-5 (a) Port 5 Block Diagram (Pins P50 to P52) Internal data bus 921 Reset R Q D P53DDR C WDDR5 Reset P53 R Q D P53DR C WDR5 RDR5 RPOR5 A/D converter A/D converter external trigger input : Write to P5DDR : Write to P5DR : Read P5DR : Read port 5 Legend WDDR5 WDR5 RDR5 RPOR5 Figure C-5 (b) Port 5 Block Diagram (Pin P53) 922 Internal data bus C.6 Port 6 Block Diagram Reset R Q D P60DDR C WDDR6 Mode 1/2*/3*/7* P60 Mode 4/5/6* Reset R Q D P60DR C WDR6 Internal data bus Bus controller Chip select DMA controller DMA request input RDR6 RPOR6 Legend WDDR6 WDR6 RDR6 RPOR6 : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure C-6 (a) Port 6 Block Diagram (Pin P60) 923 Reset R Q D P61DDR C WDDR6 Mode 1/2*/3*/7* P61 Mode 4/5/6* Reset R Q D P61DR C WDR6 RDR6 RPOR6 Legend WDDR6 : Write to P6DDR WDR6 : Write to P6DR RDR6 : Read P6DR RPOR6 : Read port 6 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure C-6 (b) Port 6 Block Diagram (Pin P61) 924 Internal data bus Bus controller Chip select DMA controller DMA transfer end enable DMA transfer end Reset R Q D P62DDR C WDDR6 Reset P62 R Q D P62DR C WDR6 RDR6 RPOR6 DMA controller DMA request input Legend WDDR6 : Write to P6DDR WDR6 : Write to P6DR RDR6 : Read P6DR RPOR6 : Read port 6 Figure C-6 (c) Port 6 Block Diagram (Pin P62) Internal data bus 925 Reset R Q D P63DDR C WDDR6 Reset R Q D P63DR C WDR6 DMA controller DMA transfer end enable DMA transfer end RDR6 P63 RPOR6 Legend WDDR6 WDR6 RDR6 RPOR6 : Write to P6DDR : Write to P6DR : Read P6DR : Read port 6 Figure C-6 (d) Port 6 Block Diagram (Pin P63) 926 Internal data bus Reset R Q D P6nDDR C WDDR6 Reset P6n R Q D P6nDR C WDR6 RDR6 RPOR6 Interrupt controller IRQ interrupt input Legend WDDR6 : Write to P6DDR WDR6 : Write to P6DR RDR6 : Read P6DR RPOR6 : Read port 6 n = 4 or 5 Figure C-6 (e) Port 6 Block Diagram (Pins P64 and P65) Internal data bus 927 Reset R Q D P6nDDR C WDDR6 Mode 1/2*/3*/7* P6n Mode 4/5/6* Reset R Q D P6nDR C WDR6 Internal data bus Bus controller Chip select Interrupt controller IRQ interrupt input RDR6 RPOR6 Legend WDDR6 : Write to P6DDR WDR6 : Write to P6DR RDR6 : Read P6DR RPOR6 : Read port 6 n = 6 or 7 Note: * Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure C-6 (f) Port 6 Block Diagram (Pins P66 and P67) 928 C.7 Port A Block Diagram H8S/2351 Reset R Q D PAnPCR C WPCRA RPCRA Mode 4/5*3 Reset S R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA PAn Mode 1/2/3/6/7 Mode 4/5 RDRA RPORA Legend WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR n = 0 to 3 Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority Figure C-7 (a-1) H8S/2351 Port A Block Diagram (Pins PA0 to PA 3) 929 Internal address bus Internal data bus H8S/2350 Mode 4/5*2 Reset S R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA Internal address bus Internal data bus PAn Mode 1 Mode 4/5 RDRA RPORA Legend WDDRA : Write to PADDR WDRA : Write to PADR RDRA : Read PADR RPORA : Read port A n = 0 to 3 Notes: 1. Output enable signal 2. Set priority Figure C-7 (a-2) H8S/2350 Port A Block Diagram (Pins PA0 to PA 3) 930 H8S/2351 Reset R Q D PA4PCR C WPCRA RPCRA Mode 4/5*3 Reset S R Q D PA4DDR C WDDRA *1 Reset R Q D PA4DR C WDRA *2 Reset R Q D PA4ODR C WODRA RODRA PA4 Mode 1/2/3/6/7 Mode 4/5 RDRA RPORA Interrupt controller Legend WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR IRQ interrupt input Notes: 1. Output enable signal 2. Open drain control signal 3. Set priority Figure C-7 (b-1) H8S/2351 Port A Block Diagram (Pin PA4) 931 Internal address bus Internal data bus H8S/2350 Mode 4/5*2 Reset Internal address bus Interrupt controller Legend WDDRA WDRA RDRA RPORA : Write to PADDR : Write to PADR : Read PADR : Read port A IRQ interrupt input WDDRA *1 Reset R Q D PA4DR C WDRA PA4 Mode 1 Mode 4/5 RDRA RPORA Notes: 1. Output enable signal 2. Set priority Figure C-7 (b-2) H8S/2350 Port A Block Diagram (Pin PA4) 932 Internal data bus S R Q D PA4DDR C H8S/2351 Reset R Q D PAnPCR C WPCRA RPCRA Reset R Q D PAnDDR C WDDRA *1 Reset R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA PAn Mode 1/2/3/6/7 Mode 4/5 RDRA RPORA Interrupt controller IRQ interrupt input Legend WDDRA : Write to PADDR WDRA : Write to PADR WODRA : Write to PAODR WPCRA : Write to PAPCR RDRA : Read PADR RPORA : Read port A RODRA : Read PAODR RPCRA : Read PAPCR n = 5 to 7 Notes: 1. Output enable signal 2. Open drain control signal Figure C-7 (c-1) H8S/2351 Port A Block Diagram (Pins PA5 to PA7) Internal address bus Internal data bus 933 H8S/2350 Reset R Q D PAnDDR C WDDRA * Reset R Q D PAnDR C WDRA PAn Mode 1 Mode 4/5 RDRA RPORA Interrupt controller IRQ interrupt input Legend WDDRA : Write to PADDR WDRA : Write to PADR RDRA : Read PADR RPORA : Read port A n = 5 to 7 Note: * Output enable signal Figure C-7 (c-2) H8S/2350 Port A Block Diagram (Pins PA5 to PA7) 934 Internal address bus Internal data bus C.8 Port B Block Diagram H8S/2351 Reset R Q D PBnPCR C WPCRB RPCRB Mode 1/4/5* Reset S R Q D PBnDDR C WDDRB Reset R Q D PBnDR C WDRB PBn Mode 3/7 Mode 1/2/4/5/6 RDRB RPORB Legend WDDRB : Write to PBDDR WDRB : Write to PBDR WPCRB : Write to PBPCR RDRB : Read PBDR RPORB : Read port B RPCRB : Read PBPCR n = 0 to 7 Note: * Set priority Figure C-8 (a) H8S/2351 Port B Block Diagram (Pin PBn) Internal address bus Internal data bus 935 H8S/2350 Internal address bus Internal data bus Mode 1/4/5 PBn Mode 1/4/5 n = 0 to 7 Figure C-8 (b) H8S/2350 Port B Block Diagram (Pin PBn) 936 C.9 Port C Block Diagram H8S/2351 Reset R Q D PCnPCR C WPCRC RPCRC Mode 1/4/5* Reset S R Q D PCnDDR C WDDRC Reset R Q D PCnDR C WDRC PCn Mode 3/7 Mode 1/2/4/5/6 RDRC RPORC Legend WDDRC : Write to PCDDR WDRC : Write to PCDR WPCRC : Write to PCPCR RDRC : Read PCDR RPORC : Read port C RPCRC : Read PCPCR n = 0 to 7 Note: * Set priority Figure C-9 (a) H8S/2351 Port C Block Diagram (Pin PC n) 937 Internal address bus Internal data bus H8S/2350 Internal address bus Internal data bus Mode 1/4/5 PCn Mode 1/4/5 n = 0 to 7 Figure C-9 (b) H8S/2350 Port C Block Diagram (Pin PCn) 938 C.10 Port D Block Diagram H8S/2351 Reset Internal upper data bus Internal lower data bus R Q D PDnPCR C WPCRD RPCRD Reset R Q D PDnDDR C WDDRD Reset R Q D PDnDR C WDRD External address write PDn Mode 3/7 Mode 1/2/4/5/6 External address upper write External address lower write RDRD RPORD Legend WDDRD : Write to PDDDR WDRD : Write to PDDR WPCRD : Write to PDPCR RDRD : Read PDDR RPORD : Read port D RPCRD : Read PDPCR n = 0 to 7 External address upper read External address lower read Figure C-10 (a) H8S/2351 Port D Block Diagram (Pin PD n) 939 H8S/2350 External address write Mode 1/4/5 PDn Internal upper data bus External address upper write External address lower write External address upper read External address lower read n = 0 to 7 Figure C-10 (b) H8S/2350 Port D Block Diagram (Pin PDn) 940 Internal lower data bus C.11 Port E Block Diagram H8S/2351 Reset Internal upper data bus Internal lower data bus R Q D PEnPCR C WPCRE RPCRE Reset R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn Mode 3/7 Mode 1/2/4/5/6 RDRE RPORE Legend WDDRE : Write to PEDDR WDRE : Write to PEDR WPCRE : Write to PEPCR RDRE : Read PEDR RPORE : Read port E RPCRE : Read PEPCR n = 0 to 7 External address lower read Figure C-11 (a) H8S/2351 Port E Block Diagram (Pin PEn) 941 H8S/2350 Reset Internal upper data bus Internal lower data bus R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE External address write PEn 8-bit bus mode 8-bit bus mode RDRE RPORE Legend WDDRE : Write to PEDDR WDRE : Write to PEDR RDRE : Read PEDR RPORE : Read port E n = 0 to 7 External address lower read Figure C-11 (b) H8S/2350 Port E Block Diagram (Pin PEn) 942 C.12 Port F Block Diagram Internal data bus Bus controller BRLE bit Bus request input Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Note: * Modes 2 and 6 only apply to the H8S/2351. Reset R Q D PF0DDR C Mode 1/2*/4/5/6* WDDRF Reset PF0 R Q D PF0DR C WDRF RDRF RPORF Figure C-12 (a) Port F Block Diagram (Pin PF0) 943 Reset R Q D PF1DDR C WDDRF Reset R Q D PF1DR C WDRF Mode 1/2*/4/5/6* PF1 RDRF RPORF Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Note: * Modes 2 and 6 only apply to the H8S/2351. Figure C-12 (b) Port F Block Diagram (Pin PF1) 944 Internal data bus Bus controller BRLE output Bus request acknowledge output Reset R Q D PF2DDR C WDDRF Reset Mode 1/2*/4/5/6* PF2 Mode 4/5/6* R Q D PF2DR C WDRF Mode 1/2*/4/5/6* Internal data bus Bus controller Wait enable Bus request output enable Bus request output Wait input LCAS output enable LCAS output RDRF RPORF Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Note: * Modes 2 and 6 only apply to the H8S/2351. Figure C-12 (c) Port F Block Diagram (Pin PF2) 945 Reset R Q D PF3DDR C WDDRF *2 PF3 *3 Reset R Q D PF3DR C WDRF *1 Internal data bus Bus controller LWR output RDRF RPORF Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode 3. H8S/2351: Mode 1/2/4/5/6 H8S/2350: 8-bit bus mode Figure C-12 (d) Port F Block Diagram (Pin PF3) 946 Reset R Q D PF4DDR C WDDRF *2 PF4 *3 Reset R Q D PF4DR C WDRF *1 Internal data bus Bus controller HWR output RDRF RPORF Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode 3. H8S/2351: Mode 1/2/4/5/6 H8S/2350: 8-bit bus mode Figure C-12 (e) Port F Block Diagram (Pin PF4) 947 Reset R Q D PF5DDR C WDDRF *2 PF5 *3 Reset R Q D PF5DR C WDRF *1 RDRF RPORF Legend WDDRF WDRF RDRF RPORF : Write to PFDDR : Write to PFDR : Read PFDR : Read port F Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode 3. H8S/2351: Mode 1/2/4/5/6 H8S/2350: 8-bit bus mode Figure C-12 (f) Port F Block Diagram (Pin PF5) 948 Internal data bus Bus controller RD output Reset R Q D PF6DDR C WDDRF *2 PF6 *3 Reset R Q D PF6DR C WDRF *1 RDRF RPORF Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Notes: 1. H8S/2351: Mode 1/2/4/5/6 H8S/2350: Mode 1/4/5 2. H8S/2351: Mode 3/7 H8S/2350: 8-bit bus mode 3. H8S/2351: Mode 1/2/4/5/6 H8S/2350: 8-bit bus mode Figure C-12 (g) Port F Block Diagram (Pin PF6) Internal data bus Bus controller AS output 949 Mode 1/2*2/4/5/6*2 Reset S*1 R Q D PF7DDR C WDDRF Reset PF7 R Q D PF7DR C WDRF RDRF RPORF Legend WDDRF : Write to PFDDR WDRF : Write to PFDR RDRF : Read PFDR RPORF : Read port F Notes: 1. Set priority 2. Modes 2 and 6 only apply to the H8S/2351. Figure C-12 (h) Port F Block Diagram (Pin PF7) 950 Internal data bus o C.13 Port G Block Diagram Reset R Q D PG0DDR C WDDRG Reset R Q D PG0DR C WDRG Mode 4/5/6* PG0 RDRG RPORG Legend WDDRG : Write to PGDDR WDRG : Write to PGDR RDRG : Read PGDR RPORG : Read port G Note: Mode 6 only applies to the H8S/2351. Figure C-13 (a) Port G Block Diagram (Pin PG0) Internal data bus Bus controller CAS enable CAS output 951 Reset R Q D PGnDDR C WDDRG Mode 1/2*/3*/7* PGn Mode 4/5/6* Reset R Q D PGnDR C WDRG Internal data bus Bus controller Chip select RDRG RPORG Legend WDDRG : Write to PGDDR WDRG : Write to PGDR RDRG : Read PGDR RPORG : Read port G n = 1, 2, 3 Note: Modes 2, 3, 6, and 7 only apply to the H8S/2351. Figure C-13 (b) Port G Block Diagram (Pins PG1 to PG3) 952 H8S/2351 Reset Mode Mode 1/4/5 2/3/6/7 WDDRG Reset Mode 3/7 PG4 Mode 1/2/4/5/6 R Q D PG4DR C WDRG RDRG RPORG Legend WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C-13 (c-1) H8S/2351 Port G Block Diagram (Pin PG4) Internal data bus Bus controller Chip select S R Q D PG4DDR C 953 H8S/2350 Reset Mode 1/4/5 WDDRG Reset R Q D PG4DR C WDRG PG4 Mode 1/4/5 RDRG RPORG Legend WDDRG WDRG RDRG RPORG : Write to PGDDR : Write to PGDR : Read PGDR : Read port G Figure C-13 (c-2) H8S/2350 Port G Block Diagram (Pin PG4) 954 Internal data bus Bus controller Chip select S R Q D PG4DDR C Appendix D Pin States D.1 Port States in Each Mode [H8S/2351] Table D-1 I/O Port States in Each Processing State (H8S/2351) Program Execution State Sleep Mode I/O port I/O port I/O port Input port I/O port I/O port I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 I/O port Address output MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 Port 4 Port 5 P65 to P62 P67/CS7 P66/CS6 P61/CS5 P60/CS4 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 7 1 to 3, 7 4 to 6 PowerOn Reset T T T T T T T T Manual Reset kept kept kept T kept kept kept kept Hardware Software Standby Standby Mode Mode T T T T T T T T kept kept kept T kept kept kept Bus Release State kept kept kept T kept kept kept [DDR * OPE = 0] T T [DDR * OPE = 1] H kept [OPE = 0] T [OPE = 1] kept kept T Port A 1 to 3, 7 4, 5 T L kept kept T T 6 T kept T [DDR * OPE = 0] T T [DDR * OPE = 1] kept [OPE = 0] T [OPE = 1] kept T [DDR = 0] Input port [DDR = 1] Address output Address output Port B 1, 4, 5 L kept T 2, 6 T kept T [DDR * OPE = 0] T T [DDR * OPE = 1] kept kept kept [DDR = 0] Input port [DDR = 1] Address output I/O port 3, 7 T kept T 955 Table D-1 I/O Port States in Each Processing State (H8S/2351) (cont) Program Execution State Sleep Mode Address output MCU Port Name Operating Pin Name Mode Port C 1, 4, 5 PowerOn Reset L Manual Reset kept Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] kept Bus Release State T 2, 6 T kept T [DDR * OPE = 0] T T [DDR * OPE = 1] kept kept T kept kept T kept [DDR = 0] Input port [DDR = 1] H [DDR = 0] Input port [DDR = 1] H [OPE = 0] T [OPE = 1] H kept kept T kept kept T kept [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output T [DDR = 0] Input port [DDR = 1] Address output I/O port Data bus I/O port I/O port Data bus I/O port [DDR = 0] Input port [DDR = 1] Clock output [DDR = 0] Input port [DDR = 1] Clock output AS, RD, HWR, LWR 3, 7 Port D 1, 2, 4 to 6 3, 7 Port E 1, 2, 8 bit 4 to 6 bus T T T T kept T* kept kept T* kept [DDR = 0] T [DDR = 1] Clock output kept T T T T T T T 16 bit T bus 3, 7 PF7/o 1, 2, 4 to 6 T Clock output 3, 7 T T PF6/AS PF5/RD PF4/HWR PF3/LWR 1, 2, 4 to 6 H H* T 3, 7 T kept T kept I/O port 956 Table D-1 I/O Port States in Each Processing State (H8S/2351) (cont) Program Execution State Sleep Mode [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS MCU Port Name Operating Pin Name Mode PF2/LCAS/ WAIT/ BREQO 1, 2, 4 to 6 PowerOn Reset T Manual Reset Hardware Software Standby Standby Mode Mode [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS kept [BRLE = 0] kept [BRLE = 1] H kept [BRLE = 0] kept [BRLE = 1] T kept Bus Release State [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T [BREQOE + T WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] H* 3, 7 PF1/BACK 1, 2, 4 to 6 T T kept [BRLE = 0] kept [BRLE = 1] BACK kept [BRLE = 0] kept [BRLE = 1] BREQ kept [DDR = 0] T [DDR = 1] H* kept kept [DDR = 0] T [DDR = 1] H* T T kept L I/O port [BRLE = 0] I/O port [BRLE = 1] BACK I/O port [BRLE = 0] I/O port [BRLE = 1] BREQ I/O port [DDR = 0] Input port [DDR = 1] CS0 I/O port I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3 3, 7 PF0/BREQ 1, 2, 4 to 6 T T T T kept T 3, 7 PG 4/CS0 1, 4, 5 2, 6 T H T T T kept [DDR * OPE = 0] T T [DDR * OPE = 1] H kept kept kept kept 3, 7 PG 3/CS1 PG 2/CS2 PG 1/CS3 1 to 3, 7 4 to 6 T T T T T T [DDR * OPE = 0] T T [DDR * OPE = 1] H 957 Table D-1 I/O Port States in Each Processing State (H8S/2351) (cont) Program Execution State Sleep Mode I/O port [DRAME = 0] Input port [DRAME = 1] CAS MCU Port Name Operating Pin Name Mode PG0/CAS 1 to 3, 7 4 to 6 PowerOn Reset T T Manual Reset kept Hardware Software Standby Standby Mode Mode T kept [DRAME = 0] kept [OPE = 0] T [DRAME * OPE= 1] CAS Bus Release State kept T [DRAME = 0] T kept [DRAME = 1] H* Legend: H L T kept DDR OPE WAITE BRLE BREQOE DRAME LCASE : High level : Low level : High impedance : Input port becomes high-impedance, output port retains state : Data direction register : Output port enable : Wait input enable : Bus release enable : BREQO pin enable : DRAM space setting : DRAM space setting, CW2 = LCASS = 0 Note: * Indicates the state after completion of the executing bus cycle. 958 D.2 Port States in Each Mode [H8S/2350] Table D-2 I/O Port States in Each Processing State (H8S/2350) Program Execution State Sleep Mode I/O port I/O port I/O port Input port I/O port I/O port I/O port [DDR = 0] Input port [DDR = 1] CS7 to CS4 I/O port Address output MCU Port Name Operating Pin Name Mode Port 1 Port 2 Port 3 Port 4 Port 5 P65 to P62 P67/CS7 P66/CS6 P61/CS5 P60/CS4 1, 4, 5 1, 4, 5 1, 4, 5 1, 4, 5 1, 4, 5 1, 4, 5 1 4, 5 PowerOn Reset T T T T T T T T Manual Reset kept kept kept T kept kept kept kept Hardware Software Standby Standby Mode Mode T T T T T T T T kept kept kept T kept kept kept Bus Release State kept kept kept T kept kept kept [DDR * OPE = 0] T T [DDR * OPE = 1] H kept [OPE = 0] T [OPE = 1] kept [OPE = 0] T [OPE = 1] kept [OPE = 0] T [OPE = 1] kept T kept T [DDR = 0] Input port [DDR = 1] H kept T Port A 1 4, 5 T L kept kept T T Port B 1, 4, 5 L kept T T Address output Port C 1, 4, 5 L kept T T Address output Port D Port E 1, 5 1, 4, 5 8 bit bus T T T* kept T* [DDR = 0] T [DDR = 1] Clock output T T T T T kept T [DDR = 0] Input port [DDR = 1] Clock output Data bus I/O port Data bus [DDR = 0] Input port [DDR = 1] Clock output 16 bit T bus PF7/o 1, 4, 5 Clock output 959 Table D-2 I/O Port States in Each Processing State (H8S/2350) (cont) Program Execution State Sleep Mode AS, RD, HWR, LWR MCU Port Name Operating Pin Name Mode PF6/AS PF5/RD PF4/HWR PF3/LWR PF2/LCAS/ WAIT/ BREQO 1, 4, 5 PowerOn Reset H Manual Reset H* Hardware Software Standby Standby Mode Mode T [OPE = 0] T [OPE = 1] H [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] kept [WAITE = 1] T [LCASE = 1, OPE = 0] T [LCASE = 1, OPE = 1] LCAS [BRLE = 0] kept [BRLE = 1] H [BRLE = 0] kept [BRLE = 1] T Bus Release State T 1, 4, 5 T [BREQOE + T WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] H* [BREQOE + WAITE + LCASE = 0] kept [BREQOE = 1] BREQO [WAITE = 1] T [LCASE = 1] T [BREQOE + WAITE + LCASE= 0] I/O port [BREQOE = 1] BREQO [WAITE = 1] WAIT [LCASE = 1] LCAS PF1/BACK 1, 4, 5 T [BRLE = 0] kept [BRLE = 1] BACK [BRLE = 0] kept [BRLE = 1] BREQ [DDR = 0] T [DDR = 1] H* kept [DDR = 0] T [DDR = 1] H* T L [BRLE = 0] I/O port [BRLE = 1] BACK [BRLE = 0] I/O port [BRLE = 1] BREQ [DDR = 0] Input port [DDR = 1] CS0 I/O port [DDR = 0] Input port [DDR = 1] CS1 to CS3 PF0/BREQ 1, 2, 4 to 6 T T T PG 4/CS0 1, 4, 5 H T [DDR * OPE = 0] T T [DDR * OPE = 1] H kept kept PG 3/CS1 PG 2/CS2 PG 1/CS3 1 4, 5 T T T T [DDR * OPE = 0] T T [DDR * OPE = 1] H 960 Table D-2 I/O Port States in Each Processing State (H8S/2350) (cont) Program Execution State Sleep Mode I/O port [DRAME = 0] Input port [DRAME = 1] CAS MCU Port Name Operating Pin Name Mode PG 0/CAS 1 to 3, 7 4 to 6 PowerOn Reset T T Manual Reset kept Hardware Software Standby Standby Mode Mode T kept [DRAME = 0] kept [OPE = 0] T [DRAME * OPE= 1] CAS Bus Release State kept T [DRAME = 0] T kept [DRAME = 1] H* Legend: H : High level L : Low level T : High impedance kept : Input port becomes high-impedance, output port retains state DDR : Data direction register OPE : Output port enable WAITE : Wait input enable BRLE : Bus release enable BREQOE : BREQO pin enable DRAME : DRAM space setting LCASE: DRAM space setting, CW2 = LCASS = 0 Note: * Indicates the state after completion of the executing bus cycle. 961 Appendix E Pin States at Power-On Note that pin states at power-on depend on the state of the STBY pin and NMI pin. The case in which pins settle* from an indeterminate state at power-on, and the case in which pins settle* from the high-impedance state, are described below. After reset release, power-on reset exception handling is started. Note: * "Settle" refers to the pin states in a power-on reset in each MCU operating mode. E.1 When Pins Settle from an Indeterminate State at Power-On When the NMI pin level changes from low to high after powering on, the chip goes to the poweron reset state after a high level is detected at the NMI pin. While the chip detects a low level at the NMI pin, the manual reset state is established. The pin states are indeterminate during this interval. (Ports may output an internally determined value after powering on.) The NMI setup time (tNMIS) is necessary for the chip to detect a high level at the NMI pin. VCC tOSC1 STBY Manual reset Power-on reset NMI RES NMI = Low NMI = High RES = Low Figure E-1 When Pins Settle from an Indeterminate State at Power-On 962 E.2 When Pins Settle from the High-Impedance State at Power-On When the STBY pin level changes from low to high after powering on, the chip goes to the poweron reset state after a high level is detected at the STBY pin. While the chip detects a low level at the STBY pin, it is in the hardware standby mode. During this interval, the pins are in the highimpedance state. After detecting a high level at the STBY pin, the chip starts oscillation. VCC tOSC1 STBY Hardware standby mode Power-on reset NMI T1 RES Confirm t1min and tNMIS. NMI = High RES = Low Figure E-2 When Pins Settle from the High-Impedance State at Power-On 963 Appendix F Timing of Transition to and Recovery from Hardware Standby Mode Timing of Transition to Hardware Standby Mode (1) To retain RAM contents with the RAME bit set to 1 in SYSCR, drive the RES signal low at least 10 states before the STBY signal goes low, as shown below. RES must remain low until STBY signal goes low (delay from STBY low to RES high: 0 ns or more). STBY t110tcyc RES t20ns Figure F-1 Timing of Transition to Hardware Standby Mode (2) To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents do not need to be retained, RES does not have to be driven low as in (1). Timing of Recovery from Hardware Standby Mode Drive the RES signal low and the NMI signal high approximately 100 ns or more before STBY goes high to execute a power-on reset. STBY t100ns RES tOSC tNMIRH NMI Figure F-2 Timing of Recovery from Hardware Standby Mode 964 Appendix G Product Code Lineup Table G-1 H8S/2350 Series Product Code Lineup Product Type H8S/2351 Mask ROM Product Code HD6432351 Mark Code HD6432351TE HD6432351F H8S/2350 Mask ROM HD6412350 HD6412350TE HD6412350F Package (Hitachi Package Code) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 120-pin TFP (TFP-120) 128-pin FP (FP-128) 965 Appendix H Package Dimensions Figures H-1 and H-2 show the TFP-120 and FP-128 package dimensions of the H8S/2350 Series. Unit: mm 16.0 0.2 14 90 91 16.0 0.2 61 60 120 1 0.17 0.05 0.15 0.04 30 31 0.17 0.05 0.15 0.04 1.20 Max 1.00 0.07 M 1.2 0.4 1.0 0 - 8 0.5 0.1 0.10 Dimension including the plating thickness Base material dimension Figure H-1 TFP-120 Package Dimensions 966 0.10 0.10 22.0 0.2 20 102 103 65 64 Unit: mm 16.0 0.2 14 128 1 0.22 0.05 0.20 0.04 0.10 M 0.75 38 39 3.15 Max 0.5 0.17 0.05 0.15 0.04 2.70 1.0 0.75 +0.15 -0.10 Dimension including the plating thickness Base material dimension Figure H-2 FP-128 Package Dimensions 0.10 0.10 0.5 0.2 0 - 10 967 968 H8S/2350 Series Hardware Manual Publication Date: 1st Edition, May 1997 2nd Edition, December 1997 Published by: Electronic Devices Sales & Marketing Group Semiconductor & Integrated Circuits Hitachi, Ltd. Edited by: Technical Documentation Group Hitachi Kodaira Semiconductor Co., Ltd. Copyright (c) Hitachi, Ltd., 1997. All rights reserved. Printed in Japan. |
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